Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / Makefile.defines
# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: Makefile.defines
# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
#
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# The above named program is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
#
# ========== Copyright Header End ============================================
SUB_DIR.ss.lib.cpu = ss/lib/cpu
OBJ_DIR.ss.lib.cpu = $(OBJ_DIR)/$(SUB_DIR.ss.lib.cpu)
SRC_DIR.ss.lib.cpu = $(SUB_DIR.ss.lib.cpu)/src
BIN_DIR.ss.lib.cpu = $(SUB_DIR.ss.lib.cpu)/bin
GEN_H_FILES.ss.lib.cpu=\
SS_Assembly.h
H_FILES.ss.lib.cpu=\
SS_Types.h\
SS_State.h\
SS_Signal.h\
SS_Message.h\
SS_Chain.h\
SS_Memory.h\
SS_FastMemory.h\
SS_MsyncMemory.h\
SS_Prefetch.h\
SS_Prefetch.il\
SS_Ld128Atomic.h\
SS_Io.h\
SS_AddressMap.h\
SS_Access.h\
SS_Asi.h\
SS_AsiCtrReg.h\
SS_AsiInfo.h\
SS_AsiInfoTable.h\
SS_AsiMap.h\
SS_AsiSpace.h\
SS_BreakPoint.h\
SS_Decode.h\
SS_Node.h\
SS_Strand.h\
SS_Opcode.h\
SS_Instr.h\
SS_InstrCache.h\
SS_PidContext.h\
SS_Fpu.h\
SS_Registers.h\
SS_SnapShot.h\
SS_Tracer.h\
SS_Trap.h\
SS_Interrupt.h\
SS_Tsb.h\
SS_Tlb.h\
SS_Tte.h\
SS_Model.h\
SS_Cpu.h\
SS_V8Code.h\
MemoryTransaction.h\
utils.h
CC_FILES.ss.lib.cpu=\
SS_AsiCtrReg.cc\
SS_AsiInfoTable.cc\
SS_AsiMap.cc\
SS_AsiSpace.cc\
SS_BreakPoint.cc\
SS_Io.cc\
SS_AddressMap.cc\
SS_FastMemory.cc\
SS_MsyncMemory.cc\
SS_Node.cc\
SS_Signal.cc\
SS_Message.cc\
SS_Strand.cc\
SS_Tlb.cc\
SS_Tte.cc\
SS_Trap.cc\
SS_Interrupt.cc\
SS_Registers.cc\
SS_Fpu.cc\
SS_SnapShot.cc\
SS_Cpu.cc\
SS_Model.cc
S_FILES.ss.lib.cpu=\
SS_Ld128Atomic.s\
SS_V8Code.s
GEN_S_FILES.ss.lib.cpu=\
SS_Memory.s
INC_BUILD.ss.lib.cpu=\
$(H_FILES.ss.lib.cpu:%=$(INC_DIR)/%)
GEN_BUILD.ss.lib.cpu=\
$(GEN_H_FILES.ss.lib.cpu:%=$(INC_DIR)/%)
OBJ_BUILD.ss.lib.cpu=\
$(CC_FILES.ss.lib.cpu:%.cc=$(OBJ_DIR.ss.lib.cpu)/src/%.o)\
$(S_FILES.ss.lib.cpu:%.s=$(OBJ_DIR.ss.lib.cpu)/src/%.o)\
$(GEN_S_FILES.ss.lib.cpu:%.s=$(OBJ_DIR)/%.o)
GEN_INSTR.ss.lib.cpu=\
$(BIN_DIR.ss.lib.cpu)/SS_Instr.py\
$(BIN_DIR.ss.lib.cpu)/SS_Setup.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrSim.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrCti.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrCtr.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrAlu.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrLsu.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrFormat.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrFpop.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrFpu.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrVis.py\
$(BIN_DIR.ss.lib.cpu)/SS_InstrRun.py\
$(GEN_STATE.ss.lib.cpu)
GEN_STATE.ss.lib.cpu=\
$(BIN_DIR.ss.lib.cpu)/SS_State.py\
$(BIN_DIR.ss.lib.cpu)/SS_StateCtr.py\
$(BIN_DIR.ss.lib.cpu)/SS_StateAsr.py\
$(BIN_DIR.ss.lib.cpu)/SS_StatePrf.py\
$(BIN_DIR.ss.lib.cpu)/SS_StateHrf.py\
$(BIN_DIR.ss.lib.cpu)/SS_StateSrf.py