sam-t2/sam/cpus/vonk/ss/lib/cpu/bin/SS_Access.py

# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: SS_Access.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
#
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# The above named program is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
#
# ========== Copyright Header End ============================================


class SS_Access:
  def __init__(self,mode):
    self.mode = mode

  ILL_INST = 'i'        # Read or write causes ILLEGAL_INSTRUCTION trap
  PRIV_OPC = 'p'        # Read or write causes PRIVILEGED_OPCODE trap
  OK       = '-'        # Read or write is OK

  USER_WRITE = 5
  USER_READ  = 4
  PRIV_WRITE = 3
  PRIV_READ  = 2
  HPRV_WRITE = 1
  HPRV_READ  = 0

  def user_read_ill_inst(self):
    return self.mode[self.USER_READ]  == self.ILL_INST
  def user_read_priv_opc(self):
    return self.mode[self.USER_READ]  == self.PRIV_OPC
  def user_write_ill_inst(self):
    return self.mode[self.USER_WRITE] == self.ILL_INST
  def user_write_priv_opc(self):
    return self.mode[self.USER_WRITE] == self.PRIV_OPC

  def priv_read_ill_inst(self):
    return self.mode[self.PRIV_READ]  == self.ILL_INST
  def priv_read_priv_opc(self):
    return self.mode[self.PRIV_READ]  == self.PRIV_OPC
  def priv_write_ill_inst(self):
    return self.mode[self.PRIV_WRITE] == self.ILL_INST
  def priv_write_priv_opc(self):
    return self.mode[self.PRIV_WRITE] == self.PRIV_OPC

  def hprv_read_ill_inst(self):
    return self.mode[self.HPRV_READ]  == self.ILL_INST
  def hprv_read_priv_opc(self):
    return self.mode[self.HPRV_READ]  == self.PRIV_OPC
  def hprv_write_ill_inst(self):
    return self.mode[self.HPRV_WRITE] == self.ILL_INST
  def hprv_write_priv_opc(self):
    return self.mode[self.HPRV_WRITE] == self.PRIV_OPC

  def is_ro(self):
    return self.user_write_ill_inst() \
       and self.priv_write_ill_inst() \
       and self.hprv_write_ill_inst()

  def is_wo(self):
    return self.user_read_ill_inst() \
       and self.priv_read_ill_inst() \
       and self.hprv_read_ill_inst()

WO____ = SS_Access('i-iiii')
RO____ = SS_Access('-iiiii')
RW____ = SS_Access('--iiii')

WOWO__ = SS_Access('i-i-ip')    # asr softint_set and asr softint_clr
RORO__ = SS_Access('-i-ipi')
RWRO__ = SS_Access('---ipp')    # prf tick
RWRW__ = SS_Access('----pp')    # asr softint and all rw prf

WOWOWO = SS_Access('i-i-i-')
RORORO = SS_Access('-i-i-i')    # asr pc and asr tick
RWRORO = SS_Access('---i-i')    # asr stick
RWRWRW = SS_Access('------')

OOOOOO = SS_Access('iiiiii')    # can't use ______ :-(, this is used for simulator specifics