sam-t2/sam/cpus/vonk/ss/lib/cpu/bin/SS_InstrCtr.py

# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: SS_InstrCtr.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
#
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# The above named program is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
#
# ========== Copyright Header End ============================================

from SS_Instr import *
from SS_Setup import *

import SS_StateAsr
import SS_StatePrf
import SS_StateHrf

setup = setups[sys.argv[1]]

#============================================================================
# SS_rdctr(reg)
#============================================================================

class SS_rdctr(SS_InstrCpp):
  def __init__(self,reg):
    SS_InstrCpp.__init__(self,'rd'+reg.table+'_'+reg.name)
    self.out = ['rd','g0']
    self.reg = reg

  def run_exe_c(self,file):
    for out in self.out:
      self.c_code_beg_name(file,'run_exe_'+self.name+'_'+out)

      if self.check_tl_zero():
        file.write('  if (s->tl() == 0)\n')
        file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
        file.write('  uint32_t opc = i->opc();\n')
        self.ill_ibe(file,'  ')

      elif self.reg.name == 'tick' or self.reg.name == 'stick':
        if setup.product == 'N2':
          file.write('  if (s->'+self.reg.name+'.npt() && (s->sim_state.priv() == SS_Strand::SS_USER))\n')
          file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::PRIVILEGED_ACTION);\n')

      elif self.reg.name == 'gsr':
        file.write('  if (s->sim_state.fp_disabled())\n')
        file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::FP_DISABLED);\n')

      elif (setup.product in ['N2']) and self.reg.name == 'pic':
        file.write('  if (((%s_Strand*)s)->pcr.priv() && (s->sim_state.priv() == SS_Strand::SS_USER))\n' % (self.reg.class_prefix))
        file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::PRIVILEGED_ACTION);\n')

      if out == 'rd':
        if (setup.product in ['N2']) and (self.reg.name in ['tick_cmpr','stick_cmpr','hstick_cmpr']):
          file.write('  '+setup.product+'_Strand* _s = ('+setup.product+'_Strand*)s;\n')
          file.write('  if (_s->sim_state.ras_enabled())\n')
          file.write('  {\n')
          file.write('    '+setup.product+'_MemErrDetector& n2_med = ('+setup.product+'_MemErrDetector&) _s->mem_err_detector;\n')
          file.write('    SS_Trap::Type tt = n2_med.n2_tick_cmpr_precise_err_detector(s,N2_TickAccess::'+self.reg.name.upper()+'_INDX);\n')
          file.write('    if (tt != SS_Trap::NO_TRAP)\n')
          file.write('      return (s->trap)(pc,npc,s,i,tt);\n')
          file.write('  }\n')
        else:
          type = self.reg.class_prefix+'_Strand*'
          file.write('  '+type+' _s = ('+type+')s;\n')

        if self.reg.name == 'pc':
          file.write('  SS_Vaddr _pc = pc & _s->mask_pstate_am;\n')
          if setup.va_bits != 64:
            file.write('  _pc = (_pc << (64 - '+str(setup.va_bits)+')) >> (64 - '+str(setup.va_bits)+');\n')
          file.write('  _s->get_irf(i->rd) = _pc;\n')
        elif self.reg.name == 'tpc' or self.reg.name == 'tnpc':
          file.write('  SS_Vaddr va = _s->'+self.reg.name+'();\n')
          if setup.va_bits != 64:
            file.write('  va = (va << (64 - '+str(setup.va_bits)+')) >> (64 - '+str(setup.va_bits)+');\n')
          file.write('  _s->get_irf(i->rd) = va;\n')
        elif self.reg.name == 'tick':
          if setup.product == 'N2':
            file.write('  _s->get_irf(i->rd) = _s->tick();\n')
            file.write('#ifdef COMPILE_FOR_COSIM\n')
            file.write('  if (_s->ctr_sync)\n')
            file.write('  {\n')
            file.write('    std::map<SS_Registers::Index,uint64_t>::const_iterator x = _s->ctr_sync->find(SS_Registers::ASR_TICK);\n')
            file.write('    if (x != _s->ctr_sync->end())\n')
            file.write('      _s->get_irf(i->rd) = (((*x).second << 1) >> 1) | (s->tick.npt() << 63);\n')
            file.write('  }\n')
            file.write('#endif\n')
        elif self.reg.name == 'stick':
          if setup.product == 'N2':
            file.write('  _s->get_irf(i->rd) = _s->stick();\n')
            file.write('#ifdef COMPILE_FOR_COSIM\n')
            file.write('  if (_s->ctr_sync)\n')
            file.write('  {\n')
            file.write('    std::map<SS_Registers::Index,uint64_t>::const_iterator x = _s->ctr_sync->find(SS_Registers::ASR_STICK);\n')
            file.write('    if (x != _s->ctr_sync->end())\n')
            file.write('      _s->get_irf(i->rd) = (((*x).second << 1) >> 1) | (s->stick.npt() << 63);\n')
            file.write('  }\n')
            file.write('#endif\n')
        elif self.reg.name == 'halt':
          file.write('  _s->get_irf(i->rd) = 0;\n')     # Why waist space in the state vector.
        elif self.reg.name == 'asi_reg':
          file.write('  _s->get_irf(i->rd) = _s->asi();\n')
        else:
          file.write('  _s->get_irf(i->rd) = _s->'+self.reg.name+'();\n')

          if self.reg.name == 'pcr' and (setup.product in ['N2']):
            file.write('#ifdef COMPILE_FOR_COSIM\n')
            file.write('  if (_s->ctr_sync)\n')
            file.write('  {\n')
            file.write('    std::map<SS_Registers::Index,uint64_t>::const_iterator x = _s->ctr_sync->find(SS_Registers::ASR_PCR);\n')
            file.write('    if (x != _s->ctr_sync->end())\n')
            file.write('      _s->get_irf(i->rd) = (*x).second;\n')
            file.write('  }\n')
            file.write('#endif\n')
          elif self.reg.name == 'pic' and (setup.product in ['N2']):
            file.write('#ifdef COMPILE_FOR_COSIM\n')
            file.write('  if (_s->ctr_sync)\n')
            file.write('  {\n')
            file.write('    std::map<SS_Registers::Index,uint64_t>::const_iterator x = _s->ctr_sync->find(SS_Registers::ASR_PIC);\n')
            file.write('    if (x != _s->ctr_sync->end())\n')
            file.write('      _s->get_irf(i->rd) = (*x).second;\n')
            file.write('  }\n')
            file.write('#endif\n')

      else:
        if self.reg.name == 'pcr' and (setup.product in ['N2']):
          type = self.reg.class_prefix+'_Strand*'
          file.write('  '+type+' _s = ('+type+')s;\n')
        elif (setup.product in ['N2']) and (self.reg.name in ['tick_cmpr','stick_cmpr','hstick_cmpr']):
          file.write('  '+setup.product+'_Strand* _s = ('+setup.product+'_Strand*)s;\n')
          file.write('  if (_s->sim_state.ras_enabled())\n')
          file.write('  {\n')
          file.write('    '+setup.product+'_MemErrDetector& n2_med = ('+setup.product+'_MemErrDetector&) _s->mem_err_detector;\n')
          file.write('    SS_Trap::Type tt = n2_med.n2_tick_cmpr_precise_err_detector(s,N2_TickAccess::'+self.reg.name.upper()+'_INDX);\n')
          file.write('    if (tt != SS_Trap::NO_TRAP)\n')
          file.write('      return (s->trap)(pc,npc,s,i,tt);\n')
          file.write('  }\n')


      file.write('  s->npc = npc + 4;  return npc;\n')
      self.c_code_end(file)

  def run_dec_c(self,file):
    self.c_code_dec_beg_name(file,'run_dec_'+self.name)
    file.write('  i->flg = SS_Instr::NON_LSU;\n')

    file.write('  if (o.is_zero_13_0())\n')
    file.write('  {\n')

    if self.reg.access.user_read_ill_inst() or self.reg.access.user_read_priv_opc():
      file.write('    if (s->sim_state.priv() == SS_Strand::SS_USER)\n')
      if self.reg.access.user_read_ill_inst():
        file.write('      return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
      elif self.reg.access.user_read_priv_opc():
        file.write('    {\n')
        self.ill_ibe(file,'      ')
        file.write('      return (s->trap)(pc,npc,s,i,SS_Trap::PRIVILEGED_OPCODE);\n')
        file.write('    }\n')
      if self.reg.access.priv_read_ill_inst():
        file.write('    else if (s->sim_state.priv() == SS_Strand::SS_PRIV)\n')
        file.write('      return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
      file.write('\n')

    # for tt,tpc,tnpc,tstate,htstate we need to check current tl value,
    # hence we need to postpone checks until excecute time

    if not self.check_tl_zero():
      self.ill_ibe(file,'    ')
      file.write('\n')

    file.write('    if (o.get_rd_irf())\n')
    self.dec_r00(file,'    ','idx_exe_'+self.name+'_rd')
    file.write('    else\n')
    self.dec_000(file,'    ','idx_exe_'+self.name+'_g0')
    file.write('  }\n')
    file.write('  else\n')
    file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
    self.c_code_end(file)

  def exe_idx_s(self,file):
    for out in self.out:
      self.exe_idx_s_name(file,self.name+'_'+out)

  def gen_exe_tbl(self,file,mode):
    for out in self.out:
      if mode == 'trc':
        file.write('  trc_exe_r00, /* '+self.name+'_'+out+' */\n')
      elif mode == 'v8_run':
        file.write('  run_exe_'+self.name+'_'+out+',\n')
      else:
        file.write('  '+mode+'_exe_'+self.name+'_'+out+',\n')

  def check_tl_zero(self):
    return self.reg.name == 'tpc' or self.reg.name == 'tnpc' or \
           self.reg.name == 'tstate' or self.reg.name == 'tt' or self.reg.name == 'htstate'

#============================================================================
# SS_wrctr(reg)
#============================================================================

class SS_wrctr(SS_InstrCpp):
  def __init__(self,reg):
    SS_InstrCpp.__init__(self,'wr'+reg.table+'_'+reg.name)
    self.imm = ['i0','i1']
    self.reg = reg

  def run_exe_c(self,file):
    for imm in self.imm:
      self.c_code_beg_name(file,'run_exe_'+self.name+'_'+imm)
      self.fail_chkpt(file)

      if imm == 'i0':
        file.write('  uint64_t val = s->get_irf(i->rs1) ^ s->get_irf(i->rs2);\n')
      else:
        file.write('  uint64_t val = s->get_irf(i->rs1) ^ i->rs2;\n')

      if self.reg.name == 'asi_reg':
        file.write('  s->asi = val;\n')

      elif self.reg.name == 'tl':
        file.write('  s->tl_save();\n')
        file.write('  // make sure val is properly masked by tl register\n')
        file.write('  s->tl.set(val);\n')
        file.write('  val = s->tl();\n')
        file.write('  if (s->sim_state.priv() > SS_Strand::SS_PRIV)\n')
        file.write('    s->tl = (val > s->max_tl()) ? s->max_tl() : val;\n')
        file.write('  else\n')
        file.write('    s->tl = (val > s->max_ptl()) ? s->max_ptl() : val;\n')
        file.write('  s->tl_load();\n')
        file.write('  (s->sim_update)(s);\n')

      elif self.check_tl_zero():
        file.write('  if (s->tl() == 0)\n')
        file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
        file.write('  else\n')
        file.write('  {\n')
        file.write('    uint32_t opc = i->opc();\n')
        self.ill_ibe(file,'    ')
        file.write('    if (s->sim_state.priv() == SS_Strand::SS_USER)\n')
        file.write('      return (s->trap)(pc,npc,s,i,SS_Trap::PRIVILEGED_OPCODE);\n')
        type = self.reg.class_prefix+'_Strand*'
        file.write('    '+type+' _s = ('+type+')s;\n')
        if setup.va_bits < 64:
          sft = '(64-'+str(setup.va_bits)+')'
          file.write('    val = int64_t(val << '+sft+') >> '+sft+';\n')
        file.write('    _s->'+self.reg.name+'.set(val);\n')
        file.write('  }\n')

      elif self.reg.name == 'gl':
        file.write('  s->gl_save();\n')
        file.write('  // make sure val is properly masked by gl register\n')
        file.write('  s->gl.set(val);\n')
        file.write('  val = s->gl();\n')
        file.write('  if (s->sim_state.priv() > SS_Strand::SS_PRIV)\n')
        file.write('    s->gl = (val > s->max_gl()) ? s->max_gl() : val;\n')
        file.write('  else\n')
        file.write('    s->gl = (val > s->max_pgl()) ? s->max_pgl() : val;\n')
        file.write('  s->gl_load();\n')

      elif (setup.va_bits < 64) and (self.reg.name == 'tba' or self.reg.name == 'htba'):
        sft = '(64-'+str(setup.va_bits)+')'
        file.write('  s->'+self.reg.name+'.set(int64_t(val << '+sft+') >> '+sft+');\n')

      elif self.reg.name == 'cwp':
        file.write('  s->cwp_save();\n')
        file.write('  s->cwp.set(val % (s->max_wp() + 1));\n')
        file.write('  s->cwp_load();\n')

      elif self.reg.name == 'cansave' or self.reg.name == 'canrestore' \
        or self.reg.name == 'cleanwin' or self.reg.name == 'otherwin':
        file.write('  s->'+self.reg.name+'.set(val % (s->max_wp() + 1));\n')

      elif self.reg.name == 'fprs' or self.reg.name == 'pstate' or self.reg.name == 'hpstate':
        file.write('  s->'+self.reg.name+'.set(val);\n')
        file.write('  (s->sim_update)(s);\n')

      elif self.reg.name == 'pil':
        file.write('  s->pil.set(val);\n')
        file.write('  s->irq.check(s);\n')

      elif self.reg.name == 'softint':
        file.write('  s->softint.set(val);\n')
        file.write('  s->irq.update_softint(s);\n')

      elif self.reg.name == 'softint_set':
        file.write('  s->softint.set(s->softint() | val);\n')
        file.write('  s->irq.update_softint(s);\n')

      elif self.reg.name == 'softint_clr':
        file.write('  s->softint.set(s->softint() &~ val);\n')
        file.write('  s->irq.update_softint(s);\n')

      elif self.reg.name == 'hintp':
        file.write('  s->hintp.set(val);\n')
        file.write('  if (s->hintp.hsp())\n')
        file.write('    s->irq.raise(s,SS_Interrupt::BIT_HSTICK_MATCH);\n')
        file.write('  else\n')
        file.write('    s->irq.retract(SS_Interrupt::BIT_HSTICK_MATCH);\n')
        file.write('  if (s->hintp())\n')
        file.write('    s->irq.check(s);\n')

      elif self.reg.name == 'halt':
        # The halt sets running=false and let the strand wait
        # for an interrupt and then wakes it.
        file.write('  if (!s->softint.sm() && !s->softint.tm() && !s->hintp.hsp())\n')
        file.write('  {\n')
        file.write('    s->halted = true;\n')
        file.write('    if (!s->sim_state.cosim())\n')
        file.write('    {\n')
        file.write('      s->sim_state.running(false);\n')
        file.write('      if (s->change_running)\n')
        file.write('        (s->change_running)(s);\n')
        file.write('      s->running = false;\n')
        file.write('      s->msg.set_reenter_loop();\n')
        file.write('    }\n')
        file.write('  }\n')

      elif self.reg.name == 'gsr':
        file.write('  if (s->sim_state.fp_disabled())\n')
        file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::FP_DISABLED);\n')
        file.write('  s->gsr.set(val);\n')

      elif (setup.product in ['N2']) and self.reg.name == 'pic':
        file.write('  if (((%s_Strand*)s)->pcr.priv() && (s->sim_state.priv() == SS_Strand::SS_USER))\n' % (self.reg.class_prefix))
        file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::PRIVILEGED_ACTION);\n')
        type = self.reg.class_prefix+'_Strand*'
        file.write('  '+type+' _s = ('+type+')s;\n')
        file.write('  _s->'+self.reg.name+'.set(val);\n')

      elif (setup.product in ['N2']) and self.reg.name == 'pcr':
        file.write('  %s_Strand* n2 = (%s_Strand*)s;\n' % (self.reg.class_prefix, self.reg.class_prefix))
        file.write('  uint64_t ov0 = n2->pcr.ov0();\n')
        file.write('  uint64_t ov1 = n2->pcr.ov1();\n')
        file.write('  if (n2->sim_state.priv() > SS_Strand::SS_PRIV)\n')
        file.write('  {\n')
        file.write('    n2->pcr.set(val);\n')
        file.write('  }\n')
        file.write('  else\n')
        file.write('  {\n')
        file.write('    uint64_t ht = n2->pcr.ht();\n')
        file.write('    n2->pcr.set(val);\n')
        file.write('    n2->pcr.ht(ht);\n')
        file.write('  }\n')
        file.write('  n2->pcr.ov0(n2->pcr.ov0wr() ? n2->pcr.ov0() : ov0);\n')
        file.write('  n2->pcr.ov1(n2->pcr.ov1wr() ? n2->pcr.ov1() : ov1);\n')
        file.write('  n2->pcr.ov0wr(0).ov1wr(0);\n')

      elif self.reg.name == 'tick' or self.reg.name == 'stick':
        if setup.product in ['N2']:
          file.write('  s->stick.set(val);\n')
          file.write('  s->tick.set(val);\n')
        else:
          file.write('  s->'+self.reg.name+'.set(val);\n')

      elif (setup.product in ['N2']) and (self.reg.name in ['tick_cmpr','stick_cmpr','hstick_cmpr']):
        file.write('  '+setup.product+'_Strand* _s = ('+setup.product+'_Strand*)s;\n')
        file.write('  if (_s->sim_state.ras_enabled())\n')
        file.write('  {\n')
        file.write('    '+setup.product+'_MemErrDetector& n2_med = ('+setup.product+'_MemErrDetector&) _s->mem_err_detector;\n')
        file.write('    _s->tick_cmpr_array_ecc[N2_TickAccess::'+self.reg.name.upper()+'_INDX] = n2_med.n2_tick_cmpr_err_injector(s,val);\n')
        file.write('  }\n')
        file.write('  _s->'+self.reg.name+'.set(val);\n')

      else:
        type = self.reg.class_prefix+'_Strand*'
        file.write('  '+type+' _s = ('+type+')s;\n')
        file.write('  _s->'+self.reg.name+'.set(val);\n')

      file.write('  s->npc = npc + 4;  return npc;\n')
      self.c_code_end(file)

  def run_dec_c(self,file):
    self.c_code_dec_beg_name(file,'run_dec_'+self.name)
    file.write('  i->flg = SS_Instr::NON_LSU;\n')

    if self.reg.access.user_write_ill_inst() or self.reg.access.user_write_priv_opc():
      file.write('  if (s->sim_state.priv() == SS_Strand::SS_USER)\n')
      if self.reg.access.user_write_ill_inst():
        file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
      elif self.reg.access.user_write_priv_opc():
        file.write('  {\n')
        self.ill_ibe(file,'    ')
        file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::PRIVILEGED_OPCODE);\n')
        file.write('  }\n')
      if self.reg.access.priv_write_ill_inst():
        file.write('  else if (s->sim_state.priv() == SS_Strand::SS_PRIV)\n')
        file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')

    file.write('  if (o.get_i())\n')
    file.write('  {\n')
    if not self.check_tl_zero():
      self.ill_ibe(file,'    ')
    self.dec_0r13(file,'  ','idx_exe_'+self.name+'_i1')
    file.write('  }\n')
    file.write('  else if (o.is_zero_12_5())\n')
    file.write('  {\n')
    if not self.check_tl_zero():
      self.ill_ibe(file,'    ')
    self.dec_0rr(file,'  ','idx_exe_'+self.name+'_i0')
    file.write('  }\n')
    file.write('  else\n')
    file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
    self.c_code_end(file)

  def gen_exe_tbl(self,file,mode):
    for imm in self.imm:
      if mode == 'trc':
        if imm == 'i0':
          file.write('  trc_exe_0rr, /* '+self.name+'_'+imm+' */\n')
        else:
          file.write('  trc_exe_0r0, /* '+self.name+'_'+imm+' */\n')
      elif mode == 'v8_run':
        file.write('  run_exe_'+self.name+'_'+imm+',\n')
      else:
        file.write('  '+mode+'_exe_'+self.name+'_'+imm+',\n')

  def check_tl_zero(self):
    return self.reg.name == 'tpc' or self.reg.name == 'tnpc' or \
           self.reg.name == 'tstate' or self.reg.name == 'tt' or self.reg.name == 'htstate'

#============================================================================
# SS_membar()
#============================================================================

class SS_membar(SS_InstrCpp):
  def __init__(self):
    SS_InstrCpp.__init__(self,'membar')

  def run_exe_c(self,file):
    self.c_code_beg_name(file,'run_exe_membar')
    self.fail_chkpt(file)
    file.write('  s->npc = npc + 4;  return npc;\n')
    self.c_code_end(file)

  def run_dec_p(self):
    return ''

  def gen_exe_tbl(self,file,mode):
    self.gen_exe_passthrough(file,mode)


#============================================================================
# SS_stbar()
#============================================================================

class SS_stbar(SS_InstrCpp):
  def __init__(self):
    SS_InstrCpp.__init__(self,'stbar')

  def run_exe_c(self,file):
    self.c_code_beg_name(file,'run_exe_stbar')
    self.fail_chkpt(file)
    file.write('  s->npc = npc + 4;  return npc;\n')
    self.c_code_end(file)

  def run_dec_p(self):
    return ''

  def gen_exe_tbl(self,file,mode):
    self.gen_exe_passthrough(file,mode)


#============================================================================
# SS_rdasr15()
#============================================================================

class SS_rdasr15(SS_InstrCpp):
  def __init__(self):
    SS_InstrCpp.__init__(self,'rdasr15')

  def run_dec_c(self,file):
    self.c_code_dec_beg_name(file,'run_dec_'+self.name)
    file.write('  i->flg = SS_Instr::NON_LSU;\n')
    file.write('  if (o.get_rd() == 0)\n')
    file.write('  {\n')
    file.write('    if (o.is_zero_13_0())\n')
    file.write('    {\n')
    self.ill_ibe(file,'    ')
    self.dec_000(file,'    ','idx_exe_stbar')
    file.write('    }\n')
    file.write('    else if (o.get_i() && o.is_zero_12_7())\n')
    file.write('    {\n')
    self.ill_ibe(file,'      ')
    self.dec_007(file,'      ','idx_exe_membar')
    file.write('    }\n')
    file.write('    else\n')
    file.write('      return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
    file.write('  }\n')
    file.write('  else\n')
    file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
    self.c_code_end(file)

  def exe_idx_s(self,file):
    pass

  def gen_exe_tbl(self,file,mode):
    pass

#============================================================================
# SS_sir()
#============================================================================

class SS_sir(SS_InstrCpp):
  def __init__(self):
    SS_InstrCpp.__init__(self,'sir')

  def run_exe_c(self,file):
    self.c_code_beg_name(file,'run_exe_sir')
    file.write('  return (s->trap)(pc,npc,s,i,SS_Trap::SOFTWARE_INITIATED_RESET);\n')
    self.c_code_end(file)

  def run_dec_c(self,file):
    self.c_code_dec_beg_name(file,'run_dec_'+self.name)
    file.write('  i->flg = SS_Instr::NON_LSU;\n')
    file.write('  if (s->sim_state.priv() < SS_Strand::SS_HPRV)\n')
    file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
    file.write('  else if ((o.get_rs1() == 0) && o.get_i())\n')
    file.write('  {\n')
    if not setup.product in ['N2']:
      self.ill_ibe(file,'    ')
    self.dec_0013(file,'    ','idx_exe_sir')
    file.write('  }\n')
    file.write('  else\n')
    file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
    self.c_code_end(file)

  def gen_exe_tbl(self,file,mode):
    self.gen_exe_passthrough(file,mode)

#============================================================================
# ss_rdasr/ss_wrasr
#============================================================================

ss_rdasr = SS_InstrGroup('10_101000_rdasr',14,0x1f)
ss_wrasr = SS_InstrGroup('10_110000_wrasr',25,0x1f)

for i in range(0,32):
  if i == 15:
    ss_rdasr.append(SS_rdasr15())
    ss_rdasr.append(SS_membar())
    ss_rdasr.append(SS_stbar())
    ss_wrasr.append(SS_sir())
  else:
    r = SS_StateAsr.ctr_table.reg_at(i)

    if r == None or r.access.is_wo():
      ss_rdasr.append(SS_ill())
    else:
      ss_rdasr.append(SS_rdctr(r))

    if r == None or r.access.is_ro():
      ss_wrasr.append(SS_ill())
    else:
      ss_wrasr.append(SS_wrctr(r))


#============================================================================
# ss_rdprf/ss_wrprf
#============================================================================

ss_rdprf = SS_InstrGroup('10_101010_rdprf',14,0x1f)
ss_wrprf = SS_InstrGroup('10_110010_wrprf',25,0x1f)

for i in range(0,32):
  r = SS_StatePrf.ctr_table.reg_at(i)

  if r == None or r.access.is_wo():
    ss_rdprf.append(SS_ill())
  else:
    ss_rdprf.append(SS_rdctr(r))

  if r == None or r.access.is_ro():
    ss_wrprf.append(SS_ill())
  else:
    ss_wrprf.append(SS_wrctr(r))


#============================================================================
# ss_rdhrf/ss_wrhrf
#============================================================================

ss_rdhrf = SS_InstrGroup('10_101001_rdhrf',14,0x1f)
ss_wrhrf = SS_InstrGroup('10_110011_wrhrf',25,0x1f)

for i in range(0,32):
  r = SS_StateHrf.ctr_table.reg_at(i)

  if r == None or r.access.is_wo():
    ss_rdhrf.append(SS_ill())
  else:
    ss_rdhrf.append(SS_rdctr(r))

  if r == None or r.access.is_ro():
    ss_wrhrf.append(SS_ill())
  else:
    ss_wrhrf.append(SS_wrctr(r))