Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / bin / SS_InstrFpop.py
# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: SS_InstrFpop.py
# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
#
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# The above named program is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
#
# ========== Copyright Header End ============================================
from SS_Instr import *
#============================================================================
# SS_fpop base for the floating point operations
#============================================================================
class SS_fpop(SS_InstrAsm):
def __init__(self,opc):
SS_InstrAsm.__init__(self,opc)
self.opc = opc
def fpop_init(self,file):
self.s_code(file,'run_exe_')
self.ld_sim(file,'%g5')
self.st_fsr_cpu(file,'%fsr')
self.ld_fsr_run(file,'%fsr')
self.ld_gsr(file,'%g1')
self.andcc(file,'%g5','F_FP_DISABLED','%g0')
self.branch(file,'ne','%xcc','fpop_disabled_trap_fsr')
self.rd_gsr(file,'%g5')
self.wr_gsr(file,'%g1')
def fpop_fini_d(self,file):
self.branch(file,'a,a','%xcc','fpop_retl_d')
self.nop(file)
def fpop_fini_f(self,file):
self.branch(file,'a,a','%xcc','fpop_retl_f')
self.nop(file)
def fpop_fini_cc_d(self,file,cc,ccr):
global inv_rcond
# brcc have 16bit offset only which is killing us, so for brcc we
# do the opposite and branch over if not(cc) and ba,a to fpop_retl_d
if cc[0] == 'r':
self.branch(file,'r'+inv_rcond[cc[1:]]+',a','%'+ccr,'1f')
self.nop(file)
self.branch(file,'a,a','%xcc','fpop_retl_d')
self.nop(file)
file.write('1:\n')
self.fpop_fini(file)
else:
self.branch(file,cc+',a','%'+ccr,'fpop_retl_d')
self.nop(file)
self.fpop_fini(file)
def fpop_fini_cc_f(self,file,cc,ccr):
global inv_rcond
# brcc have 16bit offset only which is killing us, so for brcc we
# do the opposite and branch over if not(cc) and ba,a to fpop_retl_d
if cc[0] == 'r':
self.branch(file,'r'+inv_rcond[cc[1:]]+',a','%'+ccr,'1f')
self.nop(file)
self.branch(file,'a,a','%xcc','fpop_retl_f')
self.nop(file)
file.write('1:\n')
self.fpop_fini(file)
else:
self.branch(file,cc+',a','%'+ccr,'fpop_retl_f')
self.nop(file)
self.fpop_fini(file)
def fpop_fini(self,file):
self.branch(file,'a,a','%xcc','fpop_retl')
self.nop(file)
def gen_exe_tbl(self,file,mode):
if mode == 'v8_run':
mode = 'run'
if mode == 'run' or mode == 'trc':
file.write(' %s_exe_%s,\n' % (setup.product.lower(),self.name))
else:
file.write(' %s_exe_%s,\n' % (mode,self.name))
#============================================================================
# SS_fp_f0f
#============================================================================
class SS_fp_f0f(SS_fpop):
def __init__(self,opc):
SS_fpop.__init__(self,opc)
def run_exe_c(self,file,product='run'):
SS_fpop.run_exe_c(self,file,setup.product.lower())
def run_dec_c(self,file):
self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
file.write(' i->flg = SS_Instr::NON_LSU;\n')
file.write(' if (o.get_rs1() != 0)\n')
file.write(' return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
file.write(' else\n')
file.write(' {\n')
self.ill_ibe(file)
self.dec_f0f(file,' ','idx_exe_'+self.opc)
file.write(' }\n')
self.c_code_end(file)
def gen_exe_tbl(self,file,mode):
if mode == 'trc':
file.write(' trc_exe_f0f, /* '+self.name+' */\n')
else:
SS_fpop.gen_exe_tbl(self,file,mode)
#============================================================================
# SS_fp_f0d
#============================================================================
class SS_fp_f0d(SS_fpop):
def __init__(self,opc):
SS_fpop.__init__(self,opc)
def run_exe_c(self,file,product='run'):
SS_fpop.run_exe_c(self,file,setup.product.lower())
def run_dec_c(self,file):
self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
file.write(' i->flg = SS_Instr::NON_LSU;\n')
file.write(' if (o.get_rs1() != 0)\n')
file.write(' return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
file.write(' else\n')
file.write(' {\n')
self.ill_ibe(file)
self.dec_f0d(file,' ','idx_exe_'+self.opc)
file.write(' }\n')
self.c_code_end(file)
def gen_exe_tbl(self,file,mode):
if mode == 'trc':
file.write(' trc_exe_f0d, /* '+self.name+' */\n')
else:
SS_fpop.gen_exe_tbl(self,file,mode)
#============================================================================
# SS_fp_d0d
#============================================================================
class SS_fp_d0d(SS_fpop):
def __init__(self,opc):
SS_fpop.__init__(self,opc)
def run_exe_c(self,file,product='run'):
SS_fpop.run_exe_c(self,file,setup.product.lower())
def run_dec_c(self,file):
self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
file.write(' i->flg = SS_Instr::NON_LSU;\n')
file.write(' if (o.get_rs1() != 0)\n')
file.write(' return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
file.write(' else\n')
file.write(' {\n')
self.ill_ibe(file)
self.dec_d0d(file,' ','idx_exe_'+self.opc)
file.write(' }\n')
self.c_code_end(file)
def gen_exe_tbl(self,file,mode):
if mode == 'trc':
file.write(' trc_exe_d0d, /* '+self.name+' */\n')
else:
SS_fpop.gen_exe_tbl(self,file,mode)
#============================================================================
# SS_fp_d0f
#============================================================================
class SS_fp_d0f(SS_fpop):
def __init__(self,opc):
SS_fpop.__init__(self,opc)
def run_exe_c(self,file,product='run'):
SS_fpop.run_exe_c(self,file,setup.product.lower())
def run_dec_c(self,file):
self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
file.write(' i->flg = SS_Instr::NON_LSU;\n')
file.write(' if (o.get_rs1() != 0)\n')
file.write(' return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
file.write(' else\n')
file.write(' {\n')
self.ill_ibe(file)
self.dec_d0f(file,' ','idx_exe_'+self.opc)
file.write(' }\n')
self.c_code_end(file)
def gen_exe_tbl(self,file,mode):
if mode == 'trc':
file.write(' trc_exe_d0f, /* '+self.name+' */\n')
else:
SS_fpop.gen_exe_tbl(self,file,mode)
#============================================================================
# SS_fp_fff
#============================================================================
class SS_fp_fff(SS_fpop):
def __init__(self,opc):
SS_fpop.__init__(self,opc)
def run_exe_c(self,file,product='run'):
SS_fpop.run_exe_c(self,file,setup.product.lower())
def run_dec_c(self,file):
self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
file.write(' i->flg = SS_Instr::NON_LSU;\n')
self.ill_ibe(file)
self.dec_fff(file,'','idx_exe_'+self.opc)
self.c_code_end(file)
def gen_exe_tbl(self,file,mode):
if mode == 'trc':
file.write(' trc_exe_fff, /* '+self.name+' */\n')
else:
SS_fpop.gen_exe_tbl(self,file,mode)
#============================================================================
# SS_fp_ddd
#============================================================================
class SS_fp_ddd(SS_fpop):
def __init__(self,opc):
SS_fpop.__init__(self,opc)
def run_exe_c(self,file,product='run'):
SS_fpop.run_exe_c(self,file,setup.product.lower())
def run_dec_c(self,file):
self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
file.write(' i->flg = SS_Instr::NON_LSU;\n')
self.ill_ibe(file)
self.dec_ddd(file,'','idx_exe_'+self.opc)
self.c_code_end(file)
def gen_exe_tbl(self,file,mode):
if mode == 'trc':
file.write(' trc_exe_ddd, /* '+self.name+' */\n')
else:
SS_fpop.gen_exe_tbl(self,file,mode)
#============================================================================
# SS_fp_dff
#============================================================================
class SS_fp_dff(SS_fpop):
def __init__(self,opc):
SS_fpop.__init__(self,opc)
def run_exe_c(self,file,product='run'):
SS_fpop.run_exe_c(self,file,setup.product.lower())
def run_dec_c(self,file):
self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
file.write(' i->flg = SS_Instr::NON_LSU;\n')
self.ill_ibe(file)
self.dec_dff(file,'','idx_exe_'+self.opc)
self.c_code_end(file)
def gen_exe_tbl(self,file,mode):
if mode == 'trc':
file.write(' trc_exe_dff, /* '+self.name+' */\n')
else:
SS_fpop.gen_exe_tbl(self,file,mode)
#============================================================================
# SS_fp_ffff
#============================================================================
class SS_fp_ffff(SS_fpop):
def __init__(self,opc):
SS_fpop.__init__(self,opc)
def run_exe_c(self,file,product='run'):
SS_fpop.run_exe_c(self,file,setup.product.lower())
def run_dec_c(self,file):
self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
file.write(' i->flg = SS_Instr::NON_LSU;\n')
self.ill_ibe(file)
self.dec_ffff(file,'','idx_exe_'+self.opc)
self.c_code_end(file)
def gen_exe_tbl(self,file,mode):
if mode == 'trc':
file.write(' trc_exe_ffff, /* '+self.name+' */\n')
else:
SS_fpop.gen_exe_tbl(self,file,mode)
#============================================================================
# SS_fp_dddd
#============================================================================
class SS_fp_dddd(SS_fpop):
def __init__(self,opc):
SS_fpop.__init__(self,opc)
def run_exe_c(self,file,product='run'):
SS_fpop.run_exe_c(self,file,setup.product.lower())
def run_dec_c(self,file):
self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
file.write(' i->flg = SS_Instr::NON_LSU;\n')
self.ill_ibe(file)
self.dec_dddd(file,'','idx_exe_'+self.opc)
self.c_code_end(file)
def gen_exe_tbl(self,file,mode):
if mode == 'trc':
file.write(' trc_exe_dddd, /* '+self.name+' */\n')
else:
SS_fpop.gen_exe_tbl(self,file,mode)