sam-t2/sam/cpus/vonk/ss/lib/cpu/bin/SS_InstrFpu.py

# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: SS_InstrFpu.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
#
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# The above named program is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
#
# ========== Copyright Header End ============================================
from SS_Instr import *
from SS_InstrFpop import *

# Todo:
#
# @ fabs, fneg, fmov can be implemented more efficiently
# @ n2 fpop do unfinished traps .... need to implement that
# @ fp disabled should be a separate flag so we don;t have to do andcc
# @ check fsr gsr restore
#

#============================================================================
# SS_fmovcc(opc,cc,ccr)
#
# ToDo: movn & mova can be optimised
#============================================================================

class SS_fmovcc(SS_fpop):
  def __init__(self,opc,cc,ccr):
    SS_InstrAsm.__init__(self,opc+cc+'_'+ccr)
    self.opc = opc
    self.cc = cc
    self.ccr = ccr

  def gen_exe_tbl(self,file,mode):
    file.write('  %s_exe_%s,\n' % (mode,self.name))

  def run_exe_s(self,file):
    self.fpop_init(file)
    self.ld_rs2(file,'%g2')
    self.ld_rd(file,'%g3')
    if self.ccr[:3] != 'fcc':
      self.ld_ccr(file,'%g1')
    if self.opc[-1] == 's':
      self.ld_frf(file,'%g2','%f0')
    else:
      self.ld_drf(file,'%g2','%f0')
    if self.opc[-1] == 's':
      self.ld_frf(file,'%g3','%f8')
    else:
      self.ld_drf(file,'%g3','%f8')
    if self.ccr[:3] != 'fcc':
      self.wr_ccr(file,'%g1')
    self.opr(file,self.opc+self.cc,'%'+self.ccr,'%f0','%f8')
    if self.opc[-1] == 's':
      self.fpop_fini_cc_f(file,self.cc,self.ccr)
    else:
      self.fpop_fini_cc_d(file,self.cc,self.ccr)

  def run_exe_c(self,file):
    file.write('#if defined(ARCH_X64)\n')
    self.c_code_beg(file,'run_exe_')
    file.write('  if (s->sim_state.fp_disabled())\n')
    file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::FP_DISABLED);\n')
    if (self.ccr[:3] == 'fcc'):
      self.test_fcc(file,'  ')
      file.write('  {\n')
    else:
      self.test_icc(file,'  ')
      file.write('  {\n')
    if (self.opc[-1] == 's'):
      file.write('    s->get_frf(i->rd) = s->get_frf(i->rs2);\n')
    else:
      file.write('    s->get_drf(i->rd) = s->get_drf(i->rs2);\n')
    file.write('    s->set_fprs(i->rd);\n')
    file.write('  }\n')
    file.write('  s->fsr_run.ftt(0);\n')
    file.write('  s->fsr_exc.cexc(0);\n')
    file.write('  s->npc = npc+4;\n')
    file.write('  return npc;\n')
    self.c_code_end(file)
    file.write('#else\n')
    file.write('extern "C" SS_Vaddr run_exe_%s( SS_Vaddr, SS_Vaddr, SS_Strand*, SS_Instr* );\n' % (self.name))
    file.write('#endif\n')

  def run_dec_c(self,file):
    self.c_code_dec_beg(file,'run_dec_')
    file.write('  i->flg = SS_Instr::NON_LSU;\n')
    self.ill_ibe(file)
    if self.opc[-1] == 's':
      self.dec_f0f(file,'    ','idx_exe_'+self.name)
    else:
      self.dec_d0d(file,'    ','idx_exe_'+self.name)
    self.c_code_end(file)

  def gen_exe_tbl(self,file,mode):
    if mode == 'trc':
      if self.opc[-1] == 's':
        file.write('  trc_exe_f0f, /* '+self.name+' */\n')
      else:
        file.write('  trc_exe_d0d, /* '+self.name+' */\n')
    elif mode == 'v8_run':
      file.write('  run_exe_v8plus_to_v9, /* run_exe_'+self.name+' */\n')
    else:
      SS_Instr.gen_exe_tbl(self,file,mode)

#============================================================================
# SS_fmovr(opc,cc)
#
# ToDo fmovr does not have to use floating point at all.
#============================================================================

class SS_fmovr(SS_fpop):
  def __init__(self,opc,cc):
    SS_InstrAsm.__init__(self,opc+cc)
    self.opc = opc
    self.cc = cc

  def gen_exe_tbl(self,file,mode):
    file.write('  %s_exe_%s,\n' % (mode,self.name))

  def run_exe_s(self,file):
    self.fpop_init(file)
    self.ld_rs1(file,'%g1')
    self.ld_rs2(file,'%g2')
    self.ld_rd(file,'%g3')
    self.ld_irf(file,'%g1','%g1')
    if self.opc[-1] == 's':
      self.ld_frf(file,'%g2','%f0')
      self.ld_frf(file,'%g3','%f8')
    else:
      self.ld_drf(file,'%g2','%f0')
      self.ld_drf(file,'%g3','%f8')
    self.opr(file,self.opc+self.cc,'%g1','%f0','%f8')
    if self.opc[-1] == 's':
      self.fpop_fini_cc_f(file,'r'+self.cc,'g1')
    else:
      self.fpop_fini_cc_d(file,'r'+self.cc,'g1')

  def run_exe_c(self,file):
    file.write('#if defined(ARCH_X64)\n')
    self.c_code_beg(file,'run_exe_')
    file.write('  if (s->sim_state.fp_disabled())\n')
    file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::FP_DISABLED);\n')
    self.test_r(file,'  ')
    file.write('  {\n')
    if (self.opc[-1] == 's'):
      file.write('    s->get_frf(i->rd) = s->get_frf(i->rs2);\n')
    else:
      file.write('    s->get_drf(i->rd) = s->get_drf(i->rs2);\n')
    file.write('    s->set_fprs(i->rd);\n')
    file.write('  }\n')
    file.write('  s->fsr_run.ftt(0);\n')
    file.write('  s->fsr_exc.cexc(0);\n')
    file.write('  s->npc = npc+4;\n')
    file.write('  return npc;\n')
    self.c_code_end(file)
    file.write('#else\n')
    file.write('extern "C" SS_Vaddr run_exe_%s( SS_Vaddr, SS_Vaddr, SS_Strand*, SS_Instr* );\n' % (self.name))
    file.write('#endif\n')

  def run_dec_c(self,file):
    self.c_code_dec_beg(file,'run_dec_')
    file.write('  i->flg = SS_Instr::NON_LSU;\n')
    self.ill_ibe(file)
    if self.opc[-1] == 's':
      self.dec_frf(file,'    ','idx_exe_'+self.name)
    else:
      self.dec_drd(file,'    ','idx_exe_'+self.name)
    self.c_code_end(file)

  def gen_exe_tbl(self,file,mode):
    if mode == 'trc':
      if self.opc[-1] == 's':
        file.write('  trc_exe_frf, /* '+self.name+' */\n')
      else:
        file.write('  trc_exe_drd, /* '+self.name+' */\n')
    elif mode == 'v8_run':
      file.write('  run_exe_v8plus_to_v9, /* run_exe_'+self.name+' */\n')
    else:
      SS_Instr.gen_exe_tbl(self,file,mode)

#============================================================================
# SS_fcmp
#============================================================================

class SS_fcmp(SS_fpop):
  def __init__(self,opc):
    SS_fpop.__init__(self,opc)

  def run_exe_c(self,file,product='run'):
    SS_fpop.run_exe_c(self,file,setup.product.lower())

  def run_dec_c(self,file):
    self.c_code_dec_beg_name(file,'run_dec_'+self.opc)
    file.write('  i->flg = SS_Instr::NON_LSU;\n')
    file.write('  if (o.get_rd() < 4)\n')
    file.write('  {\n')
    self.ill_ibe(file)
    if self.opc[-1] == 's':
      self.dec_nff(file,'  ','idx_exe_'+self.opc)
    else:
      self.dec_ndd(file,'  ','idx_exe_'+self.opc)
    file.write('  }\n')
    file.write('  else\n')
    file.write('    return (s->trap)(pc,npc,s,i,SS_Trap::ILLEGAL_INSTRUCTION);\n')
    self.c_code_end(file)

  def gen_exe_tbl(self,file,mode):
    if mode == 'v8_run':
      mode = 'run'
    if mode == 'trc':
      if self.opc[-1] == 's':
        file.write('  trc_exe_0ff, /* '+self.name+' */\n')
      else:
        file.write('  trc_exe_0dd, /* '+self.name+' */\n')
    else:
      SS_fpop.gen_exe_tbl(self,file,mode)

#============================================================================
# fpop1
#============================================================================

ss_fpop1   = SS_InstrGroup('10_110100_fpop1',5,0x1ff)

ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_f0f('fmovs'))
ss_fpop1.append(SS_fp_d0d('fmovd'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_f0f('fnegs'))
ss_fpop1.append(SS_fp_d0d('fnegd'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_f0f('fabss'))
ss_fpop1.append(SS_fp_d0d('fabsd'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())

for i in range(0,16):
  ss_fpop1.append(SS_ill())

ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_f0f('fsqrts'))
ss_fpop1.append(SS_fp_d0d('fsqrtd'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
if setup.product == 'N2':
  ss_fpop1.append(SS_ill())
  ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())

for i in range(0,16):
  ss_fpop1.append(SS_ill())

ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_fff('fadds'))
ss_fpop1.append(SS_fp_ddd('faddd'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_fff('fsubs'))
ss_fpop1.append(SS_fp_ddd('fsubd'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_fff('fmuls'))
ss_fpop1.append(SS_fp_ddd('fmuld'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_fff('fdivs'))
ss_fpop1.append(SS_fp_ddd('fdivd'))
ss_fpop1.append(SS_ill())

if setup.product in ['N2']:
  for i in range(0,16):
    ss_fpop1.append(SS_ill())

ss_fpop1.append(SS_ill())
if setup.product in ['N2']:
  ss_fpop1.append(SS_ill())
  ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
if setup.product in ['N2']:
  ss_fpop1.append(SS_ill())
  ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_dff('fsmuld'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())

if setup.product in ['N2']:
  for i in range(0,16):
    ss_fpop1.append(SS_ill())

ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_d0f('fstox'))
ss_fpop1.append(SS_fp_d0d('fdtox'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_f0d('fxtos'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_d0d('fxtod'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())

for i in range(0,48):
  ss_fpop1.append(SS_ill())

ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_f0f('fitos'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_f0d('fdtos'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_d0f('fitod'))
ss_fpop1.append(SS_fp_d0f('fstod'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())

ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_fp_f0f('fstoi'))
ss_fpop1.append(SS_fp_f0d('fdtoi'))
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())
ss_fpop1.append(SS_ill())

for i in range(0,32):
  ss_fpop1.append(SS_ill())

for i in range(0,256):
  ss_fpop1.append(SS_ill())

#============================================================================
# fpop2
#============================================================================

ss_fmovsfcc0 = SS_InstrGroup('10_110101_000000001_fmovsfcc0',14,0x1f)
ss_fmovsfcc1 = SS_InstrGroup('10_110101_001000001_fmovsfcc1',14,0x1f)
ss_fmovsfcc2 = SS_InstrGroup('10_110101_010000001_fmovsfcc2',14,0x1f)
ss_fmovsfcc3 = SS_InstrGroup('10_110101_011000001_fmovsfcc3',14,0x1f)
ss_fmovsicc  = SS_InstrGroup('10_110101_100000001_fmovsicc',14,0x1f)
ss_fmovsxcc  = SS_InstrGroup('10_110101_110000001_fmovsxcc',14,0x1f)

ss_fmovdfcc0 = SS_InstrGroup('10_110101_000000010_fmovsfcc0',14,0x1f)
ss_fmovdfcc1 = SS_InstrGroup('10_110101_001000010_fmovsfcc1',14,0x1f)
ss_fmovdfcc2 = SS_InstrGroup('10_110101_010000010_fmovsfcc2',14,0x1f)
ss_fmovdfcc3 = SS_InstrGroup('10_110101_011000010_fmovsfcc3',14,0x1f)
ss_fmovdicc  = SS_InstrGroup('10_110101_100000010_fmovsicc',14,0x1f)
ss_fmovdxcc  = SS_InstrGroup('10_110101_110000010_fmovsxcc',14,0x1f)

for cc,x in fcond:
  ss_fmovsfcc0.append(SS_fmovcc('fmovs',cc,'fcc0'))
  ss_fmovsfcc1.append(SS_fmovcc('fmovs',cc,'fcc1'))
  ss_fmovsfcc2.append(SS_fmovcc('fmovs',cc,'fcc2'))
  ss_fmovsfcc3.append(SS_fmovcc('fmovs',cc,'fcc3'))
  ss_fmovdfcc0.append(SS_fmovcc('fmovd',cc,'fcc0'))
  ss_fmovdfcc1.append(SS_fmovcc('fmovd',cc,'fcc1'))
  ss_fmovdfcc2.append(SS_fmovcc('fmovd',cc,'fcc2'))
  ss_fmovdfcc3.append(SS_fmovcc('fmovd',cc,'fcc3'))

for cc,x in cond:
  ss_fmovsicc.append(SS_fmovcc('fmovs',cc,'icc'))
  ss_fmovdicc.append(SS_fmovcc('fmovd',cc,'icc'))
  ss_fmovsxcc.append(SS_fmovcc('fmovs',cc,'xcc'))
  ss_fmovdxcc.append(SS_fmovcc('fmovd',cc,'xcc'))

for i in range(0,16):
  ss_fmovsfcc0.append(SS_ill())
  ss_fmovsfcc1.append(SS_ill())
  ss_fmovsfcc2.append(SS_ill())
  ss_fmovsfcc3.append(SS_ill())
  ss_fmovdfcc0.append(SS_ill())
  ss_fmovdfcc1.append(SS_ill())
  ss_fmovdfcc2.append(SS_ill())
  ss_fmovdfcc3.append(SS_ill())
  ss_fmovsicc.append(SS_ill())
  ss_fmovdicc.append(SS_ill())
  ss_fmovsxcc.append(SS_ill())
  ss_fmovdxcc.append(SS_ill())

ss_fpop2 = SS_InstrGroup('10_110101_fpop2',5,0x1ff)

# 0 0000 0000
ss_fpop2.append(SS_ill())
ss_fpop2.append(ss_fmovsfcc0)
ss_fpop2.append(ss_fmovdfcc0)
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

# 0 0001 0000
for i in range(0,16):
  ss_fpop2.append(SS_ill())

# 0 0010 0000
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_fmovr('fmovrs','z'))
ss_fpop2.append(SS_fmovr('fmovrd','z'))
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

# 0 0011 0000
for i in range(0,16):
  ss_fpop2.append(SS_ill())

# 0 0100 0000
ss_fpop2.append(SS_ill())
ss_fpop2.append(ss_fmovsfcc1)
ss_fpop2.append(ss_fmovdfcc1)
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_fmovr('fmovrs','lez'))
ss_fpop2.append(SS_fmovr('fmovrd','lez'))
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

# 0 0101 0000
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_fcmp('fcmps'))
ss_fpop2.append(SS_fcmp('fcmpd'))
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_fcmp('fcmpes'))
ss_fpop2.append(SS_fcmp('fcmped'))
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

# 0 0110 0000
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_fmovr('fmovrs','lz'))
ss_fpop2.append(SS_fmovr('fmovrd','lz'))
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

# 0 0111 0000
for i in range(0,16):
  ss_fpop2.append(SS_ill())

# 0 1000 0000
ss_fpop2.append(SS_ill())
ss_fpop2.append(ss_fmovsfcc2)
ss_fpop2.append(ss_fmovdfcc2)
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

# 0 1001 0000
for i in range(0,16):
  ss_fpop2.append(SS_ill())

# 0 1010 0000
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_fmovr('fmovrs','nz'))
ss_fpop2.append(SS_fmovr('fmovrd','nz'))
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

# 0 1011 0000
for i in range(0,16):
  ss_fpop2.append(SS_ill())

# 0 1100 0000
ss_fpop2.append(SS_ill())
ss_fpop2.append(ss_fmovsfcc3)
ss_fpop2.append(ss_fmovdfcc3)
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_fmovr('fmovrs','gz'))
ss_fpop2.append(SS_fmovr('fmovrd','gz'))
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

# 0 1101 0000
for i in range(0,16):
  ss_fpop2.append(SS_ill())

# 0 1110 0000
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_fmovr('fmovrs','gez'))
ss_fpop2.append(SS_fmovr('fmovrd','gez'))
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

# 0 1111 0000
for i in range(0,16):
  ss_fpop2.append(SS_ill())

ss_fpop2.append(SS_ill())
ss_fpop2.append(ss_fmovsicc)
ss_fpop2.append(ss_fmovdicc)
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

for i in range(0,48):
  ss_fpop2.append(SS_ill())

for i in range(0,64):
  ss_fpop2.append(SS_ill())

ss_fpop2.append(SS_ill())
ss_fpop2.append(ss_fmovsxcc)
ss_fpop2.append(ss_fmovdxcc)
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())
ss_fpop2.append(SS_ill())

for i in range(0,48):
  ss_fpop2.append(SS_ill())

for i in range(0,64):
  ss_fpop2.append(SS_ill())

#============================================================================
# fma
#============================================================================

ss_fmaf = SS_InstrGroup('10_110111_fmaf',5,0xf)
ss_fmau = SS_InstrGroup('10_111111_fmau',5,0xf)

if setup.product in ['N2']:
  for i in range(0,16):
    ss_fmaf.append(SS_ill())

if setup.product in ['N2']:
  for i in range(0,16):
    ss_fmau.append(SS_ill())