Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / bin / SS_InstrRun.py

# ========== Copyright Header Begin ==========================================
# 
# OpenSPARC T2 Processor File: SS_InstrRun.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
# 
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
# 
# The above named program is distributed in the hope that it will be 
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
# 
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
# 
# ========== Copyright Header End ============================================

from SS_Setup    import *
from SS_InstrSim import *
from SS_InstrAlu import *
from SS_InstrCtr import *
from SS_InstrCti import *
from SS_InstrLsu import *
from SS_InstrFpu import *
from SS_InstrVis import *

setup = setups[sys.argv[1]]

mem = []
exe = SS_InstrTable(setup, 'xx_xxxxxx')

# 00_xxxxxx

exe.append(SS_illtrap())
exe.append(ss_bp_icc)
exe.append(ss_bp_c01)
exe.append(ss_bp_xcc)
exe.append(ss_bp_c11)
exe.append(ss_bi)
exe.append(ss_br)
exe.append(SS_nop())
exe.append(SS_sethi())
exe.append(ss_fbp_fcc0)
exe.append(ss_fbp_fcc1)
exe.append(ss_fbp_fcc2)
exe.append(ss_fbp_fcc3)
exe.append(ss_fbi)
for i in range(0,8):
 exe.append(SS_ill())

# 01_xxxxxx

exe.append(SS_call())

# 10_000xxx add .... xnor,
# 10_001xxx addc mulx umul smul subc udivx udiv sdiv
# 10_010xxx addcc .... xnorcc,
# 10_011xxx addccc - umulcc smulcc subccc - udivcc sdivcc
# 10_100xxx taddcc tsubcc taddcctv tsubcctv mulscc sll srl sra
# 10_101xxx rdasr rdhrf rdprf flushw movcc sdivx popc movr
# 10_110xxx wrasr saved/restored wrprf wrhrf fpop1 fpop2 vis fmaf
# 10_111xxx jmpl return tcc flush(a) save restore done/retry fmau

for i in ['add','and','or','xor','sub','andn','orn','xnor']:
 exe.append(SS_alu(i))
for i in ['addc','mulx','umul','smul','subc','udivx','udiv','sdiv']:
 exe.append(SS_alu(i))
for i in ['addcc','andcc','orcc','xorcc','subcc','andncc','orncc','xnorcc']:
 exe.append(SS_alu(i))
for i in ['addccc','-','umulcc','smulcc','subccc','-','udivcc','sdivcc']:
 if i == '-':
   exe.append(SS_ill())
 else:
   exe.append(SS_alu(i))

exe.append(SS_tagged_alu('taddcc'))
exe.append(SS_tagged_alu('tsubcc'))
exe.append(SS_tagged_alu('taddcctv'))
exe.append(SS_tagged_alu('tsubcctv'))
if setup.product == 'N2':
 exe.append(SS_alu('mulscc'))
exe.append(ss_sll)
exe.append(ss_srl)
exe.append(ss_sra)

exe.append(ss_rdasr)
exe.append(ss_rdhrf)
exe.append(ss_rdprf)
exe.append(SS_flushw())
exe.append(ss_movcc)
exe.append(SS_alu('sdivx'))
exe.append(SS_popc())
exe.append(ss_movr)

exe.append(ss_wrasr)
exe.append(ss_saved)
exe.append(ss_wrprf)
exe.append(ss_wrhrf)
exe.append(ss_fpop1)
exe.append(ss_fpop2)
exe.append(ss_vis)
exe.append(ss_fmaf)

exe.append(SS_jmpl())
exe.append(SS_return())
exe.append(ss_tcc)
exe.append(ss_flush)
exe.append(SS_save())
exe.append(SS_restore())
exe.append(ss_done)
exe.append(ss_fmau)

for i in ['lduw', 'ldub',  'lduh', 'ldd',  'stw', 'stb',      'sth',  'std',            # 11_000xxx
         'ldsw', 'ldsb',  'ldsh', 'ldx',  '-',   'ldstub',   'stx',  'swap',           # 11_001xxx
         'lduwa','lduba', 'lduha','ldda', 'stwa','stba',     'stha', 'stda',           # 11_010xxx
         'ldswa','ldsba', 'ldsha','ldxa', '-',   'ldstuba',  'stxa', 'swapa',          # 11_011xxx
         'ldf',  'ldxfsr','-',    'lddf', 'stf', 'stxfsr',   '-',    'stdf',           # 11_100xxx
         '-',    '-',     '-',    '-',    '-',   'prefetch', '-',    '-',              # 11_101xxx
         'ldfa', '-',     '-',    'lddfa','stfa','-',        '-',    'stdfa',          # 11_110xxx
         '-',    '-',     '-',    '-',    'casa','prefetcha','casxa','-'     ]:        # 11_111xxx
 if i == '-':
   exe.append(SS_ill())
 elif i == 'ldxfsr':
   exe.append(ss_ldxfsr)
 elif i == 'stxfsr':
   exe.append(ss_stxfsr)
 elif i == 'prefetch':
   exe.append(ss_prefetch)
 elif i == 'prefetcha':
   exe.append(ss_prefetcha)
 else:
   exe.append(SS_lsu_dec(i))


for i in ['lduw','ldub','lduh','ldd','ldsw','ldsb','ldsh','ldx','ldtd', 
         'stw','stb','sth','std','stx','stfsr','stxfsr',
         'ldf','lddf','ldshortf8','ldshortf16','ldblockf','ldfsr','ldxfsr',
         'stf','stdf','stshortf8','stshortf16','stpartial8','stpartial16','stpartial32','stblockf', 
         'ldstub','swap','cas','casx','prefetch','flush']:
 exe.append(SS_lsu_exe(i))

exe.append(SS_rdasi('i0','rd'))
exe.append(SS_rdasi('i0','g0'))
exe.append(SS_rdasi('i1','rd'))
exe.append(SS_rdasi('i1','g0'))
exe.append(SS_wrasi('i0','rd'))
exe.append(SS_wrasi('i0','g0'))
exe.append(SS_wrasi('i1','rd'))
exe.append(SS_wrasi('i1','g0'))

for i in ['lduw','ldub','lduh','ldd','ldsw','ldsb','ldsh','ldx','ldtd']:
 mem.append(SS_ld_mem(i,'rd'))
 mem.append(SS_ld_mem(i,'g0'))
for i in ['prefetch']:
 mem.append(SS_ld_mem(i,'fn'))
for i in ['ldf','lddf','ldshortf8','ldshortf16','ldblockf','ldfsr','ldxfsr']:
 mem.append(SS_ld_mem(i,'fp'))
for i in ['stw','stb','sth','std','stx']:
 mem.append(SS_st_mem(i,'rd'))
 mem.append(SS_st_mem(i,'g0'))
for i in ['stf','stdf','stshortf8','stshortf16','stpartial8','stpartial16','stpartial32','stblockf','stfsr','stxfsr']:
 mem.append(SS_st_mem(i,'fp'))

mem.append(SS_ldstub_mem('ldstub','rd'))
mem.append(SS_ldstub_mem('ldstub','g0'))
mem.append(SS_swap_mem('swap','rd'))
mem.append(SS_swap_mem('swap','g0'))
mem.append(SS_cas_mem('cas','rd'))
mem.append(SS_cas_mem('cas','g0'))
mem.append(SS_cas_mem('casx','rd'))
mem.append(SS_cas_mem('casx','g0'))
mem.append(SS_flush_mem('flush','fn'))



if sys.argv[2] == 's':

 s_file=open('%sAsm.s'  % sys.argv[3],'w')
 s_file.write('#if !defined(ARCH_X64)\n')
 s_file.write('#include "SS_Assembly.h"\n')
 s_file.write('\n')
 s_file.write('.section\t".text"\n')
 s_file.write('\n')
 s_file.write('.register\t%g2,#scratch\n')
 s_file.write('.register\t%g3,#scratch\n')
 s_file.write('\n')
 s_file.write('/* cas and casx are not sun sparc instructions so for now do*/\n')
 s_file.write('#define run_dec_cas     run_dec_casa\n')
 s_file.write('#define run_dec_casx    run_dec_casxa\n')
 s_file.write('\n')
 s_file.write('#if defined(ARCH_V9)\n')
 s_file.write('#define V8_PC\n')
 s_file.write('#elif defined(ARCH_V8)\n')
 s_file.write('#define V8_PC\\\n')
 s_file.write('        srl     %o0,0,%o1;\\\n')
 s_file.write('        srlx    %o0,32,%o0\n')
 s_file.write('#else\n')
 s_file.write('#error "Need ARCH option in make\n')
 s_file.write('#endif\n')
 s_file.write('\n')
 s_file.write('#include "SS_Float.s"\n')
 s_file.write('#include "SS_LsuTrap.s"\n')

 s_file.write('\n')
 for i in mem:
   i.idx_mem_s(s_file)

 s_file.write('\n')
 exe.exe_idx_s(s_file)

 exe.run_dec_s(s_file)
 exe.run_exe_s(s_file)

 s_file.write('#endif\n')
 s_file.close()

elif sys.argv[2] == 'h':

 h_base_name = sys.argv[3].split('/')[-1]
 h_file=open('%sCpp.h'  % sys.argv[3],'w')
 h_file.write('#ifndef __'+h_base_name+'Cpp_h__\n')
 h_file.write('#define __'+h_base_name+'Cpp_h__\n')
 h_file.write('\n')

 h_file.write('\n')
 h_file.write('extern SS_Memop mem_run_table[][4];\n')
 h_file.write('extern SS_Memop mem_trc_table[][4];\n')
 h_file.write('extern SS_Memop mem_ras_table[][4];\n')
 h_file.write('\n')
 h_file.write('extern SS_DecodeTable run_dec_xx_xxxxxx;\n')
 h_file.write('\n')

 h_file.write('\nenum ExeIdx\n')
 h_file.write('{\n')
 exe.gen_exe_tbl(h_file,mode='idx')
 h_file.write('  idx_exe_table_size\n')
 h_file.write('};\n\n')

 h_file.write('#endif\n')
 h_file.close()
     
elif sys.argv[2] == 'cc':

 c_file=open('%sCpp.cc' % sys.argv[3],'w')
 c_file.write('#include "BL_Endian.h"\n')
 c_file.write('#include "SS_Strand.h"\n')
 c_file.write('#include "SS_Tlb.h"\n')
 c_file.write('#include "SS_Decode.h"\n')
 c_file.write('#include "SS_TrcExe.h"\n')  
 c_file.write('#include "SS_V8Code.h"\n')  

 if setup.product in ['N2']:
   c_file.write('#include "BL_Hamming_64_8_Synd.h"\n')
   c_file.write('#include "N2_Model.h"\n')
   c_file.write('#include "N2_RunCpp.h"\n')
   c_file.write('#include "N2_Strand.h"\n')
   c_file.write('#include "N2_MemErrDetector.h"\n')

 c_file.write('\nenum MemIdx\n')
 c_file.write('{\n')
 c_file.write('  idx_mem_xxxxx,\n')
 for i in mem:
   i.gen_mem_tbl(c_file,'idx')
 c_file.write('  mem_idx_table_size\n')
 c_file.write('};\n\n')

 c_file.write('static inline uint64_t endianess_partial( uint64_t b )\n')
 c_file.write('{\n')
 c_file.write('  uint64_t v = 0;\n')
 c_file.write('  for (int i=0; i<8; i++)\n')
 c_file.write('  {\n')
 c_file.write('    v = (v << 1) | (b & 1);\n')
 c_file.write('    b >>= 1;\n')
 c_file.write('  }\n')
 c_file.write('  return v;\n')
 c_file.write('}\n')
 c_file.write('\n')

 exe.run_exe_c(c_file)

 for i in mem:
   i.mem_c(c_file)

 c_file.write('\n')
 c_file.write('SS_Execute '+setup.product+'_Strand::run_exe_table[] =\n')
 c_file.write('{\n')
 exe.gen_exe_tbl(c_file,'run')
 c_file.write('  0\n')
 c_file.write('};\n\n')

 c_file.write('#if !defined(ARCH_X64)\n')
 c_file.write('SS_Execute '+setup.product+'_Strand::v8_run_exe_table[] =\n')
 c_file.write('{\n')
 exe.gen_exe_tbl(c_file,'v8_run')
 c_file.write('  0\n')
 c_file.write('};\n\n')
 c_file.write('#endif\n')

 c_file.write('SS_Execute '+setup.product+'_Strand::trc_exe_table[] =\n')
 c_file.write('{\n')
 exe.gen_exe_tbl(c_file,'trc')
 c_file.write('  0\n')
 c_file.write('};\n\n')

 c_file.write('SS_Memop '+setup.product+'_Strand::mem_run_table[][4] =\n')
 c_file.write('{\n')
 c_file.write('  mem_run_fetch512,\n')
 c_file.write('  io_run_fetch512,\n')
 c_file.write('  0,\n')
 c_file.write('  0,\n')
 for i in mem:
   i.gen_mem_tbl(c_file,'run')
 c_file.write('  0\n')
 c_file.write('};\n\n')

 c_file.write('SS_Memop '+setup.product+'_Strand::mem_trc_table[][4] =\n')
 c_file.write('{\n')
 c_file.write('  mem_trc_fetch512,\n')
 c_file.write('  io_trc_fetch512,\n')
 c_file.write('  0,\n')
 c_file.write('  0,\n')
 for i in mem:
   i.gen_mem_tbl(c_file,'trc')
 c_file.write('  0\n')
 c_file.write('};\n\n')

 c_file.write('SS_Memop '+setup.product+'_Strand::mem_ras_table[][4] =\n')
 c_file.write('{\n')
 c_file.write('  mem_trc_fetch512,\n')
 c_file.write('  io_trc_fetch512,\n')
 c_file.write('  0,\n')
 c_file.write('  0,\n')
 for i in mem:
   i.gen_mem_tbl(c_file,'ras')
 c_file.write('  0\n')
 c_file.write('};\n\n')

 exe.run_dec_c(c_file)

 c_file.close()