Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / bin / SS_Setup.py
# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: SS_Setup.py
# Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
#
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# The above named program is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
#
# ========== Copyright Header End ============================================
class SS_Setup:
product = "SS"
va_bits = 64 # Size of the VA space. Value < 64 causes VA hole check
pa_bits = 55 # Size of the PA space.
va_edge = False # Does Iside treat last Icacheline as part of the VA hole
ill_ibe = False # True when illegal instr trap has higher priority then instr breakpoint trap
class N2_Setup(SS_Setup):
product = "N2"
va_bits = 48
pa_bits = 40
va_edge = True
ill_ibe = True
setups = {
'ss': SS_Setup(),
'n2': N2_Setup()
}