sam-t2/sam/cpus/vonk/ss/lib/cpu/bin/SS_StateAsr.py

# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: SS_StateAsr.py
# Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
# DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
#
# The above named program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public
# License version 2 as published by the Free Software Foundation.
#
# The above named program is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public
# License along with this work; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
#
# ========== Copyright Header End ============================================

import sys

from SS_State import *
from SS_Setup import *

setup = setups[sys.argv[1]]

ctr_regs = [
  SS_CtrReg('SS','y'          ,'asr', 0,RWRWRW,32,
  [
  ])
, SS_CtrReg('SS','ccr'        ,'asr', 2,RWRWRW, 8,
  [
    ('icc'      , 0, 3, RW, X),
    ('xcc'      , 4, 7, RW, X)
  ])
, SS_CtrReg('SS','asi_reg'    ,'asr', 3,RWRWRW, 8,
  [
  ])
, SS_CtrReg('SS','tick'       ,'asr', 4,RORORO,64,
  [
    ('counter'  , 0,62, RW, 0),
    ('npt'      ,63,63, RW, 0)
  ])
, SS_CtrReg('SS','pc'         ,'asr', 5,RORORO,64,
  [
    (''         , 2,63, RW, 0)])
, SS_CtrReg('SS','fprs'       ,'asr', 6,RWRWRW, 8,
  [
    ('dl'       , 0, 0, RW, 0),
    ('du'       , 1, 1, RW, 0),
    ('fef'      , 2, 2, RW, 0)
  ])
, SS_CtrReg('SS','gsr'        ,'asr',19,RWRWRW,64,
  [
    ('align'    , 0, 2, RW, 0),
    ('scale'    , 3, 7, RW, 0),
    ('irnd'     ,25,26, RW, 0),
    ('im'       ,27,27, RW, 0),
    ('mask'     ,32,63, RW, 0)
  ])
, SS_CtrReg('SS','softint_set','asr',20,WOWO__, 8,
  [
    # This register is the same as softint
  ])
, SS_CtrReg('SS','softint_clr','asr',21,WOWO__, 8,
  [
    # This register is the same as softint
  ])
, SS_CtrReg('SS','softint'    ,'asr',22,RWRW__,32,
  [
    ('tm'       , 0, 0, RW, 0),
    ('level'    , 1,15, RW, 0),
    ('sm'       ,16,16, RW, 0)
  ])
, SS_CtrReg('SS','tick_cmpr'  ,'asr',23,RWRW__,64,
  [
    ('cmpr'     , 0,62, RW, 0),
    ('int_dis'  ,63,63, RW, 1)
  ])
, SS_CtrReg('SS','stick'      ,'asr',24,RWRORO,64,
  [
    ('counter'  , 0,62, RW, 0),
    ('npt'      ,63,63, RW, 0)
  ])
, SS_CtrReg('SS','stick_cmpr' ,'asr',25,RWRW__,64,
  [
    ('cmpr'     , 0,62, RW, 0),
    ('int_dis'  ,63,63, RW, 1)
  ])
]

# ToDo For now we add the asr registers here. The full definition appears in
# N2_State.py  ... somehow this code needs to be cleaned up.
# The only reason they appear here is that the list is used in SS_InstrCrt.py
# to make our life easier for generating the various rdctr/wrctr instructions.

if setup.product in ['N2']:
  ctr_regs.append(SS_CtrReg('N2','pcr','asr',16,RWRW__,0,[]))
  ctr_regs.append(SS_CtrReg('N2','pic','asr',17,RWRWRW,0,[]))

ctr_table = SS_CtrTable(ctr_regs)