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Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / src / SS_Fpu.cc
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: SS_Fpu.cc
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/*
===============================================================================
This C source file is adapted from the SoftFloat IEC/IEEE Floating-point
Arithmetic Package, Release 2a.
Written by John R. Hauser. This work was made possible in part by the
International Computer Science Institute, located at Suite 600, 1947 Center
Street, Berkeley, California 94704. Funding was partially provided by the
National Science Foundation under grant MIP-9311980. The original version
of this code was written as part of a project to build a fixed-point vector
processor in collaboration with the University of California at Berkeley,
overseen by Profs. Nelson Morgan and John Wawrzynek. More information
is available through the Web page `http://HTTP.CS.Berkeley.EDU/~jhauser/
arithmetic/SoftFloat.html'.
THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE. Although reasonable effort
has been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT
TIMES RESULT IN INCORRECT BEHAVIOR. USE OF THIS SOFTWARE IS RESTRICTED TO
PERSONS AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ANY
AND ALL LOSSES, COSTS, OR OTHER PROBLEMS ARISING FROM ITS USE.
Derivative works are acceptable, even for commercial purposes, so long as
(1) they include prominent notice that the work is derivative, and (2) they
include prominent notice akin to these four paragraphs for those parts of
this code that are retained.
===============================================================================
*/
#include "SS_Fpu.h"
SS_Fpu::SS_Fpu()/*{{{*/
:
float_rounding_mode(ROUND_NEAREST),
float_exception_flags(EXC_NONE),
float_partial_exception_flags(EXC_NONE),
float_round_needed(0),
float_detect_tininess(TINY_BEFORE_ROUNDING)
{}
/*}}}*/
int32_t SS_Fpu::roundAndPackInt32( int zSign, uint64_t absZ )/*{{{*/
{
/* -------------------------------------------------------------------------------
Takes a 64-bit fixed-point value `absZ' with binary point between bits 6
and 7, and returns the properly rounded 32-bit integer corresponding to the
input. If `zSign' is 1, the input is negated before being converted to an
integer. Bit 63 of `absZ' must be zero. Ordinarily, the fixed-point input
is simply rounded to an integer, with the inexact exception raised if the
input cannot be represented exactly as an integer. However, if the fixed-
point input is too large, the invalid exception is raised and the largest
positive or negative integer is returned.
------------------------------------------------------------------------------- */
int8_t roundingMode;
int roundNearestEven;
int8_t roundIncrement, roundBits;
int32_t z;
roundingMode = float_rounding_mode;
roundNearestEven = ( roundingMode == ROUND_NEAREST );
roundIncrement = 0x40;
if ( ! roundNearestEven ) {
if ( roundingMode == ROUND_TO_ZERO ) {
roundIncrement = 0;
}
else {
roundIncrement = 0x7F;
if ( zSign ) {
if ( roundingMode == ROUND_UP ) roundIncrement = 0;
}
else {
if ( roundingMode == ROUND_DOWN ) roundIncrement = 0;
}
}
}
roundBits = absZ & 0x7F;
absZ = ( absZ + roundIncrement )>>7;
absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
z = (int32_t) absZ;
if ( zSign ) z = - z;
if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {
float_raise( EXC_INVALID );
return zSign ? (int32_t) 0x80000000 : 0x7FFFFFFF;
}
if ( roundBits ) float_exception_flags = float_exception_flags | EXC_INEXACT;
return z;
}
/*}}}*/
int64_t SS_Fpu::roundAndPackInt64( int zSign, uint64_t absZ0, uint64_t absZ1 )/*{{{*/
{
/* -------------------------------------------------------------------------------
Takes the 128-bit fixed-point value formed by concatenating `absZ0' and
`absZ1', with binary point between bits 63 and 64 (between the input words),
and returns the properly rounded 64-bit integer corresponding to the input.
If `zSign' is 1, the input is negated before being converted to an integer.
Ordinarily, the fixed-point input is simply rounded to an integer, with
the inexact exception raised if the input cannot be represented exactly as
an integer. However, if the fixed-point input is too large, the invalid
exception is raised and the largest positive or negative integer is
returned.
------------------------------------------------------------------------------- */
int8_t roundingMode;
int roundNearestEven, increment;
int64_t z;
roundingMode = float_rounding_mode;
roundNearestEven = ( roundingMode == ROUND_NEAREST );
increment = ( (int64_t) absZ1 < 0 );
if ( ! roundNearestEven ) {
if ( roundingMode == ROUND_TO_ZERO ) {
increment = 0;
}
else {
if ( zSign ) {
increment = ( roundingMode == ROUND_DOWN ) && absZ1;
}
else {
increment = ( roundingMode == ROUND_UP ) && absZ1;
}
}
}
if ( increment ) {
++absZ0;
if ( absZ0 == 0 ) goto overflow;
absZ0 &= ~ ( ( (uint64_t) ( absZ1<<1 ) == 0 ) & roundNearestEven );
}
z = absZ0;
if ( zSign ) z = - z;
if ( z && ( ( z < 0 ) ^ zSign ) ) {
overflow:
float_raise( EXC_INVALID );
return
zSign ? (int64_t) 0x8000000000000000
: 0x7FFFFFFFFFFFFFFF ;
}
if ( absZ1 ) float_exception_flags = float_exception_flags | EXC_INEXACT;
return z;
}
/*}}}*/
uint32_t SS_Fpu::roundAndPackFloat32( int zSign, int16_t zExp, uint32_t zSig )/*{{{*/
{
/* -------------------------------------------------------------------------------
Takes an abstract floating-point value having sign `zSign', exponent `zExp',
and significand `zSig', and returns the proper single-precision floating-
point value corresponding to the abstract input. Ordinarily, the abstract
value is simply rounded and packed into the single-precision format, with
the inexact exception raised if the abstract input cannot be represented
exactly. However, if the abstract value is too large, the overflow and
inexact exceptions are raised and an infinity or maximal finite value is
returned. If the abstract value is too small, the input value is rounded to
a subnormal number, and the underflow and inexact exceptions are raised if
the abstract input cannot be represented exactly as a subnormal single-
precision floating-point number.
The input significand `zSig' has its binary point between bits 30
and 29, which is 7 bits to the left of the usual location. This shifted
significand must be normalized or smaller. If `zSig' is not normalized,
`zExp' must be 0; in that case, the result returned is a subnormal number,
and it must not require rounding. In the usual case that `zSig' is
normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.
The handling of underflow and overflow follows the IEC/IEEE Standard for
Binary Floating-Point Arithmetic.
-------------------------------------------------------------------------------
*/
int8_t roundingMode;
int roundNearestEven;
int8_t roundIncrement, roundBits;
int isTiny;
roundingMode = float_rounding_mode;
roundNearestEven = ( roundingMode == ROUND_NEAREST );
roundIncrement = 0x40;
if ( ! roundNearestEven ) {
if ( roundingMode == ROUND_TO_ZERO ) {
roundIncrement = 0;
}
else {
roundIncrement = 0x7F;
if ( zSign ) {
if ( roundingMode == ROUND_UP ) roundIncrement = 0;
}
else {
if ( roundingMode == ROUND_DOWN ) roundIncrement = 0;
}
}
}
roundBits = zSig & 0x7F;
if ( 0xFD <= (uint16_t) zExp ) {
if ( ( 0xFD < zExp )
|| ( ( zExp == 0xFD )
&& ( (int32_t) ( zSig + roundIncrement ) < 0 ) )
) {
float_raise( EXC_OVERFLOW | EXC_INEXACT );
return packFloat32( zSign, 0xFF, 0 ) - ( roundIncrement == 0 );
}
if ( zExp < 0 ) {
isTiny =
( float_detect_tininess == TINY_BEFORE_ROUNDING )
|| ( zExp < -1 )
|| ( zSig + roundIncrement < 0x80000000 );
shift32RightJamming( zSig, - zExp, &zSig );
zExp = 0;
roundBits = zSig & 0x7F;
if ( isTiny && roundBits ) float_raise( EXC_UNDERFLOW );
}
}
if ( roundBits ) float_exception_flags = float_exception_flags | EXC_INEXACT;
zSig = ( zSig + roundIncrement )>>7;
zSig &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );
if ( zSig == 0 ) zExp = 0;
return packFloat32( zSign, zExp, zSig );
}
/*}}}*/
uint64_t SS_Fpu::roundAndPackFloat64( int zSign, int16_t zExp, uint64_t zSig )/*{{{*/
{
/* -------------------------------------------------------------------------------
Takes an abstract floating-point value having sign `zSign', exponent `zExp',
and significand `zSig', and returns the proper double-precision floating-
point value corresponding to the abstract input. Ordinarily, the abstract
value is simply rounded and packed into the double-precision format, with
the inexact exception raised if the abstract input cannot be represented
exactly. However, if the abstract value is too large, the overflow and
inexact exceptions are raised and an infinity or maximal finite value is
returned. If the abstract value is too small, the input value is rounded to
a subnormal number, and the underflow and inexact exceptions are raised if
the abstract input cannot be represented exactly as a subnormal double-
precision floating-point number.
The input significand `zSig' has its binary point between bits 62
and 61, which is 10 bits to the left of the usual location. This shifted
significand must be normalized or smaller. If `zSig' is not normalized,
`zExp' must be 0; in that case, the result returned is a subnormal number,
and it must not require rounding. In the usual case that `zSig' is
normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.
The handling of underflow and overflow follows the IEC/IEEE Standard for
Binary Floating-Point Arithmetic.
-------------------------------------------------------------------------------
*/
int8_t roundingMode;
int roundNearestEven;
int16_t roundIncrement, roundBits;
int isTiny;
roundingMode = float_rounding_mode;
roundNearestEven = ( roundingMode == ROUND_NEAREST );
roundIncrement = 0x200;
if ( ! roundNearestEven ) {
if ( roundingMode == ROUND_TO_ZERO ) {
roundIncrement = 0;
}
else {
roundIncrement = 0x3FF;
if ( zSign ) {
if ( roundingMode == ROUND_UP ) roundIncrement = 0;
}
else {
if ( roundingMode == ROUND_DOWN ) roundIncrement = 0;
}
}
}
roundBits = zSig & 0x3FF;
if ( 0x7FD <= (uint16_t) zExp ) {
if ( ( 0x7FD < zExp )
|| ( ( zExp == 0x7FD )
&& ( (int64_t) ( zSig + roundIncrement ) < 0 ) )
) {
float_raise( EXC_OVERFLOW | EXC_INEXACT );
return packFloat64( zSign, 0x7FF, 0 ) - ( roundIncrement == 0 );
}
if ( zExp < 0 ) {
isTiny =
( float_detect_tininess == TINY_BEFORE_ROUNDING )
|| ( zExp < -1 )
|| ( zSig + roundIncrement < 0x8000000000000000 );
shift64RightJamming( zSig, - zExp, &zSig );
zExp = 0;
roundBits = zSig & 0x3FF;
if ( isTiny && roundBits ) float_raise( EXC_UNDERFLOW );
}
}
if ( roundBits ) float_exception_flags = float_exception_flags | EXC_INEXACT;
zSig = ( zSig + roundIncrement )>>10;
zSig &= ~ ( ( ( roundBits ^ 0x200 ) == 0 ) & roundNearestEven );
if ( zSig == 0 ) zExp = 0;
return packFloat64( zSign, zExp, zSig );
}
/*}}}*/
uint32_t SS_Fpu::normalizeRoundAndPackFloat32( int zSign, int16_t zExp, uint32_t zSig )/*{{{*/
{
/* -------------------------------------------------------------------------------
Takes an abstract floating-point value having sign `zSign', exponent `zExp',
and significand `zSig', and returns the proper single-precision floating-
point value corresponding to the abstract input. This routine is just like
`roundAndPackFloat32' except that `zSig' does not have to be normalized.
Bit 31 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''
floating-point exponent.
------------------------------------------------------------------------------- */
int8_t shiftCount;
shiftCount = countLeadingZeros32( zSig ) - 1;
return roundAndPackFloat32( zSign, zExp - shiftCount, zSig<<shiftCount );
}
/*}}}*/
uint64_t SS_Fpu::normalizeRoundAndPackFloat64( int zSign, int16_t zExp, uint64_t zSig )/*{{{*/
{
/* -------------------------------------------------------------------------------
Takes an abstract floating-point value having sign `zSign', exponent `zExp',
and significand `zSig', and returns the proper double-precision floating-
point value corresponding to the abstract input. This routine is just like
`roundAndPackFloat64' except that `zSig' does not have to be normalized.
Bit 63 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''
floating-point exponent.
------------------------------------------------------------------------------- */
int8_t shiftCount;
shiftCount = countLeadingZeros64( zSig ) - 1;
return roundAndPackFloat64( zSign, zExp - shiftCount, zSig<<shiftCount );
}
/*}}}*/
void SS_Fpu::normalizeFloat32Subnormal( uint32_t aSig, int16_t *zExpPtr, uint32_t *zSigPtr )/*{{{*/
{
/* -------------------------------------------------------------------------------
Normalizes the subnormal single-precision floating-point value represented
by the denormalized significand `aSig'. The normalized exponent and
significand are stored at the locations pointed to by `zExpPtr' and
`zSigPtr', respectively.
------------------------------------------------------------------------------- */
int8_t shiftCount;
shiftCount = countLeadingZeros32( aSig ) - 8;
*zSigPtr = aSig<<shiftCount;
*zExpPtr = 1 - shiftCount;
}
/*}}}*/
void SS_Fpu::normalizeFloat64Subnormal( uint64_t aSig, int16_t *zExpPtr, uint64_t *zSigPtr )/*{{{*/
{
/* -------------------------------------------------------------------------------
Normalizes the subnormal double-precision floating-point value represented
by the denormalized significand `aSig'. The normalized exponent and
significand are stored at the locations pointed to by `zExpPtr' and
`zSigPtr', respectively.
------------------------------------------------------------------------------- */
int8_t shiftCount;
shiftCount = countLeadingZeros64( aSig ) - 11;
*zSigPtr = aSig<<shiftCount;
*zExpPtr = 1 - shiftCount;
}
/*}}}*/
uint32_t SS_Fpu::addFloat32Sigs( uint32_t a, uint32_t b, int zSign, int half )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of adding the absolute values of the single-precision
floating-point values `a' and `b'. If `zSign' is 1, the sum is negated
before being returned. `zSign' is ignored if the result is a NaN.
The addition is performed according to the IEC/IEEE Standard for Binary
Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int16_t aExp, bExp, zExp;
uint32_t aSig, bSig, zSig;
int16_t expDiff;
aSig = extractFloat32Frac( a );
aExp = extractFloat32Exp( a );
bSig = extractFloat32Frac( b );
bExp = extractFloat32Exp( b );
expDiff = aExp - bExp;
aSig <<= 6;
bSig <<= 6;
if ( 0 < expDiff ) {
if ( aExp == 0xFF ) {
if ( aSig ) return propagateFloat32NaN( a, b );
return packFloat32( zSign, 0xFF, 0 );
}
if ( bExp == 0 ) {
--expDiff;
}
else {
bSig |= 0x20000000;
}
shift32RightJamming( bSig, expDiff, &bSig );
zExp = aExp;
}
else if ( expDiff < 0 ) {
if ( bExp == 0xFF ) {
if ( bSig ) return propagateFloat32NaN( a, b );
return packFloat32( zSign, 0xFF, 0 );
}
if ( aExp == 0 ) {
++expDiff;
}
else {
aSig |= 0x20000000;
}
shift32RightJamming( aSig, - expDiff, &aSig );
zExp = bExp;
}
else {
if ( aExp == 0xFF ) {
if ( aSig | bSig ) return propagateFloat32NaN( a, b );
return packFloat32( zSign, 0xFF, 0 );
}
if ( aExp == 0 ) {
if (half) {
zSig = aSig + bSig;
if (zSig) {
int8_t shiftCount = countLeadingZeros32(zSig) - 1;
zSig <<= shiftCount;
aExp -= shiftCount;
return roundAndPackFloat32( zSign, aExp, zSig );
}
else
return packFloat32( zSign, 0, 0 );
}
else
return packFloat32( zSign, 0, ( aSig + bSig )>>6 );
}
zSig = 0x40000000 + aSig + bSig;
zExp = aExp;
goto roundAndPack;
}
aSig |= 0x20000000;
zSig = ( aSig + bSig )<<1;
--zExp;
if ( (int32_t) zSig < 0 ) {
zSig = aSig + bSig;
++zExp;
}
roundAndPack:
if (half)
--zExp;
return roundAndPackFloat32( zSign, zExp, zSig );
}
/*}}}*/
uint32_t SS_Fpu::subFloat32Sigs( uint32_t a, uint32_t b, int zSign, int half )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of subtracting the absolute values of the single-
precision floating-point values `a' and `b'. If `zSign' is 1, the
difference is negated before being returned. `zSign' is ignored if the
result is a NaN. The subtraction is performed according to the IEC/IEEE
Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int16_t aExp, bExp, zExp;
uint32_t aSig, bSig, zSig;
int16_t expDiff;
aSig = extractFloat32Frac( a );
aExp = extractFloat32Exp( a );
bSig = extractFloat32Frac( b );
bExp = extractFloat32Exp( b );
expDiff = aExp - bExp;
aSig <<= 7;
bSig <<= 7;
if ( 0 < expDiff ) goto aExpBigger;
if ( expDiff < 0 ) goto bExpBigger;
if ( aExp == 0xFF ) {
if ( aSig | bSig ) return propagateFloat32NaN( a, b );
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
if ( aExp == 0 ) {
aExp = 1;
bExp = 1;
}
if ( bSig < aSig ) goto aBigger;
if ( aSig < bSig ) goto bBigger;
return packFloat32( float_rounding_mode == ROUND_DOWN, 0, 0 );
bExpBigger:
if ( bExp == 0xFF ) {
if ( bSig ) return propagateFloat32NaN( a, b );
return packFloat32( zSign ^ 1, 0xFF, 0 );
}
if ( aExp == 0 ) {
++expDiff;
}
else {
aSig |= 0x40000000;
}
shift32RightJamming( aSig, - expDiff, &aSig );
bSig |= 0x40000000;
bBigger:
zSig = bSig - aSig;
zExp = bExp;
zSign ^= 1;
goto normalizeRoundAndPack;
aExpBigger:
if ( aExp == 0xFF ) {
if ( aSig ) return propagateFloat32NaN( a, b );
return packFloat32( zSign, 0xFF, 0 );
}
if ( bExp == 0 ) {
--expDiff;
}
else {
bSig |= 0x40000000;
}
shift32RightJamming( bSig, expDiff, &bSig );
aSig |= 0x40000000;
aBigger:
zSig = aSig - bSig;
zExp = aExp;
normalizeRoundAndPack:
if (half)
zExp -= 2;
else
--zExp;
return normalizeRoundAndPackFloat32( zSign, zExp, zSig );
}
/*}}}*/
uint64_t SS_Fpu::addFloat64Sigs( uint64_t a, uint64_t b, int zSign, int half )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of adding the absolute values of the double-precision
floating-point values `a' and `b'. If `zSign' is 1, the sum is negated
before being returned. `zSign' is ignored if the result is a NaN.
The addition is performed according to the IEC/IEEE Standard for Binary
Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int16_t aExp, bExp, zExp;
uint64_t aSig, bSig, zSig;
int16_t expDiff;
aSig = extractFloat64Frac( a );
aExp = extractFloat64Exp( a );
bSig = extractFloat64Frac( b );
bExp = extractFloat64Exp( b );
expDiff = aExp - bExp;
aSig <<= 9;
bSig <<= 9;
if ( 0 < expDiff ) {
if ( aExp == 0x7FF ) {
if ( aSig ) return propagateFloat64NaN( a, b );
return packFloat64( zSign, 0x7FF, 0 );
}
if ( bExp == 0 ) {
--expDiff;
}
else {
bSig |= 0x2000000000000000 ;
}
shift64RightJamming( bSig, expDiff, &bSig );
zExp = aExp;
}
else if ( expDiff < 0 ) {
if ( bExp == 0x7FF ) {
if ( bSig ) return propagateFloat64NaN( a, b );
return packFloat64( zSign, 0x7FF, 0 );
}
if ( aExp == 0 ) {
++expDiff;
}
else {
aSig |= 0x2000000000000000 ;
}
shift64RightJamming( aSig, - expDiff, &aSig );
zExp = bExp;
}
else {
if ( aExp == 0x7FF ) {
if ( aSig | bSig ) return propagateFloat64NaN( a, b );
return packFloat64( zSign, 0x7FF, 0 );
}
if ( aExp == 0 ) {
if (half) {
zSig = aSig + bSig;
if (zSig) {
int8_t shiftCount = countLeadingZeros64(zSig) - 1;
zSig <<= shiftCount;
aExp -= shiftCount;
return roundAndPackFloat64( zSign, aExp, zSig );
}
else
return packFloat64( zSign, 0, 0 );
}
else
return packFloat64( zSign, 0, ( aSig + bSig )>>9 );
}
zSig = 0x4000000000000000 + aSig + bSig;
zExp = aExp;
goto roundAndPack;
}
aSig |= 0x2000000000000000 ;
zSig = ( aSig + bSig )<<1;
--zExp;
if ( (int64_t) zSig < 0 ) {
zSig = aSig + bSig;
++zExp;
}
roundAndPack:
if (half)
--zExp;
return roundAndPackFloat64( zSign, zExp, zSig );
}
/*}}}*/
uint64_t SS_Fpu::subFloat64Sigs( uint64_t a, uint64_t b, int zSign, int half )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of subtracting the absolute values of the double-
precision floating-point values `a' and `b'. If `zSign' is 1, the
difference is negated before being returned. `zSign' is ignored if the
result is a NaN. The subtraction is performed according to the IEC/IEEE
Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int16_t aExp, bExp, zExp;
uint64_t aSig, bSig, zSig;
int16_t expDiff;
aSig = extractFloat64Frac( a );
aExp = extractFloat64Exp( a );
bSig = extractFloat64Frac( b );
bExp = extractFloat64Exp( b );
expDiff = aExp - bExp;
aSig <<= 10;
bSig <<= 10;
if ( 0 < expDiff ) goto aExpBigger;
if ( expDiff < 0 ) goto bExpBigger;
if ( aExp == 0x7FF ) {
if ( aSig | bSig ) return propagateFloat64NaN( a, b );
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
if ( aExp == 0 ) {
aExp = 1;
bExp = 1;
}
if ( bSig < aSig ) goto aBigger;
if ( aSig < bSig ) goto bBigger;
return packFloat64( float_rounding_mode == ROUND_DOWN, 0, 0 );
bExpBigger:
if ( bExp == 0x7FF ) {
if ( bSig ) return propagateFloat64NaN( a, b );
return packFloat64( zSign ^ 1, 0x7FF, 0 );
}
if ( aExp == 0 ) {
++expDiff;
}
else {
aSig |= 0x4000000000000000 ;
}
shift64RightJamming( aSig, - expDiff, &aSig );
bSig |= 0x4000000000000000 ;
bBigger:
zSig = bSig - aSig;
zExp = bExp;
zSign ^= 1;
goto normalizeRoundAndPack;
aExpBigger:
if ( aExp == 0x7FF ) {
if ( aSig ) return propagateFloat64NaN( a, b );
return packFloat64( zSign, 0x7FF, 0 );
}
if ( bExp == 0 ) {
--expDiff;
}
else {
bSig |= 0x4000000000000000 ;
}
shift64RightJamming( bSig, expDiff, &bSig );
aSig |= 0x4000000000000000 ;
aBigger:
zSig = aSig - bSig;
zExp = aExp;
normalizeRoundAndPack:
if (half)
zExp -= 2;
else
--zExp;
return normalizeRoundAndPackFloat64( zSign, zExp, zSig );
}
/*}}}*/
uint32_t SS_Fpu::int32_to_float32( int32_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the 32-bit two's complement integer `a'
to the single-precision floating-point format. The conversion is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int zSign;
if ( a == 0 ) return 0;
if ( a == (int32_t) 0x80000000 ) return packFloat32( 1, 0x9E, 0 );
zSign = ( a < 0 );
return normalizeRoundAndPackFloat32( zSign, 0x9C, zSign ? - a : a );
}
/*}}}*/
uint64_t SS_Fpu::int32_to_float64( int32_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the 32-bit two's complement integer `a'
to the double-precision floating-point format. The conversion is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int zSign;
uint32_t absA;
int8_t shiftCount;
uint64_t zSig;
if ( a == 0 ) return 0;
zSign = ( a < 0 );
absA = zSign ? - a : a;
shiftCount = countLeadingZeros32( absA ) + 21;
zSig = absA;
return packFloat64( zSign, 0x432 - shiftCount, zSig<<shiftCount );
}
/*}}}*/
uint32_t SS_Fpu::int64_to_float32( int64_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the 64-bit two's complement integer `a'
to the single-precision floating-point format. The conversion is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int zSign;
uint64_t absA;
int8_t shiftCount;
if ( a == 0 ) return 0;
zSign = ( a < 0 );
absA = zSign ? - a : a;
shiftCount = countLeadingZeros64( absA ) - 40;
if ( 0 <= shiftCount ) {
return packFloat32( zSign, 0x95 - shiftCount, absA<<shiftCount );
}
else {
shiftCount += 7;
if ( shiftCount < 0 ) {
shift64RightJamming( absA, - shiftCount, &absA );
}
else {
absA <<= shiftCount;
}
return roundAndPackFloat32( zSign, 0x9C - shiftCount, absA );
}
}
/*}}}*/
uint64_t SS_Fpu::int64_to_float64( int64_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the 64-bit two's complement integer `a'
to the double-precision floating-point format. The conversion is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int zSign;
if ( a == 0 ) return 0;
if ( a == (int64_t) 0x8000000000000000 ) {
return packFloat64( 1, 0x43E, 0 );
}
zSign = ( a < 0 );
return normalizeRoundAndPackFloat64( zSign, 0x43C, zSign ? - a : a );
}
/*}}}*/
int32_t SS_Fpu::float32_to_int32( uint32_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the single-precision floating-point value
`a' to the 32-bit two's complement integer format. The conversion is
performed according to the IEC/IEEE Standard for Binary Floating-Point
Arithmetic---which means in particular that the conversion is rounded
according to the current rounding mode. If `a' is a NaN, the largest
positive integer is returned. Otherwise, if the conversion overflows, the
largest integer with the same sign as `a' is returned.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp, shiftCount;
uint32_t aSig;
uint64_t aSig64;
aSig = extractFloat32Frac( a );
aExp = extractFloat32Exp( a );
aSign = extractFloat32Sign( a );
//if ( ( aExp == 0xFF ) && aSig ) aSign = 0;
if ( aExp ) aSig |= 0x00800000;
shiftCount = 0xAF - aExp;
aSig64 = aSig;
aSig64 <<= 32;
if ( 0 < shiftCount ) shift64RightJamming( aSig64, shiftCount, &aSig64 );
return roundAndPackInt32( aSign, aSig64 );
}
/*}}}*/
int64_t SS_Fpu::float32_to_int64( uint32_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the single-precision floating-point value
`a' to the 64-bit two's complement integer format. The conversion is
performed according to the IEC/IEEE Standard for Binary Floating-Point
Arithmetic---which means in particular that the conversion is rounded
according to the current rounding mode. If `a' is a NaN, the largest
positive integer is returned. Otherwise, if the conversion overflows, the
largest integer with the same sign as `a' is returned.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp, shiftCount;
uint32_t aSig;
uint64_t aSig64, aSigExtra;
aSig = extractFloat32Frac( a );
aExp = extractFloat32Exp( a );
aSign = extractFloat32Sign( a );
shiftCount = 0xBE - aExp;
if ( shiftCount < 0 ) {
float_raise( EXC_INVALID );
if ( ! aSign ) {
return 0x7FFFFFFFFFFFFFFF ;
}
return (int64_t) 0x8000000000000000 ;
}
if ( aExp ) aSig |= 0x00800000;
aSig64 = aSig;
aSig64 <<= 40;
shift64ExtraRightJamming( aSig64, 0, shiftCount, &aSig64, &aSigExtra );
return roundAndPackInt64( aSign, aSig64, aSigExtra );
}
/*}}}*/
uint64_t SS_Fpu::float32_to_float64( uint32_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the single-precision floating-point value
`a' to the double-precision floating-point format. The conversion is
performed according to the IEC/IEEE Standard for Binary Floating-Point
Arithmetic.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp;
uint32_t aSig;
aSig = extractFloat32Frac( a );
aExp = extractFloat32Exp( a );
aSign = extractFloat32Sign( a );
if ( aExp == 0xFF ) {
if ( aSig )
{
if ( float32_is_signaling_nan( a ) ) float_raise( EXC_INVALID );
return (((uint64_t)(a >> 31)) <<63 ) | 0x7FF8000000000000 | (uint64_t(aSig) << 29);
}
return packFloat64( aSign, 0x7FF, 0 );
}
if ( aExp == 0 ) {
if ( aSig == 0 ) return packFloat64( aSign, 0, 0 );
normalizeFloat32Subnormal( aSig, &aExp, &aSig );
--aExp;
}
return packFloat64( aSign, aExp + 0x380, ( (uint64_t) aSig )<<29 );
}
/*}}}*/
int32_t SS_Fpu::float64_to_int32( uint64_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the double-precision floating-point value
`a' to the 32-bit two's complement integer format. The conversion is
performed according to the IEC/IEEE Standard for Binary Floating-Point
Arithmetic---which means in particular that the conversion is rounded
according to the current rounding mode. If `a' is a NaN, the largest
positive integer is returned. Otherwise, if the conversion overflows, the
largest integer with the same sign as `a' is returned.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp, shiftCount;
uint64_t aSig;
aSig = extractFloat64Frac( a );
aExp = extractFloat64Exp( a );
aSign = extractFloat64Sign( a );
//if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;
if ( aExp ) aSig |= 0x0010000000000000 ;
shiftCount = 0x42C - aExp;
if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig );
return roundAndPackInt32( aSign, aSig );
}
/*}}}*/
int64_t SS_Fpu::float64_to_int64( uint64_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the double-precision floating-point value
`a' to the 64-bit two's complement integer format. The conversion is
performed according to the IEC/IEEE Standard for Binary Floating-Point
Arithmetic---which means in particular that the conversion is rounded
according to the current rounding mode. If `a' is a NaN, the largest
positive integer is returned. Otherwise, if the conversion overflows, the
largest integer with the same sign as `a' is returned.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp, shiftCount;
uint64_t aSig, aSigExtra;
aSig = extractFloat64Frac( a );
aExp = extractFloat64Exp( a );
aSign = extractFloat64Sign( a );
if ( aExp ) aSig |= 0x0010000000000000 ;
shiftCount = 0x433 - aExp;
if ( shiftCount <= 0 ) {
if ( 0x43E < aExp ) {
float_raise( EXC_INVALID );
if (! aSign) {
return 0x7FFFFFFFFFFFFFFF ;
}
return (int64_t) 0x8000000000000000 ;
}
aSigExtra = 0;
aSig <<= - shiftCount;
}
else {
shift64ExtraRightJamming( aSig, 0, shiftCount, &aSig, &aSigExtra );
}
return roundAndPackInt64( aSign, aSig, aSigExtra );
}
/*}}}*/
uint32_t SS_Fpu::float64_to_float32( uint64_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of converting the double-precision floating-point value
`a' to the single-precision floating-point format. The conversion is
performed according to the IEC/IEEE Standard for Binary Floating-Point
Arithmetic.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp;
uint64_t aSig;
uint32_t zSig;
aSig = extractFloat64Frac( a );
aExp = extractFloat64Exp( a );
aSign = extractFloat64Sign( a );
if ( aExp == 0x7FF ) {
if ( aSig )
{
if ( float64_is_signaling_nan( a ) ) float_raise( EXC_INVALID );
return (uint32_t(a >>63) << 31) | 0x7FC00000 | ((a << 12) >> 41);
}
return packFloat32( aSign, 0xFF, 0 );
}
shift64RightJamming( aSig, 22, &aSig );
zSig = aSig;
if ( aExp || zSig ) {
zSig |= 0x40000000;
aExp -= 0x381;
}
return roundAndPackFloat32( aSign, aExp, zSig );
}
/*}}}*/
uint32_t SS_Fpu::float32_add( uint32_t a, uint32_t b, int flipSign, int half )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of adding the single-precision floating-point values `a'
and `b'. The operation is performed according to the IEC/IEEE Standard for
Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign, zSign;
aSign = extractFloat32Sign( a );
bSign = extractFloat32Sign( b );
zSign = aSign;
if (flipSign)
zSign ^= 1;
if ( aSign == bSign )
return addFloat32Sigs( a, b, zSign, half );
else
return subFloat32Sigs( a, b, zSign, half );
}
/*}}}*/
uint32_t SS_Fpu::float32_sub( uint32_t a, uint32_t b, int flipSign, int half )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of subtracting the single-precision floating-point values
`a' and `b'. The operation is performed according to the IEC/IEEE Standard
for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign, zSign;
aSign = extractFloat32Sign( a );
bSign = extractFloat32Sign( b );
zSign = aSign;
if (flipSign)
zSign ^= 1;
if ( aSign == bSign )
return subFloat32Sigs( a, b, zSign, half );
else
return addFloat32Sigs( a, b, zSign, half );
}
/*}}}*/
uint32_t SS_Fpu::float32_mul( uint32_t a, uint32_t b, int flipSign )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of multiplying the single-precision floating-point values
`a' and `b'. The operation is performed according to the IEC/IEEE Standard
for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign, zSign;
int16_t aExp, bExp, zExp;
uint32_t aSig, bSig;
uint64_t zSig64;
uint32_t zSig;
uint32_t ra, rb;
int check_float_round_needed = 0;
float_round_needed = 0;
aSig = extractFloat32Frac( a );
aExp = extractFloat32Exp( a );
aSign = extractFloat32Sign( a );
bSig = extractFloat32Frac( b );
bExp = extractFloat32Exp( b );
bSign = extractFloat32Sign( b );
zSign = aSign ^ bSign;
if (flipSign)
zSign ^= 1;
if ( aExp == 0xFF ) {
if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
return propagateFloat32NaN( a, b );
}
if ( ( bExp | bSig ) == 0 ) {
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
return packFloat32( zSign, 0xFF, 0 );
}
if ( bExp == 0xFF ) {
if ( bSig ) return propagateFloat32NaN( a, b );
if ( ( aExp | aSig ) == 0 ) {
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
return packFloat32( zSign, 0xFF, 0 );
}
if ( aExp == 0 ) {
if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );
normalizeFloat32Subnormal( aSig, &aExp, &aSig );
}
if ( bExp == 0 ) {
if ( bSig == 0 ) return packFloat32( zSign, 0, 0 );
normalizeFloat32Subnormal( bSig, &bExp, &bSig );
}
zExp = aExp + bExp - 0x7F;
aSig = ( aSig | 0x00800000 )<<7;
bSig = ( bSig | 0x00800000 )<<8;
shift64RightJamming( ( (uint64_t) aSig ) * bSig, 32, &zSig64 );
zSig = zSig64;
if ( 0 <= (int32_t) ( zSig<<1 ) ) {
zSig <<= 1;
--zExp;
if (((zSig >> 7) & 0x7) == 0x7)
check_float_round_needed = 1;
}
/* Check overflow/underflow before rounding for unfused multiply. Remember,
* zExp is one less than true value. */
if (zExp > 0xFD)
float_partial_exception_flags = float_partial_exception_flags | EXC_OVERFLOW;
else if (zExp < 0)
float_partial_exception_flags = float_partial_exception_flags | EXC_UNDERFLOW;
if (check_float_round_needed && (zExp == 0xFD)) {
ra = packFloat32( zSign, zExp, zSig >> 7 );
rb = roundAndPackFloat32( zSign, zExp, zSig );
if (ra != rb)
float_round_needed = 1;
return rb;
}
return roundAndPackFloat32( zSign, zExp, zSig );
}
/*}}}*/
uint32_t SS_Fpu::float32_div( uint32_t a, uint32_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of dividing the single-precision floating-point value `a'
by the corresponding value `b'. The operation is performed according to the
IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign, zSign;
int16_t aExp, bExp, zExp;
uint32_t aSig, bSig, zSig;
aSig = extractFloat32Frac( a );
aExp = extractFloat32Exp( a );
aSign = extractFloat32Sign( a );
bSig = extractFloat32Frac( b );
bExp = extractFloat32Exp( b );
bSign = extractFloat32Sign( b );
zSign = aSign ^ bSign;
if ( aExp == 0xFF ) {
if ( aSig ) return propagateFloat32NaN( a, b );
if ( bExp == 0xFF ) {
if ( bSig ) return propagateFloat32NaN( a, b );
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
return packFloat32( zSign, 0xFF, 0 );
}
if ( bExp == 0xFF ) {
if ( bSig ) return propagateFloat32NaN( a, b );
return packFloat32( zSign, 0, 0 );
}
if ( bExp == 0 ) {
if ( bSig == 0 ) {
if ( ( aExp | aSig ) == 0 ) {
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
float_raise( EXC_DIVBYZERO );
return packFloat32( zSign, 0xFF, 0 );
}
normalizeFloat32Subnormal( bSig, &bExp, &bSig );
}
if ( aExp == 0 ) {
if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );
normalizeFloat32Subnormal( aSig, &aExp, &aSig );
}
zExp = aExp - bExp + 0x7D;
aSig = ( aSig | 0x00800000 )<<7;
bSig = ( bSig | 0x00800000 )<<8;
if ( bSig <= ( aSig + aSig ) ) {
aSig >>= 1;
++zExp;
}
zSig = ( ( (uint64_t) aSig )<<32 ) / bSig;
if ( ( zSig & 0x3F ) == 0 ) {
zSig |= ( (uint64_t) bSig * zSig != ( (uint64_t) aSig )<<32 );
}
return roundAndPackFloat32( zSign, zExp, zSig );
}
/*}}}*/
uint32_t SS_Fpu::float32_sqrt( uint32_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the square root of the single-precision floating-point value `a'.
The operation is performed according to the IEC/IEEE Standard for Binary
Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp, zExp;
uint32_t aSig, zSig;
uint64_t rem, term;
aSig = extractFloat32Frac( a );
aExp = extractFloat32Exp( a );
aSign = extractFloat32Sign( a );
if ( aExp == 0xFF ) {
if ( aSig ) return propagateFloat32NaN( a, 0 );
if ( ! aSign ) return a;
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
if ( aSign ) {
if ( ( aExp | aSig ) == 0 ) return a;
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
if ( aExp == 0 ) {
if ( aSig == 0 ) return 0;
normalizeFloat32Subnormal( aSig, &aExp, &aSig );
}
zExp = ( ( aExp - 0x7F )>>1 ) + 0x7E;
aSig = ( aSig | 0x00800000 )<<8;
zSig = estimateSqrt32( aExp, aSig ) + 2;
if ( ( zSig & 0x7F ) <= 5 ) {
if ( zSig < 2 ) {
zSig = 0x7FFFFFFF;
goto roundAndPack;
}
aSig >>= aExp & 1;
term = ( (uint64_t) zSig ) * zSig;
rem = ( ( (uint64_t) aSig )<<32 ) - term;
while ( (int64_t) rem < 0 ) {
--zSig;
rem += ( ( (uint64_t) zSig )<<1 ) | 1;
}
zSig |= ( rem != 0 );
}
shift32RightJamming( zSig, 1, &zSig );
roundAndPack:
return roundAndPackFloat32( 0, zExp, zSig );
}
/*}}}*/
uint32_t SS_Fpu::float32_rsqrt( uint32_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Reciprocal square root.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp, tExp, zExp;
uint32_t aSig, tSig, oneSig, zSig;
uint64_t rem, term;
aSig = extractFloat32Frac( a );
aExp = extractFloat32Exp( a );
aSign = extractFloat32Sign( a );
if ( aExp == 0xFF ) {
if ( aSig ) return propagateFloat32NaN( a, 0 );
if ( ! aSign ) return 0;
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
if ( aSign ) {
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
if ( aExp == 0 ) {
if ( aSig == 0 ) {
float_raise( EXC_DIVBYZERO );
return 0x7F800000;
}
normalizeFloat32Subnormal( aSig, &aExp, &aSig );
}
tExp = ( ( aExp - 0x7F )>>1 ) + 0x7E;
aSig = ( aSig | 0x00800000 )<<8;
tSig = estimateSqrt32( aExp, aSig ) + 2;
if ( ( tSig & 0x7F ) <= 5 ) {
if ( tSig < 2 ) {
tSig = 0x7FFFFFFF;
goto cont1;
}
aSig >>= aExp & 1;
term = ( (uint64_t) tSig ) * tSig;
rem = ( ( (uint64_t) aSig )<<32 ) - term;
while ( (int64_t) rem < 0 ) {
--tSig;
rem += ( ( (uint64_t) tSig )<<1 ) | 1;
}
tSig |= ( rem != 0 );
}
shift32RightJamming( tSig, 1, &tSig );
cont1:
/* We have just finished sqrt() now comes reciprocal 1/sqrt().
* Remember that tExp is 1 less than true value.
*/
zExp = 0xFB - tExp;
oneSig = 0x40000000;
tSig <<= 1;
if ( tSig <= ( oneSig + oneSig ) ) {
oneSig >>= 1;
++zExp;
}
zSig = ( ( (int64_t) oneSig )<<32 ) / tSig;
if ( ( zSig & 0x3F ) == 0 ) {
zSig |= ( (int64_t) tSig * zSig != ( (int64_t) oneSig )<<32 );
}
return roundAndPackFloat32( 0, zExp, zSig );
}
/*}}}*/
uint64_t SS_Fpu::float64_add( uint64_t a, uint64_t b, int flipSign, int half )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of adding the double-precision floating-point values `a'
and `b'. The operation is performed according to the IEC/IEEE Standard for
Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign, zSign;
aSign = extractFloat64Sign( a );
bSign = extractFloat64Sign( b );
zSign = aSign;
if (flipSign)
zSign ^= 1;
if ( aSign == bSign )
return addFloat64Sigs( a, b, zSign, half );
else
return subFloat64Sigs( a, b, zSign, half );
}
/*}}}*/
uint64_t SS_Fpu::float64_sub( uint64_t a, uint64_t b, int flipSign, int half )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of subtracting the double-precision floating-point values
`a' and `b'. The operation is performed according to the IEC/IEEE Standard
for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign, zSign;
aSign = extractFloat64Sign( a );
bSign = extractFloat64Sign( b );
zSign = aSign;
if (flipSign)
zSign ^= 1;
if ( aSign == bSign )
return subFloat64Sigs( a, b, zSign, half );
else
return addFloat64Sigs( a, b, zSign, half );
}
/*}}}*/
uint64_t SS_Fpu::float64_mul( uint64_t a, uint64_t b, int flipSign )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of multiplying the double-precision floating-point values
`a' and `b'. The operation is performed according to the IEC/IEEE Standard
for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign, zSign;
int16_t aExp, bExp, zExp;
uint64_t aSig, bSig, zSig0, zSig1;
uint64_t ra, rb;
int check_float_round_needed = 0;
float_round_needed = 0;
aSig = extractFloat64Frac( a );
aExp = extractFloat64Exp( a );
aSign = extractFloat64Sign( a );
bSig = extractFloat64Frac( b );
bExp = extractFloat64Exp( b );
bSign = extractFloat64Sign( b );
zSign = aSign ^ bSign;
if (flipSign)
zSign ^= 1;
if ( aExp == 0x7FF ) {
if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {
return propagateFloat64NaN( a, b );
}
if ( ( bExp | bSig ) == 0 ) {
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
return packFloat64( zSign, 0x7FF, 0 );
}
if ( bExp == 0x7FF ) {
if ( bSig ) return propagateFloat64NaN( a, b );
if ( ( aExp | aSig ) == 0 ) {
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
return packFloat64( zSign, 0x7FF, 0 );
}
if ( aExp == 0 ) {
if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );
normalizeFloat64Subnormal( aSig, &aExp, &aSig );
}
if ( bExp == 0 ) {
if ( bSig == 0 ) return packFloat64( zSign, 0, 0 );
normalizeFloat64Subnormal( bSig, &bExp, &bSig );
}
zExp = aExp + bExp - 0x3FF;
aSig = ( aSig | 0x0010000000000000 )<<10;
bSig = ( bSig | 0x0010000000000000 )<<11;
mul64To128( aSig, bSig, &zSig0, &zSig1 );
zSig0 |= ( zSig1 != 0 );
if ( 0 <= (int64_t) ( zSig0<<1 ) ) {
zSig0 <<= 1;
--zExp;
if (((zSig0 >> 10) & 0x7) == 0x7)
check_float_round_needed = 1;
}
/* Check overflow/underflow before rounding for unfused multiply. Remember,
* zExp is one less than true value. */
if (zExp > 0x7FD)
float_partial_exception_flags = float_partial_exception_flags | EXC_OVERFLOW;
else if (zExp < 0)
float_partial_exception_flags = float_partial_exception_flags | EXC_UNDERFLOW;
if (check_float_round_needed && (zExp == 0x7FD)) {
ra = packFloat64( zSign, zExp, zSig0 >> 10 );
rb = roundAndPackFloat64( zSign, zExp, zSig0 );
if (ra != rb)
float_round_needed = 1;
return rb;
}
return roundAndPackFloat64( zSign, zExp, zSig0 );
}
/*}}}*/
uint64_t SS_Fpu::float64_div( uint64_t a, uint64_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the result of dividing the double-precision floating-point value `a'
by the corresponding value `b'. The operation is performed according to
the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign, zSign;
int16_t aExp, bExp, zExp;
uint64_t aSig, bSig, zSig;
uint64_t rem0, rem1;
uint64_t term0, term1;
aSig = extractFloat64Frac( a );
aExp = extractFloat64Exp( a );
aSign = extractFloat64Sign( a );
bSig = extractFloat64Frac( b );
bExp = extractFloat64Exp( b );
bSign = extractFloat64Sign( b );
zSign = aSign ^ bSign;
if ( aExp == 0x7FF ) {
if ( aSig ) return propagateFloat64NaN( a, b );
if ( bExp == 0x7FF ) {
if ( bSig ) return propagateFloat64NaN( a, b );
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
return packFloat64( zSign, 0x7FF, 0 );
}
if ( bExp == 0x7FF ) {
if ( bSig ) return propagateFloat64NaN( a, b );
return packFloat64( zSign, 0, 0 );
}
if ( bExp == 0 ) {
if ( bSig == 0 ) {
if ( ( aExp | aSig ) == 0 ) {
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
float_raise( EXC_DIVBYZERO );
return packFloat64( zSign, 0x7FF, 0 );
}
normalizeFloat64Subnormal( bSig, &bExp, &bSig );
}
if ( aExp == 0 ) {
if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );
normalizeFloat64Subnormal( aSig, &aExp, &aSig );
}
zExp = aExp - bExp + 0x3FD;
aSig = ( aSig | 0x0010000000000000 )<<10;
bSig = ( bSig | 0x0010000000000000 )<<11;
if ( bSig <= ( aSig + aSig ) ) {
aSig >>= 1;
++zExp;
}
zSig = estimateDiv128To64( aSig, 0, bSig );
if ( ( zSig & 0x1FF ) <= 2 ) {
mul64To128( bSig, zSig, &term0, &term1 );
sub128( aSig, 0, term0, term1, &rem0, &rem1 );
while ( (int64_t) rem0 < 0 ) {
--zSig;
add128( rem0, rem1, 0, bSig, &rem0, &rem1 );
}
zSig |= ( rem1 != 0 );
}
return roundAndPackFloat64( zSign, zExp, zSig );
}
/*}}}*/
uint64_t SS_Fpu::float64_sqrt( uint64_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns the square root of the double-precision floating-point value `a'.
The operation is performed according to the IEC/IEEE Standard for Binary
Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp, zExp;
uint64_t aSig, zSig, doubleZSig;
uint64_t rem0, rem1, term0, term1;
aSig = extractFloat64Frac( a );
aExp = extractFloat64Exp( a );
aSign = extractFloat64Sign( a );
if ( aExp == 0x7FF ) {
if ( aSig ) return propagateFloat64NaN( a, a );
if ( ! aSign ) return a;
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
if ( aSign ) {
if ( ( aExp | aSig ) == 0 ) return a;
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
if ( aExp == 0 ) {
if ( aSig == 0 ) return 0;
normalizeFloat64Subnormal( aSig, &aExp, &aSig );
}
zExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE;
aSig |= 0x0010000000000000 ;
zSig = estimateSqrt32( aExp, aSig>>21 );
aSig <<= 9 - ( aExp & 1 );
zSig = estimateDiv128To64( aSig, 0, zSig<<32 ) + ( zSig<<30 );
if ( ( zSig & 0x1FF ) <= 5 ) {
doubleZSig = zSig<<1;
mul64To128( zSig, zSig, &term0, &term1 );
sub128( aSig, 0, term0, term1, &rem0, &rem1 );
while ( (int64_t) rem0 < 0 ) {
--zSig;
doubleZSig -= 2;
add128( rem0, rem1, zSig>>63, doubleZSig | 1, &rem0, &rem1 );
}
zSig |= ( ( rem0 | rem1 ) != 0 );
}
return roundAndPackFloat64( 0, zExp, zSig );
}
/*}}}*/
uint64_t SS_Fpu::float64_rsqrt( uint64_t a )/*{{{*/
{
/* -------------------------------------------------------------------------------
Reciprocal square root.
------------------------------------------------------------------------------- */
int aSign;
int16_t aExp, tExp, zExp;
uint64_t aSig, tSig, zSig, doubleZSig, oneSig;
uint64_t rem0, rem1, term0, term1;
aSig = extractFloat64Frac( a );
aExp = extractFloat64Exp( a );
aSign = extractFloat64Sign( a );
if ( aExp == 0x7FF ) {
if ( aSig ) return propagateFloat64NaN( a, a );
if ( ! aSign ) return 0;
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
if ( aSign ) {
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
if ( aExp == 0 ) {
if ( aSig == 0 ) {
float_raise( EXC_DIVBYZERO );
return 0x7FF0000000000000;
}
normalizeFloat64Subnormal( aSig, &aExp, &aSig );
}
tExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE;
aSig |= 0x0010000000000000 ;
tSig = estimateSqrt32( aExp, aSig>>21 );
aSig <<= 9 - ( aExp & 1 );
tSig = estimateDiv128To64( aSig, 0, tSig<<32 ) + ( tSig<<30 );
if ( ( tSig & 0x1FF ) <= 5 ) {
doubleZSig = tSig<<1;
mul64To128( tSig, tSig, &term0, &term1 );
sub128( aSig, 0, term0, term1, &rem0, &rem1 );
while ( (int64_t) rem0 < 0 ) {
--tSig;
doubleZSig -= 2;
add128( rem0, rem1, tSig>>63, doubleZSig | 1, &rem0, &rem1 );
}
tSig |= ( ( rem0 | rem1 ) != 0 );
}
/* We have just finished sqrt() now comes reciprocal 1/sqrt().
* Remember that tExp is 1 less than true value.
*/
zExp = 0x7FB - tExp;
oneSig = 0x4000000000000000;
tSig <<= 1;
if ( tSig <= ( oneSig + oneSig ) ) {
oneSig >>= 1;
++zExp;
}
zSig = estimateDiv128To64( oneSig, 0, tSig );
if ( ( zSig & 0x1FF ) <= 2 ) {
mul64To128( tSig, zSig, &term0, &term1 );
sub128( oneSig, 0, term0, term1, &rem0, &rem1 );
while ( (int64_t) rem0 < 0 ) {
--zSig;
add128( rem0, rem1, 0, tSig, &rem0, &rem1 );
}
zSig |= ( rem1 != 0 );
}
return roundAndPackFloat64( 0, zExp, zSig );
}
/*}}}*/
int SS_Fpu::float32_eq( uint32_t a, uint32_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns 1 if the single-precision floating-point value `a' is equal to
the corresponding value `b', and 0 otherwise. The comparison is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
) {
if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
float_raise( EXC_INVALID );
}
return 0;
}
return ( a == b ) || ( (uint32_t) ( ( a | b )<<1 ) == 0 );
}
/*}}}*/
int SS_Fpu::float32_lt( uint32_t a, uint32_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns 1 if the single-precision floating-point value `a' is less than
the corresponding value `b', and 0 otherwise. The comparison is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign;
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
) {
float_raise( EXC_INVALID );
return 0;
}
aSign = extractFloat32Sign( a );
bSign = extractFloat32Sign( b );
if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( a | b )<<1 ) != 0 );
return ( a != b ) && ( aSign ^ ( a < b ) );
}
/*}}}*/
int SS_Fpu::float32_eq_signaling( uint32_t a, uint32_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns 1 if the single-precision floating-point value `a' is equal to
the corresponding value `b', and 0 otherwise. The invalid exception is
raised if either operand is a NaN. Otherwise, the comparison is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
) {
float_raise( EXC_INVALID );
return 0;
}
return ( a == b ) || ( (uint32_t) ( ( a | b )<<1 ) == 0 );
}
/*}}}*/
int SS_Fpu::float32_lt_quiet( uint32_t a, uint32_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns 1 if the single-precision floating-point value `a' is less than
the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
exception. Otherwise, the comparison is performed according to the IEC/IEEE
Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign;
if ( ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )
|| ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )
) {
if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {
float_raise( EXC_INVALID );
}
return 0;
}
aSign = extractFloat32Sign( a );
bSign = extractFloat32Sign( b );
if ( aSign != bSign ) return aSign && ( (uint32_t) ( ( a | b )<<1 ) != 0 );
return ( a != b ) && ( aSign ^ ( a < b ) );
}
/*}}}*/
int SS_Fpu::float64_eq( uint64_t a, uint64_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns 1 if the double-precision floating-point value `a' is equal to the
corresponding value `b', and 0 otherwise. The comparison is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
) {
if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
float_raise( EXC_INVALID );
}
return 0;
}
return ( a == b ) || ( (uint64_t) ( ( a | b )<<1 ) == 0 );
}
/*}}}*/
int SS_Fpu::float64_lt( uint64_t a, uint64_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns 1 if the double-precision floating-point value `a' is less than
the corresponding value `b', and 0 otherwise. The comparison is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign;
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
) {
float_raise( EXC_INVALID );
return 0;
}
aSign = extractFloat64Sign( a );
bSign = extractFloat64Sign( b );
if ( aSign != bSign ) return aSign && ( (uint64_t) ( ( a | b )<<1 ) != 0 );
return ( a != b ) && ( aSign ^ ( a < b ) );
}
/*}}}*/
int SS_Fpu::float64_eq_signaling( uint64_t a, uint64_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns 1 if the double-precision floating-point value `a' is equal to the
corresponding value `b', and 0 otherwise. The invalid exception is raised
if either operand is a NaN. Otherwise, the comparison is performed
according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
) {
float_raise( EXC_INVALID );
return 0;
}
return ( a == b ) || ( (uint64_t) ( ( a | b )<<1 ) == 0 );
}
/*}}}*/
int SS_Fpu::float64_lt_quiet( uint64_t a, uint64_t b )/*{{{*/
{
/* -------------------------------------------------------------------------------
Returns 1 if the double-precision floating-point value `a' is less than
the corresponding value `b', and 0 otherwise. Quiet NaNs do not cause an
exception. Otherwise, the comparison is performed according to the IEC/IEEE
Standard for Binary Floating-Point Arithmetic.
------------------------------------------------------------------------------- */
int aSign, bSign;
if ( ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )
|| ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )
) {
if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {
float_raise( EXC_INVALID );
}
return 0;
}
aSign = extractFloat64Sign( a );
bSign = extractFloat64Sign( b );
if ( aSign != bSign ) return aSign && ( (uint64_t) ( ( a | b )<<1 ) != 0 );
return ( a != b ) && ( aSign ^ ( a < b ) );
}
/*}}}*/
uint32_t SS_Fpu::float32_madd(uint32_t a, uint32_t b, uint32_t c, int isSub, int flipSign)/*{{{*/
{
/*
-------------------------------------------------------------------------------
Returns the result (a*b+c) of fused multiply-add operation on the
single-precision floating-point values `a', `b', and `c'. The operation is
performed according to the IEC/IEEE Standard for Binary Floating-Point
Arithmetic.
-------------------------------------------------------------------------------
*/
int aSign, bSign, cSign, pSign, zSign;
int16_t aExp, bExp, cExp, pExp, zExp, expDiff;
uint32_t aSig, bSig, cSig, zSig;
uint64_t pSig64, cSig64, zSig64;
uint32_t pRes;
int8_t shiftCount;
aSign = extractFloat32Sign(a);
aExp = extractFloat32Exp(a);
aSig = extractFloat32Frac(a);
bSign = extractFloat32Sign(b);
bExp = extractFloat32Exp(b);
bSig = extractFloat32Frac(b);
/* Checking for invalid exception 0 * inf */
if ((aExp == 0xFF) && (aSig == 0)) {
if ((bExp | bSig) == 0) {
/* a is infinity and b is zero -> invalid operation exception */
float_raise( EXC_INVALID );
return propagateFloat32NaN(0x7FFFFFFF, c);
}
}
if ((bExp == 0xFF) && (bSig == 0)) {
if ((aExp | aSig) == 0) {
/* b is infinity and a is zero -> invalid operation exception */
float_raise( EXC_INVALID );
return propagateFloat32NaN(0x7FFFFFFF, c);
}
}
/* NaN propagation */
if (float32_is_nan(a) || float32_is_nan(b) || float32_is_nan(c))
return propagate3Float32NaN(a, b, c);
if (isSub)
c ^= 0x80000000;
cSign = extractFloat32Sign(c);
cExp = extractFloat32Exp(c);
cSig = extractFloat32Frac(c);
pSign = aSign ^ bSign;
/* Checking for infinities */
if (aExp == 0xFF) {
if (cExp == 0xFF) {
if (pSign != cSign) {
/* sum of infinities of different signs -> invalid operation */
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
}
return packFloat32(pSign ^ flipSign, 0xFF, 0);
}
if (bExp == 0xFF) {
if (cExp == 0xFF) {
if (pSign != cSign) {
/* sum of infinities of different signs -> invalid operation */
float_raise( EXC_INVALID );
return 0x7FFFFFFF;
}
}
return packFloat32(pSign ^ flipSign, 0xFF, 0);
}
if (cExp == 0xFF) {
return packFloat32(cSign ^ flipSign, 0xFF, 0);
}
/* Case a*b is zero */
if (((aExp | aSig) == 0) || ((bExp | bSig) == 0)) {
if ((cExp | cSig) == 0) { /* c is zero */
if (pSign == cSign)
return packFloat32(pSign ^ flipSign, 0, 0);
else
return packFloat32(float_rounding_mode == ROUND_DOWN, 0, 0);
}
/* return c, flip sign bit if necessary */
if (flipSign)
c ^= 0x80000000;
return c;
}
/* Normal computation */
if (aExp == 0)
normalizeFloat32Subnormal(aSig, &aExp, &aSig);
if (bExp == 0)
normalizeFloat32Subnormal(bSig, &bExp, &bSig);
pExp = aExp + bExp - 0x7F;
aSig = (aSig | 0x00800000) << 7;
bSig = (bSig | 0x00800000) << 7;
pSig64 = ((uint64_t) aSig) * bSig; /* binary pt btwn bits 60-59 */
/* Normalize pSig64 with bin pt btwn bits 61-60 */
if (pSig64 & 0x2000000000000000)
++pExp;
else
pSig64 <<= 1;
if (cExp == 0) {
if (cSig == 0) {
/* c is zero, returns the product */
--pExp;
shift64RightJamming(pSig64, 31, &pSig64);
zSig = pSig64;
return roundAndPackFloat32(pSign ^ flipSign, pExp, zSig);
}
else
normalizeFloat32Subnormal(cSig, &cExp, &cSig);
}
else
cSig |= 0x00800000;
cSig64 = ((uint64_t) cSig) << 38;/* binary pt btwn bits 61-60 */
expDiff = pExp - cExp;
if (0 < expDiff) {
/* product exp is bigger */
zExp = pExp;
zSign = pSign;
shift64RightJamming(cSig64, expDiff, &cSig64);
if (pSign == cSign)
zSig64 = pSig64 + cSig64;
else
zSig64 = pSig64 - cSig64;
}
else if (expDiff < 0) {
/* c exp is bigger */
zExp = cExp;
zSign = cSign;
shift64RightJamming(pSig64, -expDiff, &pSig64);
if (pSign == cSign)
zSig64 = cSig64 + pSig64;
else
zSig64 = cSig64 - pSig64;
}
else {
/* p exp and c exp are equal */
zExp = pExp;
zSign = pSign;
if (pSign == cSign)
zSig64 = pSig64 + cSig64;
else {
if (pSig64 > cSig64) {
zSig64 = pSig64 - cSig64;
}
else if (cSig64 > pSig64) {
zSign = cSign;
zSig64 = cSig64 - pSig64;
}
else {
/* return zero value */
return packFloat32(float_rounding_mode == ROUND_DOWN, 0, 0);
}
}
}
shiftCount = countLeadingZeros64(zSig64);
zSig64 <<= (shiftCount -1);
zExp -= (shiftCount - 1);
shift64RightJamming(zSig64, 32, &zSig64);
zSig = zSig64;
return roundAndPackFloat32(zSign ^ flipSign, zExp, zSig);
}
/*}}}*/
uint64_t SS_Fpu::float64_madd(uint64_t a, uint64_t b, uint64_t c, int isSub, int flipSign)/*{{{*/
{
/*
-------------------------------------------------------------------------------
Returns the result (a*b+c) of fused multiply-add operation on the
double-precision floating-point values `a', `b', and `c'. The operation is
performed according to the IEC/IEEE Standard for Binary Floating-Point
Arithmetic.
-------------------------------------------------------------------------------
*/
int aSign, bSign, cSign, pSign, zSign;
int16_t aExp, bExp, cExp, pExp, zExp, expDiff;
uint64_t aSig, bSig, cSig0, cSig1, pSig0, pSig1, zSig0, zSig1;
uint64_t pRes;
int8_t shiftCount;
aSign = extractFloat64Sign(a);
aExp = extractFloat64Exp(a);
aSig = extractFloat64Frac(a);
bSign = extractFloat64Sign(b);
bExp = extractFloat64Exp(b);
bSig = extractFloat64Frac(b);
/* Checking for invalid exception 0 * inf */
if ((aExp == 0x7FF) && (aSig == 0)) {
if ((bExp | bSig) == 0) {
/* a is infinity and b is zero -> invalid operation exception */
float_raise( EXC_INVALID );
return propagateFloat64NaN(0x7FFFFFFFFFFFFFFF, c);
}
}
if ((bExp == 0x7FF) && (bSig == 0)) {
if ((aExp | aSig) == 0) {
/* b is infinity and a is zero -> invalid operation exception */
float_raise( EXC_INVALID );
return propagateFloat64NaN(0x7FFFFFFFFFFFFFFF, c);
}
}
/* NaN propagation */
if (float64_is_nan(a) || float64_is_nan(b) || float64_is_nan(c))
return propagate3Float64NaN(a, b, c);
if (isSub)
c ^= 0x8000000000000000;
cSign = extractFloat64Sign(c);
cExp = extractFloat64Exp(c);
cSig0 = extractFloat64Frac(c);
pSign = aSign ^ bSign;
/* Checking for infinities */
if (aExp == 0x7FF) {
if (cExp == 0x7FF) {
if (pSign != cSign) {
/* sum of infinities of different signs -> invalid operation */
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
}
return packFloat64(pSign ^ flipSign, 0x7FF, 0);
}
if (bExp == 0x7FF) {
if (cExp == 0x7FF) {
if (pSign != cSign) {
/* sum of infinities of different signs -> invalid operation */
float_raise( EXC_INVALID );
return 0x7FFFFFFFFFFFFFFF;
}
}
return packFloat64(pSign ^ flipSign, 0x7FF, 0);
}
if (cExp == 0x7FF) {
return packFloat64(cSign ^ flipSign, 0x7FF, 0);
}
/* Case a*b is zero */
if (((aExp | aSig) == 0) || ((bExp | bSig) == 0)) {
if ((cExp | cSig0) == 0) { /* c is zero */
if (pSign == cSign)
return packFloat64(pSign ^ flipSign, 0, 0);
else
return packFloat64(float_rounding_mode == ROUND_DOWN, 0, 0);
}
/* return c, flip sign bit if necessary */
if (flipSign)
c ^= 0x8000000000000000;
return c;
}
/* Normal computation */
if (aExp == 0)
normalizeFloat64Subnormal(aSig, &aExp, &aSig);
if (bExp == 0)
normalizeFloat64Subnormal(bSig, &bExp, &bSig);
pExp = aExp + bExp - 0x3FF;
aSig = (aSig | 0x0010000000000000) << 10;
bSig = (bSig | 0x0010000000000000) << 10;
mul64To128(aSig, bSig, &pSig0, &pSig1); /* bin pt btwn bits 60-59 of pSig0 */
/* Normalize pSig with bin pt btwn bits 61-60 of pSig0 */
if (pSig0 & 0x2000000000000000)
++pExp;
else
shortShift128Left(pSig0, pSig1, 1, &pSig0, &pSig1);
if (cExp == 0) {
if (cSig0 == 0) {
/* c is zero, returns the product */
--pExp;
shortShift128Left(pSig0, pSig1, 1, &pSig0, &pSig1);
pSig0 |= (pSig1 != 0);
return roundAndPackFloat64(pSign ^ flipSign, pExp, pSig0);
}
else
normalizeFloat64Subnormal(cSig0, &cExp, &cSig0);
}
else
cSig0 |= 0x0010000000000000;
cSig0 <<= 9; /* bin pt btwn bits 61-60 */
cSig1 = 0;
expDiff = pExp - cExp;
if (0 < expDiff) {
/* product exp is bigger */
zExp = pExp;
zSign = pSign;
shift128RightJamming(cSig0, cSig1, expDiff, &cSig0, &cSig1);
if (pSign == cSign)
add128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
else
sub128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
}
else if (expDiff < 0) {
/* c exp is bigger */
zExp = cExp;
zSign = cSign;
shift128RightJamming(pSig0, pSig1, -expDiff, &pSig0, &pSig1);
if (pSign == cSign)
add128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
else
sub128(cSig0, cSig1, pSig0, pSig1, &zSig0, &zSig1);
}
else {
/* p exp and c exp are equal */
zExp = pExp;
zSign = pSign;
if (pSign == cSign)
add128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
else {
if (lt128(cSig0, cSig1, pSig0, pSig1)) {
sub128(pSig0, pSig1, cSig0, cSig1, &zSig0, &zSig1);
}
else if (lt128(pSig0, pSig1, cSig0, cSig1)) {
zSign = cSign;
sub128(cSig0, cSig1, pSig0, pSig1, &zSig0, &zSig1);
}
else {
/* return zero value */
return packFloat64(float_rounding_mode == ROUND_DOWN, 0, 0);
}
}
}
shiftCount = countLeadingZeros64(zSig0);
if (shiftCount != 64) {
shortShift128Left(zSig0, zSig1, shiftCount-1, &zSig0, &zSig1);
zExp -= (shiftCount-1);
zSig0 |= (zSig1 != 0);
}
else {
shiftCount = countLeadingZeros64(zSig1);
if (shiftCount == 0) {
zSig1 >>= 1;
zExp -= 63;
}
else {
zSig1 <<= (shiftCount-1);
zExp -= (63 + shiftCount);
}
zSig0 = zSig1;
}
return roundAndPackFloat64(zSign ^ flipSign, zExp, zSig0);
}
/*}}}*/
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