Initial commit of OpenSPARC T2 architecture model.

[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / cpu / src / SS_Model.h

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: SS_Model.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/

#ifndef __SS_Model_h__
#define __SS_Model_h__

#include "SS_Node.h"
#include "SS_Cpu.h"
#include "SS_Strand.h"
#include "SS_MemErrDetector.h"

class SS_Model : public SS_Node
{
 public:
   // SS_Model() takes as version number argument. The version is
   // used for versioning snapshots. If the snaphot files becomes
   // different then we should use a new version number (+1)  

   // potential error/exception posted by sub-component like I/O space. Use
   // each bit to represent an error type.
   enum ErrorBit
   {
     IO_RSVD_READ = 0x1 << 0
   };
   enum
   {
     MAX_ERROR_SIZE=1024
   };

   friend ErrorBit operator|( ErrorBit a, ErrorBit b ) { return ErrorBit(int(a)|int(b)); }
   friend ErrorBit operator&( ErrorBit a, ErrorBit b ) { return ErrorBit(int(a)&int(b)); }
   friend ErrorBit operator~( ErrorBit a ) { return ErrorBit(~int(a)); }

   SS_Model();
   
   void hard_reset();
   // intp is used to indicate whether a WMR trap should be triggered (at
   // strand level). A warm_reset() with intp=false will reset registers
   // to warm_reset state, but will not invoke the WMR trap routine.
   void warm_reset(bool intp=true);
   void xtrn_reset();

   enum { MAX_CPU_COUNT = 64 };        // Current limit, just ficticious

   // create_cpu() create a given number of cpus and adds them to
   // the cpus that have already been created.

   virtual void create_cpu( uint_t no_cpu ) = 0;
   virtual void create_cpu_dynamic( uint_t no_cpu, int no_core=1 ) { create_cpu(no_cpu); }

   // cpu_cnt() returns the number of cpu's available in the model

   uint_t  cpu_cnt()                   { return cpu_count; }

   // cpu[] is the area of created cpu instances
   
   SS_Cpu* cpu[MAX_CPU_COUNT];

   // snapshot() is called to take a snapshot of the whole model 
  
   virtual void snapshot( SS_SnapShot& );

   // flush() broadcasts the flush to all the strands in the cpus.
   // SS_Strand is the strand that issues the flush. When this returns
   // false it means the flush is not broadcast: 1 strand running case.
   
   bool flush( SS_Strand* s, SS_Paddr pa, uint_t size );
   
   // flush() flush pa frin the decode cache of all strands. This
   // flush is very usefull for frontends.

   void flush( SS_Paddr pa );

   // ras_flush() is called to flush RAS related cache models if a
   // flush or flushw instrucion is executed
   void ras_flush(  SS_Strand* requesting_strand, SS_Paddr pa, uint64_t size, SS_MemErrDetector::CacheType type );

   // ras enable from frontend
   virtual void ras_enable(char* cmd);

   // place holder for posting errors
   ErrorBit get_error( int strand_id )           { assert(strand_id<MAX_ERROR_SIZE); return errors[strand_id]; }
   void set_error( int strand_id, ErrorBit err ) { assert(strand_id<MAX_ERROR_SIZE); errors[strand_id] = err; }
   void clr_error( int strand_id, ErrorBit err ) { assert(strand_id<MAX_ERROR_SIZE); errors[strand_id] = errors[strand_id] & ~err; }

 protected:
   uint_t   cpu_count;         // Number of cpu objects set in cpu array

   ErrorBit errors[MAX_ERROR_SIZE];
};

#endif