sam-t2/sam/cpus/vonk/ss/lib/cpu/src/SS_Registers.cc

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: SS_Registers.cc
// Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================

#include "SS_Registers.h"
#include "SS_State.h"

const char* SS_Registers::irf_name[IRF_SIZE] =
{
  "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
  "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
  "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
  "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7"
};

const char* SS_Registers::drf_name[DRF_SIZE] =
{
  "d0",  "d2",  "d4",  "d6",  "d8",  "d10", "d12", "d14",
  "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30",
  "d32", "d34", "d36", "d38", "d40", "d42", "d44", "d46",
  "d48", "d50", "d52", "d54", "d56", "d58", "d60", "d62"
};

const char* SS_Registers::asr_name[ASR_SIZE] =
{
  "asr0",  "asr1",  "asr2",  "asr3",  "asr4",  "asr5",  "asr6",  "asr7",
  "asr8",  "asr9",  "asr10", "asr11", "asr12", "asr13", "asr14", "asr15",
  "asr16", "asr17", "asr18", "asr19", "asr20", "asr21", "asr22", "asr23",
  "asr24", "asr25", "asr26", "asr27", "asr28", "asr29", "asr30", "asr31"
};

const char* SS_Registers::pr_name[PR_SIZE] =
{
  "pr0",  "pr1",  "pr2",  "pr3",  "pr4",  "pr5",  "pr6",  "pr7",
  "pr8",  "pr9",  "pr10", "pr11", "pr12", "pr13", "pr14", "pr15",
  "pr16", "pr17", "pr18", "pr19", "pr20", "pr21", "pr22", "pr23",
  "pr24", "pr25", "pr26", "pr27", "pr28", "pr29", "pr30", "pr31"
};

const char* SS_Registers::hpr_name[HPR_SIZE] =
{
  "hpr0",  "hpr1",  "hpr2",  "hpr3",  "hpr4",  "hpr5",  "hpr6",  "hpr7",
  "hpr8",  "hpr9",  "hpr10", "hpr11", "hpr12", "hpr13", "hpr14", "hpr15",
  "hpr16", "hpr17", "hpr18", "hpr19", "hpr20", "hpr21", "hpr22", "hpr23",
  "hpr24", "hpr25", "hpr26", "hpr27", "hpr28", "hpr29", "hpr30", "hpr31"
};

const char* SS_Registers::frf_name[FRF_SIZE] =
{
  "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
  "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
  "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
  "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
  "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
  "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
  "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
  "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63"
};

const char* SS_Registers::sim_name[SIM_SIZE] =
{
  "sim0",  "sim1",  "sim2",  "sim3",  "sim4",  "sim5",  "sim6",  "sim7",
  "sim8",  "sim9",  "sim10", "sim11", "sim12", "sim13", "sim14", "sim15",
  "sim16", "sim17", "sim18", "sim19", "sim20", "sim21", "sim22", "sim23",
  "sim24", "sim25", "sim26", "sim27", "sim28", "sim29", "sim30", "sim31"
};


const char* SS_Registers::get_name( SS_Registers::Index index )
{
  if (SS_Registers::is_irf(index))
    return SS_Registers::irf_name[index - SS_Registers::IRF_OFS];
  else if (SS_Registers::is_drf(index))
    return SS_Registers::drf_name[index - SS_Registers::DRF_OFS];
  else if (SS_Registers::is_asr(index))
    return SS_Registers::asr_name[index - SS_Registers::ASR_OFS];
  else if (SS_Registers::is_pr(index))
    return SS_Registers::pr_name[index - SS_Registers::PR_OFS];
  else if (SS_Registers::is_hpr(index))
    return SS_Registers::hpr_name[index - SS_Registers::HPR_OFS];
  else if (SS_Registers::is_frf(index))
    return SS_Registers::frf_name[index - SS_Registers::FRF_OFS];
  else if (SS_Registers::is_sim(index))
    return SS_Registers::sim_name[index - SS_Registers::SIM_OFS];
  else
    return 0;
}