Initial commit of OpenSPARC T2 architecture model.
[OpenSPARC-T2-SAM] / sam-t2 / sam / cpus / vonk / ss / lib / ras / src / SS_CKMemory.h
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: SS_CKMemory.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
#ifndef __SS_CKMemory_h__
#define __SS_CKMemory_h__
#include <iostream.h>
#include <map>
#include <SS_Types.h>
#include "BL_Memory.h"
#include "SS_Memory.h"
#include "MemoryTransaction.h"
#include "BL_CKEcc.h"
#include "BL_CKSyndrome.h"
using namespace::std;
class SS_Strand;
class SS_CKMemory:public BL_Memory/*{{{*/
{
public:
SS_CKMemory(SS_Memory *mem);
~SS_CKMemory();
// Supported User Interface Operations
void poke8( uint64_t addr, uint8_t data ){ss_mem->poke8(addr,data);}
void poke16( uint64_t addr, uint16_t data ){ss_mem->poke16(addr,data);}
void poke32( uint64_t addr, uint32_t data ){ss_mem->poke32(addr,data);}
void poke64( uint64_t addr, uint64_t data ){ss_mem->poke64(addr,data);}
uint8_t peek8u( uint64_t addr ){return ss_mem->peek8u(addr);}
int8_t peek8s( uint64_t addr ){return ss_mem->peek8s(addr);}
uint16_t peek16u( uint64_t addr ){return ss_mem->peek16u(addr);}
int16_t peek16s( uint64_t addr ){return ss_mem->peek16s(addr);}
uint32_t peek32u( uint64_t addr ){return ss_mem->peek32u(addr);}
int32_t peek32s( uint64_t addr ){return ss_mem->peek32s(addr);}
uint64_t peek64( uint64_t addr ){return ss_mem->peek64(addr);}
// Supported Fetch Operation (instruction fetch)
uint32_t fetch32 ( uint64_t addr );
void fetch256( uint64_t addr, uint64_t data[4] );
void fetch512( uint64_t addr, uint64_t data[8] );
// Supported Store Operations. st8(), st16(), st32() and st64() are gueranteed to be atomic.
// st128() and st512() are atomic per 64bit quantity.
void st8 ( uint64_t addr, uint8_t data );
void st16 ( uint64_t addr, uint16_t data );
void st32 ( uint64_t addr, uint32_t data );
void st64 ( uint64_t addr, uint64_t data );
void st128( uint64_t addr, uint64_t data[2] );
void st512( uint64_t addr, uint64_t data[8] );
// Supported Load Operations. ld8[su]() to ld64() are quaranteed to be atomic. ld128() and
// above are atomic at the 64 bit granularity.
uint8_t ld8u ( uint64_t addr );
int8_t ld8s ( uint64_t addr );
uint16_t ld16u( uint64_t addr );
int16_t ld16s( uint64_t addr );
uint32_t ld32u( uint64_t addr );
int32_t ld32s( uint64_t addr );
uint64_t ld64 ( uint64_t addr );
void ld128( uint64_t addr, uint64_t data[2] );
void ld256( uint64_t addr, uint64_t data[4] );
void ld512( uint64_t addr, uint64_t data[8] );
// st64partial() performs 8 byte partial store. The bytes to store are specified by mask. A 1 in bit N of
// mask denotes that byte (data >> (8*N)) & 0xff should be written to memory
void st64partial( uint64_t addr, uint64_t data, uint64_t mask );
// ld128atomic() (aka load twin double, load quad atomic) atomically loads two
// 64bit values from memory at addr into rd. rd[0] is the value at addr, rd[1]
// is the value at addr + 8. Note ld128 does() not guarantee atomicity.
void ld128atomic( uint64_t addr, uint64_t data[2] );
// ldstub() return a byte from memory at addr, and set the byte at addr
// to 0xff. The ldstub() operation is atomic.
uint8_t ldstub( uint64_t addr );
// swap() stores the 32bit value rd with the 32bit value at addr.
// The old 32bit value at addr is returned. The operation is atomic.
uint32_t swap( uint64_t addr, uint32_t rd );
// casx() compares the 64bit value rs2 with the 64bit value at addr.
// If the two values are equal, the value rd is stored in the
// 64bit value at addr. In both cases the old 64bit value at addr is
// returned, that is the value at addr before the storei happened.
// The casx() operation is atomic.
uint64_t casx( uint64_t addr, uint64_t rd, uint64_t rs2 );
// cas() is as casx, but for 32bit.
uint32_t cas( uint64_t addr, uint32_t rd, uint32_t rs2 );
//----------------------------------------------------------------------------
// CK additional interface
//----------------------------------------------------------------------------
// dram_update_ecc() updates the ecc value associated with paddress.
void dram_update_ecc(uint64_t paddr,uint64_t newDramEcc)
{
dram_ecc_map[paddr] = newDramEcc;
}
// Verifies if a ecc value exists for a given physical address
bool ecc_exists(uint64_t key) const
{
return dram_ecc_map.find(key) != dram_ecc_map.end();
}
// Returns the ecc value for a given physical address
uint64_t fetch_ecc(uint64_t key) const
{
std::map<uint64_t,uint64_t>::const_iterator i = dram_ecc_map.find(key);
if (i == dram_ecc_map.end())
{
fprintf(stderr, "SS_CKMemory::fetchecc(): no ecc at 0x%x", key);
exit(-1);
}
return i->second;
}
// Calculates ecc for 128 bits of data give a higher order physical
// address
uint64_t calculate_dram_ecc(uint64_t paddr)
{
return BL_CKEccFile::generateChipkillECC(read_raw_CK_line(paddr));
}
// DRAM Error Detection and Handling
// Detect ecc error
// If the paddr has an entry in the ecc Map
bool detect_dram_error(uint64_t paddr,BL_CKSyndrome &ck_syndrome)
{
if(ecc_exists(paddr))
{
BL_CKSyndrome syndrome(read_raw_CK_line(paddr), fetch_ecc(paddr));
ck_syndrome = syndrome;
return true;
}
return false;
}
// Reads one Chip-Kill line from memory without correction
BL_CKEccFile::ChipKillLine read_raw_CK_line(uint64_t paddress) const
{
BL_CKEccFile::ChipKillLine line;
line.msdw = ss_mem->peek64(paddress);
line.lsdw = ss_mem->peek64((paddress+8));
return line;
}
// Correct Chip-Kill data errors in a memory transaction
// data payload
bool read_dram_error_corrected(MemoryTransaction &memXact);
static const uint64_t DRAM_LINE_LENGTH = 16;
// Chip-Kill ecc used to indicate poisoned data (NotData)
static const uint64_t DRAM_NOT_DATA = 0x8221;
private:
MemoryTransaction mem_xact;
uint64_t ras_ld_buf( uint64_t addr, uint_t size );
void ras_ld( uint64_t addr, uint_t size, uint64_t* data );
SS_Memory *ss_mem;
std::map<uint64_t,uint64_t> dram_ecc_map;
// Return "size" bytes of data located at specified physical
// address for Chip-kill
uint64_t read_corrected_dram_data(uint64_t paddress, uint8_t size);
// Return "size" (<= 4) bytes of data located at specified physical
// address for Chip-kill
uint64_t read_short_corrected_dram_data(uint64_t paddress, uint8_t size);
// set to artificially inject Chip-Kill errors. Note that this
// can't be used with "real" CK error injection because it
// could result in uncorrectable double nibble errors.
bool debug_CK;
};
/*}}}*/
#endif /*__SS_CKMemory_h__*/