sam-t2/sam/devices/n2_piu/include/defs.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: defs.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/

/*
 * this file includes complete/dummy definitions of structures used by legion.
 * the idea is to implement only those variables that are actually
 * accessed by piu, initialized with either arbitrary values or
 * those that make sense from SAM's perspective.
 */

/////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////

        /*
         * Generic physical and virtual address types.
         *
         * Core design is 64 bit addressing, however some
         * chips & cores may use 32bits in which case the
         * bit widths should be explicit, but for the general
         * infrastructure types use these two.
         */

typedef uint64_t    tpaddr_t;
typedef uint64_t    tvaddr_t;

////////////////////////////////////////////////////////////////

/*
 * below lifted from legions' src/include/simcore.h
 */

        /*
         * Op fields for memory access operations
         *
         * Note: These field values are used by the core for embedding
         * in decoded instructions. However, processor modules may also
         * choose additional specific encodings that are restricted to
         * those modules only and are defined elsewhere.
         *
         * Care should be taken when modifying these codes as not to
         * tread on value defined elsewhere (values >= 0x100 && < 0xfff0).
         *
         * Processor specific modules should use the value
         * MA_Non_Gen_Base as the base for their specific definitions.
         *
         * The generic core values reside in no more than 8 bits
         * and are used to define basic load, store and cas operations.
         */

enum MACCESS {
    MA_Size_Mask        = 0xf,

    MA_Size8    = 0x0,
    MA_Size16   = 0x1,
    MA_Size32   = 0x2,
    MA_Size64   = 0x3,
    MA_Size128  = 0x4,
    MA_Size256  = 0x5,
    MA_Size512  = 0x6,

    MA_Op_MaskGeneric = 0xf0,
    MA_Op_Mask  = 0xfff0,

    MA_Ld               = 0x00,
    MA_LdSigned = 0x10,
    MA_LdDouble = 0x20,         /* SPARC only ? */
    MA_LdFloat  = 0x30,
    MA_St               = 0x40,
    MA_StFloat  = 0x50,
    MA_CAS              = 0x60,
    MA_StDouble = 0x70,         /* SPARC only ? */
    MA_LdSt             = 0x80,
    MA_Swap             = 0x90,

    MA_Non_Gen_Base = 0x100,    /* First non generic useable value */
    MA_Non_Gen_Skip = 0x10,             /* skip value for non-generic codes */

    MA_ldu8             = MA_Size8 | MA_Ld,
    MA_ldu16    = MA_Size16 | MA_Ld,
    MA_ldu32    = MA_Size32 | MA_Ld,
    MA_ldu64    = MA_Size64 | MA_Ld,

    MA_lddu64   = MA_Size64 | MA_LdDouble,      /* loads 64 bit value 64 bit aligned */
    MA_stdu64   = MA_Size64 | MA_StDouble,

    MA_lddu128  = MA_Size128 | MA_LdDouble,     /* loads 2x64 bit
                                                   values atomically
                                                   128 bit aligned */

    MA_lds8             = MA_Size8 | MA_LdSigned,
    MA_lds16    = MA_Size16 | MA_LdSigned,
    MA_lds32    = MA_Size32 | MA_LdSigned,
    MA_lds64    = MA_Size64 | MA_LdSigned,

    MA_st8              = MA_Size8 | MA_St,
    MA_st16             = MA_Size16 | MA_St,
    MA_st32             = MA_Size32 | MA_St,
    MA_st64             = MA_Size64 | MA_St,

    MA_ldfp8        = MA_Size8 | MA_LdFloat,
    MA_ldfp16       = MA_Size16 | MA_LdFloat,
    MA_ldfp32   = MA_Size32 | MA_LdFloat,
    MA_ldfp64   = MA_Size64 | MA_LdFloat,
    MA_ldfp128  = MA_Size128 | MA_LdFloat,

    MA_stfp8        = MA_Size8 | MA_StFloat,
    MA_stfp16       = MA_Size16 | MA_StFloat,
    MA_stfp32   = MA_Size32 | MA_StFloat,
    MA_stfp64   = MA_Size64 | MA_StFloat,
    MA_stfp128  = MA_Size128 | MA_StFloat,

    MA_cas32    = MA_Size32 | MA_CAS,
    MA_cas64    = MA_Size64 | MA_CAS,

        /* Are these generic ? FIXME */
    MA_ldstub   = MA_Size8 | MA_LdSt,
    MA_swap             = MA_Size32 | MA_Swap
};

typedef enum MACCESS maccess_t;

/*
 * These macros must be passed an op masked with MA_Op_Mask.
 * It is intended that they be included as part of a architecture
 * specific form, hence the underscore prefix.
 */
#define _IS_MA_LOAD(_op) \
        (MA_Ld == (_op) || MA_LdSigned == (_op) || \
        MA_LdDouble == (_op) || MA_LdFloat == (_op) || \
        MA_LdSt == (_op) || MA_CAS == (_op) || MA_Swap == (_op))
#define _IS_MA_STORE(_op) \
        (MA_St == (_op) || MA_StDouble == (_op) || \
        MA_StFloat == (_op) || \
        MA_LdSt == (_op) || MA_CAS == (_op) || MA_Swap == (_op))
#define _IS_MA_ATOMIC(_op) \
        (MA_LdSt == (_op) || MA_CAS == (_op) || MA_Swap == (_op))


///////////////////////////////////////////////////////////////
//
    /* definitions from src/parser/include/config.h */


typedef enum {
        PIU_REGION_CFGIO = 0,
        PIU_REGION_MEM32 = 1,
        PIU_REGION_MEM64 = 2,
        PIU_REGION_8MB = 3,
        PIU_REGION_UNMAPPED
} piu_region_t;

typedef enum {
        DA_Load = 0x1,
        DA_Store = 0x2,
        DA_Atomic = 0x3,        /* bit fields - atomic considered load | store */
        DA_Instn = 0x4,
        DA_Other = 0x8
} dev_access_t;


///////////////////////////////////////////////////////////////
// other hash defines.

#define MASK64( _high, _low )   ( ( (uint64_t)((~(uint64_t)0)>>(63-(_high))) ) & ( (uint64_t)( (~(uint64_t)0)<<(_low)) ) )
#define GETMASK64(x, hi, lo) (((uint64_t)(x) & MASK64((hi), (lo)))>>(lo))

#define PHYS_ADDR_NCU           0x8000000000
#define PHYS_ADDR_CCU           0x8300000000
#define PHYS_ADDR_MCU           0x8400000000
#define PHYS_ADDR_HWDBG         0x8600000000
#define PHYS_ADDR_DMU           0x8800000000
#define PHYS_ADDR_RCU           0x8900000000
#define PHYS_ADDR_L2C           0xA000000000
#define PHYS_ADDR_PIU_LB        0xC000000000
#define PHYS_ADDR_PIU_UB        0xCF00000000
#define PHYS_ADDR_SSI           0xFF00000000
#define PHYS_ADDR_JTAG          0x9000000000

#define PHYS_ADDR_MASK          0xFF00000000
/*
 * DMU 8MB configu region address map
 */
#define DMU_8MB_GAP_MASK        MASK64(31,23)
#define DMU_8MB_OFFSET_MASK     MASK64(22,0)


/*
 * PCIE Mondo interrupt
 */
typedef struct PCIE_MONDO {
        int thread_id;
        uint64_t data[8];
} pcie_mondo_t;


typedef enum {
        ES_IDLE,
        ES_RESUME,
        ES_RESET,
        ES_SSI,
        ES_JBUS,
        ES_SPOR,
        ES_XIR,
        ES_NIU,
        ES_PCIE
} ext_sig_t;


typedef enum {
        PCIE_IS32 = 0,
        PCIE_IS64 = 1
} dev_mode_t;

typedef enum {
        _PCIE_CFG   = 0,
        _PCIE_IO    = 1,
        _PCIE_MEM32 = 2,
        _PCIE_MEM64 = 3
} pcie_space_t;

struct config_dev_t{
    uint64_t dummy;
};

struct config_proc_t{
    uint64_t dummy;
};