sam-t2/sam/devices/schizo/include/schizo_impl.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: schizo_impl.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/*
 * Copyright (C) 1996, 2001 Sun Microsystems, Inc.
 * All rights reserved.
 */
#ifndef _SCHIZO_IMPL_H
#define _SCHIZO_IMPL_H


#include <synch.h>

#include "schizo_regs.h"
#include "safari_interface.h"

#include "schizo_stc.h"
#include "schizo_mdu.h"
#include "schizo_iommu.h"
#include "decl_macros.h"

extern int debug_ctr;

#define BUS(n)          ((n) << 16)

#define MAX_INTR_DEVICES    64
#define MAX_SLAVES          64

#define PCI_A_IDX  (0)
#define PCI_B_IDX  (1)

#define PCI_BUS_NUM(a)          (((a) & 0xf0000) >> 16)
#define PCI_DEVICE(a)           (((a) & 0xf800) >> 11)
#define PCI_FUNCTION(a)         (((a) & 0x0700) >> 8)

#define PCI_CONFIG_OFFSET(a)    ((a) & 0xff)


typedef enum { memory, io, config } space_t;
typedef enum { A, B } pbm_t;
typedef enum Address_cycle { sac, dac } Address_cycle;
typedef enum Xlate_mode { bypass, passthro, transltn } Xlate_mode;

#define Mem_Timing1_CTL     0x00
#define Mem_Timing2_CTL     0x08
#define Mem_Addr_Decode_0   0x10
#define Mem_Addr_Decode_1   0x18
#define Mem_Addr_Decode_2   0x20
#define Mem_Addr_Decode_3   0x28
#define Mem_Addr_CTL        0x30
#define Mem_Timing3_CTL     0x38
#define Mem_Timing4_CTL     0x40
#define FLUSH_FLAG              0x00000001

typedef struct Tlb_entry {
        union u_tlb_tag tag;
        union u_iotlb_data data;
} Tlb_entry_t;

typedef struct schizo_struct {
        int mid;                /* module id */

        Tlb_entry_t *a_entries;
        Tlb_entry_t *a_current_entry;
        Tlb_entry_t *b_entries;
        Tlb_entry_t *b_current_entry;

        mutex_t lock;           /* for multiple device interrupts */
        mutex_t counter_lock;   /* for multiple interrupts per device */
        mutex_t iommu_a_lock;   /* for multiple iommu/tlb updates */
        mutex_t iommu_b_lock;   /* for multiple iommu/tlb updates */

        uint32_t  dev_type;    //  Interrupt tracing
        uint32_t  dev_id;      //  stuff

        /*Safari interface Registers */
        /* Address Match Registers */

          /**** DUMP starts from here *****/

          FLDDECL(union u_safari_dev_id, safari_dev_id,, dump,);
          FLDDECL(union u_Addr_Match_Reg, UPA0Base_addr_match,, dump,);
          FLDDECL(union u_Addr_Match_Reg, UPA1Base_addr_match,, dump,);
          FLDDECL(union u_NewLinkBase_addr_match, NewLinkBase_addr_match,,
                  dump,);
          FLDDECL(union u_NewLinkAltBase_addr_match,
                  NewLinkAltBase_addr_match,, dump,);
          FLDDECL(union u_Addr_Match_Reg, PCI_A_MemBase_addr_match,, dump,);
          FLDDECL(union u_PCI_A_ConfigBase_addr_match,
                  PCI_A_ConfigBase_addr_match,, dump,);
          FLDDECL(union u_Addr_Match_Reg, PCI_B_MemBase_addr_match,, dump,);
          FLDDECL(union u_PCI_B_ConfigBase_addr_match,
                  PCI_B_ConfigBase_addr_match,, dump,);

        /*Address Mask Registers */
        union u_Addr_Mask_Reg UPA0Base_addr_mask;
        union u_Addr_Mask_Reg UPA1Base_addr_mask;
          FLDDECL(union u_NewLinkBase_addr_mask, NewLinkBase_addr_mask,,
                  dump,);
          FLDDECL(union u_NewLinkAltBase_addr_mask, NewLinkAltBase_addr_mask,,
                  dump,);
          FLDDECL(union u_Addr_Mask_Reg, PCI_A_MemBase_addr_mask,, dump,);
          FLDDECL(union u_PCI_A_ConfigBase_addr_mask,
                  PCI_A_ConfigBase_addr_mask,, dump,);
          FLDDECL(union u_Addr_Mask_Reg, PCI_B_MemBase_addr_mask,, dump,);
          FLDDECL(union u_PCI_B_ConfigBase_addr_mask,
                  PCI_B_ConfigBase_addr_mask,, dump,);


          FLDDECL(union u_schizo_cntrl, schizo_cntrl,, dump,);  /* may change to schizo */
          FLDDECL(union u_upa_port_id, upa_port_id,, dump,);
          FLDDECL(union u_upa_config, upa_config,, dump,);

          FLDDECL(union u_ecc_cntrl, ecc_cntrl,, dump,);
          FLDDECL(union u_ue_afsr, ue_afsr,, dump,);
          FLDDECL(union u_ue_afar, ue_afar,, dump,);
          FLDDECL(union u_ce_afsr, ce_afsr,, dump,);
          FLDDECL(union u_ce_afar, ce_afar,, dump,);

          FLDDECL(union u_ffb_config_register, ffb_config_reg,[2], dump,);

          FLDDECL(union u_pci_bus_cntrl, pci_bus_a_cntrl,, dump,);
          FLDDECL(union u_pci_bus_afsr, pci_bus_a_afsr,, dump,);
          FLDDECL(union u_pci_bus_afar, pci_bus_a_afar,, dump,);
          FLDDECL(union u_pci_bus_cntrl, pci_bus_b_cntrl,, dump,);
          FLDDECL(union u_pci_bus_afsr, pci_bus_b_afsr,, dump,);
          FLDDECL(union u_pci_bus_afar, pci_bus_b_afar,, dump,);
          FLDDECL(union u_perf_counter, perf_counter,, dump,);
          FLDDECL(union u_perf_monitor, perf_monitor,, dump,);

        /* stc regs */

          FLDDECL(union u_stc_cntrl, stc_a_cntrl,, dump,);
          FLDDECL(union u_stc_cntrl, stc_b_cntrl,, dump,);
          FLDDECL(union u_stc_flush, stc_a_flush,, dump,);
          FLDDECL(union u_stc_flush, stc_b_flush,, dump,);
          FLDDECL(union u_stc_flsync, stc_a_flsync,, dump,);
          FLDDECL(union u_stc_flsync, stc_b_flsync,, dump,);

        /* FIXME! how to deal with this in genMemberUtils? */
          FLDDECL(union u_stc_data_diag, stc_data_diag_a,
                  [NUM_STC_ENTRIES][LWORDS_PER_ENTRY], dump,);
          FLDDECL(union u_stc_ptag_diag, stc_ptag_diag_a,[NUM_STC_ENTRIES],
                  dump,);
          FLDDECL(union u_stc_ltag_diag, stc_ltag_diag_a,[NUM_STC_ENTRIES],
                  dump,);
          FLDDECL(union u_stc_cntx_mtch_diag, stc_cntx_mtch_diag_a,, dump,);
        /* FIXME! how to deal with this in genMemberUtils? */
          FLDDECL(union u_stc_error_diag, stc_error_diag_a,
                  [NUM_STC_ENTRIES][LWORDS_PER_ENTRY], dump,);
        /* FIXME! how to deal with this in genMemberUtils? */
          FLDDECL(union u_stc_data_diag, stc_data_diag_b,
                  [NUM_STC_ENTRIES][LWORDS_PER_ENTRY], dump,);
          FLDDECL(union u_stc_ptag_diag, stc_ptag_diag_b,[NUM_STC_ENTRIES],
                  dump,);
          FLDDECL(union u_stc_ltag_diag, stc_ltag_diag_b,[NUM_STC_ENTRIES],
                  dump,);
          FLDDECL(union u_stc_cntx_mtch_diag, stc_cntx_mtch_diag_b,, dump,);
        /* FIXME! how to deal with this in genMemberUtils? */
          FLDDECL(union u_stc_error_diag, stc_error_diag_b,
                  [NUM_STC_ENTRIES][LWORDS_PER_ENTRY], dump,);

        /* IOMMU A */
          FLDDECL(int, a_num_entries,, dump,);
          FLDDECL(union u_iommu_cntrl_reg, a_iommu_cntrl,, dump,);
          FLDDECL(union u_flush_page_reg, a_flush_page,, dump,);
          FLDDECL(union u_flush_context_reg, a_flush_context,, dump,);
          FLDDECL(union u_imtbr, a_imtbr,, dump,);
          FLDDECL(int, a_lru_entry_num,, dump,);
          FLDDECL(int, a_shift_reg,[16], dump,);
          FLDDECL(union u_pcibus_va_diag, a_pcibus_va_diag,, dump,);
          FLDDECL(union u_tag_cmpr_diag, a_tag_cmpr_diag,, dump,);
          FLDDECL(union u_lru_q_diag, a_lru_q_diag,[16], dump,);

        /* IOMMU B */
          FLDDECL(int, b_num_entries,, dump,);
          FLDDECL(union u_iommu_cntrl_reg, b_iommu_cntrl,, dump,);
          FLDDECL(union u_flush_page_reg, b_flush_page,, dump,);
          FLDDECL(union u_flush_context_reg, b_flush_context,, dump,);
          FLDDECL(union u_imtbr, b_imtbr,, dump,);
          FLDDECL(int, b_lru_entry_num,, dump,);
          FLDDECL(int, b_shift_reg,[16], dump,);
          FLDDECL(union u_pcibus_va_diag, b_pcibus_va_diag,, dump,);
          FLDDECL(union u_tag_cmpr_diag, b_tag_cmpr_diag,, dump,);
          FLDDECL(union u_lru_q_diag, b_lru_q_diag,[16], dump,);


        /* Mondo Stuff */
          FLDDECL(bool_t, pending_intr,, dump,);
          FLDDECL(union u_int_mapping, intr_map_reg,[64], dump,);
          FLDDECL(union u_clear_int, clr_int_reg,[64], dump,);
          FLDDECL(int, pending_intr_counter,[64], dump,);

          FLDDECL (union u_int_mapping, upa_slot0_intr_map_reg,[2], dump,);
          FLDDECL (union u_int_mapping, upa_slot1_intr_map_reg,[2], dump,);


          FLDDECL(union u_int_retry_timer, retry_timer,, dump,);

  // FIXME:  There should be TWO obio_isr and TWO pci_isr because of
  // PCI A & B

          FLDDECL(union u_obio_isr, obio_isr,, dump,);
          FLDDECL(union u_pci_isr, pci_isr,, dump,);

        FLDDECL(union u_pci_bus_diag, pci_bus_a_diag,, dump,);
        FLDDECL(union u_pci_bus_diag, pci_bus_b_diag,, dump,);

          FLDDECL(uint64_t, SafariBase,, dump,);
          FLDDECL(uint64_t, FCode,, dump,);
          FLDDECL(uint64_t, SafariCSRBase,, dump,);
          FLDDECL(uint64_t, NewLinkCSRBase,, dump,);
          FLDDECL(uint64_t, SafariErrorBase,, dump,);
          FLDDECL(uint64_t, PCI_A_CSRBase,, dump,);
          FLDDECL(uint64_t, PCI_A_IOBase,, dump,);
          FLDDECL(uint64_t, PCI_B_CSRBase,, dump,);
          FLDDECL(uint64_t, PCI_B_IOBase,, dump,);

          FLDDECL(uint64_t, PBM_B_CONFIG_PADDR,, dump,);
          FLDDECL(uint64_t, PBM_B_IO_PADDR,, dump,);
          FLDDECL(uint64_t, PBM_A_CONFIG_PADDR,, dump,);
          FLDDECL(uint64_t, PBM_A_IO_PADDR,, dump,);
          FLDDECL(uint64_t, PBM_A_MEM_PADDR,, dump,);
          FLDDECL(uint64_t, PBM_B_MEM_PADDR,, dump,);
} schizo_structT;

/////////////////////////////////////////////////////////////////
//   SCHIZO extensions (IO ld/st extension implementation
/////////////////////////////////////////////////////////////////

int
schizo_ext_process (uint32_t cpu_id, uint64_t paddr, bool_t  wr, uint32_t  size, uint64_t*   buf);


typedef uint8_t (*schizo_ld_ext_handler_t) (void *cd, struct BlzMemop *);
typedef uint8_t (*schizo_st_ext_handler_t) (void *cd, struct BlzMemop *);

typedef int (*schizo_ld_mmi_handler_t) (void *cd, uint64_t paddr, uint64_t *buf, int size, void *cpu);
typedef int (*schizo_st_mmi_handler_t) (void *cd, uint64_t paddr, uint64_t *buf, int size, void *cpu);


typedef struct schizo_ext
{
  uint64_t start_addr,
           end_addr,
           range;

  schizo_ld_ext_handler_t schizo_ld_handler;
  schizo_st_ext_handler_t schizo_st_handler;
  schizo_ld_mmi_handler_t schizo_ld_mmi_handler;
  schizo_st_mmi_handler_t schizo_st_mmi_handler;

  // TODO : interrupts ??

  struct schizo_ext *next;
} schizo_ext_t;


#define NI_ROM_SIZE  0x40000          // ???
#define NI_ROM_ADDR  0xfff0000000LLU  // ???
#define NI_CONS_ADDR 0xEF00000000LLU
#define NI_CONS_SIZE 0x2000LLU

#ifdef NIAGARA

typedef struct ni_rom
{

  uint64_t start_addr;
  uint64_t end_addr;
  uint64_t size;
  uint8_t  *ptr_rom;

} ni_rom_t;

void init_schizo_console (uint64_t ba, uint64_t ea);

#endif

void
schizo_ext_init (uint64_t addr, uint64_t size);

bool_t
schizo_rom_load  (uint32_t cpu_id, uint64_t  paddr, uint32_t size, uint64_t *buf);

bool_t
schizo_rom_store (uint32_t cpu_id, uint64_t  paddr, uint32_t size, uint64_t *buf);

bool_t
schizo_rom_match (uint64_t paddr) ;

///////////////////////////////////////////////
//
// Schizo PROPS impl
//

typedef enum {

     DEV_SCSI     = 11,
     DEV_ETHERNET = 22,
     DEV_SERIAL   = 33

} DevType;


void * schizo_add_dev_to_conf   ( uint32_t type);
void   schizo_add_int_dev_props (void *vpv , char *props_name, uint64_t value);

#endif /* _SCHIZO_IMPL_H */