sam-t2/sam/devices/schizo/include/schizo_mdu.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: schizo_mdu.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/
/*
 * Copyright (C) 1996, Sun Microsystems, Inc.
 */
#ifndef _SCHIZO_MDU_H_
#define _SCHIZO_MDU_H_

#pragma ident "@(#)1.1  01/08/23        schizo_mdu.h"

#define NUM_SL0_INTS            4
#define NUM_SL1_INTS            4
#define NUM_SL2_INTS            4
#define NUM_SL3_INTS            4
#define NUM_SL4_INTS            4
#define NUM_SL5_INTS            4
#define NUM_PCI_INTS            32
#define NUM_OBIO_INTS           16
#define NUM_PULSE_INTS          2
#define NUM_INTERNAL_INT        8
#define NUM_LEVEL_INTS          NUM_PCI_INTS + NUM_OBIO_INTS + MAX_NUM_INTERNAL_INT
#define MAX_NUM_EXTERNAL_INT    NUM_PCI_INTS + NUM_OBIO_INTS + NUM_PULSE_INTS
#define MAX_NUM_INT_SOURCES     MAX_NUM_EXTERNAL_INT + MAX_NUM_INTERNAL_INT

#define IDLE                    0
#define RECIEVED                1
#define PENDING                 3
#define INX_SHIFT               6       /* to get AgentID into INR */
#define INO_MASK              0x3f      /* to get INO into INR */
#define GRAPH_INTR_C            35
#define UPA_INTR_C              38
#define GRAPH_MAP_IND           21
#define UPA_MAP_IND             22
#define GRAPH_SHFT              34
#define UPA_SHFT                35
#define NO_INTERR               50      /* A random high int to diff. NULL and zero */

/* Internal interrupts INO value */
#define UE_ECC                  52
#define CE_ECC                  53
#define SBUS_ERROR              54

#define STATE_MASK      0x00000003      /* get only LSB 2 bits ie int_state */

// Interrupt State Register, Diagnostic Reg
// There are two such registers one for pci_bus_isr and the other obio_isr
// for level interrupts 2 bits are reqd 0-idle, 1-Rcved, 2-illegal, 3-Pending
// for pulse interrupts 1 bit is sufficient, 0-idle 1-recieved.

// epp 220
typedef struct s_pci_bus_isr {
        uint32_t pb3_int_D:2;   // [63:62]
        uint32_t pb3_int_C:2;   // [61:60]
        uint32_t pb3_int_B:2;   // [59:58]
        uint32_t pb3_int_A:2;   // [57:56]
        uint32_t pb2_int_D:2;   // [55:54]
        uint32_t pb2_int_C:2;   // [53:52]
        uint32_t pb2_int_B:2;   // [51:50]
        uint32_t pb2_int_A:2;   // [49:48]
        uint32_t pb1_int_D:2;   // [47:46]
        uint32_t pb1_int_C:2;   // [45:44]
        uint32_t pb1_int_B:2;   // [43:42]
        uint32_t pb1_int_A:2;   // [41:40]
        uint32_t pb0_int_D:2;   // [39:38]
        uint32_t pb0_int_C:2;   // [37:36]
        uint32_t pb0_int_B:2;   // [35:34]
        uint32_t pb0_int_A:2;   // [33:32]
        uint32_t rsvd:16;       // [31:16]
        uint32_t pa1_int_D:2;   // [15:14]
        uint32_t pa1_int_C:2;   // [13:12]
        uint32_t pa1_int_B:2;   // [11:10]
        uint32_t pa1_int_A:2;   // [09:08]
        uint32_t pa0_int_D:2;   // [07:06]
        uint32_t pa0_int_C:2;   // [05:04]
        uint32_t pa0_int_B:2;   // [03:02]
        uint32_t pa0_int_A:2;   // [01:00]
} s_pci_bus_isr;

union u_pci_isr {
        s_pci_bus_isr s;
        uint64_t l;
} u_sbus_isr;

// epp 221
typedef struct s_obio_isr {
        uint32_t rsvd:16;       // [63:48]
        uint32_t int_int_state:16;      // [47:32]
        uint32_t obio_int_state:32;     // [31:00]
} s_obio_isr;

typedef union u_obio_isr {
        s_obio_isr s;
        uint64_t l;
} u_obio_isr;

/*
 * Writing to this Register will caues the interrupt to transit from
 * any state to idle, recieved, or pending depending on value 0,1 or 3 resp.
 * There is one such register for each interrupt
 */

typedef struct s_clear_int {
        uint32_t rsvd2:32;
        uint32_t rsvd1:30;
        uint32_t int_state:2;   /* state the interrupt will transit to */
} s_clear_int_t;

union u_clear_int {
        s_clear_int_t s;
        uint64_t l;
} u_clear_int;

typedef struct s_pulse_clr {
        uint32_t rsvd2:32;
        uint32_t rsvd1:31;
        uint32_t int_state:1;
} s_pulse_clr_t;

union u_pulse_clr {
        s_pulse_clr_t s;
        uint64_t l;
} u_pulse_clr;

/* The mapping registers keeps the INR value for all interrupts. */
// Schizo specification (spp), revision 50, Nov. 2000. spp 201 or epp 218
// epp refers to page number in Excalibur arch manual.
typedef struct s_int_mapping {
        uint32_t rsvd2:32;
        uint32_t v:1;           /* valid bit-rw */
        uint32_t agent_id:5;    /* 30:26 target processor Agent_id-rw */
        uint32_t node_id:5;     /* 25:21 target processor Node_id */
        uint32_t rsvd:10;       /* 20:11 read-only  */
        uint32_t ign:5;         /* 10:6  intr grp Num==AGentid -ro */
        uint32_t ino:6;         /*  5:0interrupt Number offset -ro */
} s_int_mapping_t;

union u_int_mapping {
        s_int_mapping_t s;
        uint64_t l;
} u_int_mapping;

typedef struct s_int_retry_timer {
        uint32_t rsvd2:32;      /* unused */
        uint32_t rsvd1:25;      /* unused */
        uint32_t limit:7;       /* retry interval(max 255 clks delay) */
} s_int_retry_timer_t;

union u_int_retry_timer {
        s_int_retry_timer_t s;
        uint64_t l;
} u_int_retry_timer;

#endif /* _MDU_H */