* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: serial_common.h
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* ========== Copyright Header End ============================================
* Copyright (C) 1991, Sun Microsystems, Inc.
#ident "@(#)1.3 05/05/11 SMI serial_common.h"
* There are 16 write registers and 9 read registers in each channel.
* As usual, the two channels are ALMOST orthogonal, not exactly.
* Most regs can only be written to, or read, but not both.
* To access one, you must first write to register 0 with the number of
* the register you are interested in, then read/write the actual value.
/* bits in RR0 -- Xmit/Rcv Buffer Status & External Status */
#define RX_CHAR_AVAILABLE 0x01 /* received character available */
#define TX_READY 0x04 /* Tx Buffer Empty */
#define DCD 0x08 /* Data Carrier Detect */
#define CTS 0x20 /* Clear To Send */
/* bits in RR1 -- Special Rcv Condition status */
#define ALL_SENT 0x01 /* All characters Sent */
* bits in R/WR2 -- interrupt vector number
* NOTE that RR2 in channel A is unmodified, while in channel B it is
* modified by the current status of the UARTs. (This is independent
* of the setting of WR9_VIS.) If no interrupts are pending, the modified
* status is Channel B Special Receive. It can be written from
* either channel. Vector Includes Status (VIS) codes:
* (these codes get placed in channel B's RR2 on interrupt conditions
#define VIS_LO_MASK 0x0e /* VIS low bits V3,V2,V1 */
#define VIS_HI_MASK 0x70 /* VIS hi bits V6,V5,V4 */
#define TX_BUF_EMPTY 0x00 /* transmit buffer empty */
#define XS_CHANGE 0x02 /* external/status change */
#define RX_CHAR_AVAIL 0x04 /* receive character available */
#define SRC 0x06 /* special receive condition */
#define CHAN_B 0x00 /* channel/port b */
#define CHAN_A 0x08 /* channel/port a */
* bits in RR3 -- Interrupt Pending flags for both channels
* The status for both channels are reported in channel A
* (this register only exists in channel A; this register can only
* be read from channel A)
#define B_IP_MASK 0x07 /* channel B IP bit mask */
#define A_IP_MASK 0x38 /* channel A IP bit mask */
#define B_XS_IP 0x01 /* channel B External/Status Int Pending */
#define B_TX_IP 0x02 /* channel B Transmit Int Pending */
#define B_RX_IP 0x04 /* channel B Receive Int Pending */
#define A_XS_IP 0x08 /* channel A External/Status Int Pending */
#define A_TX_IP 0x10 /* channel A Transmit Int Pending */
#define A_RX_IP 0x20 /* channel A Receive Intr Pending */
/* bits in RR8 -- this is the same as reading the Data port */
/* bits in R/WR12 -- lower byte of time constant for baud rate generator */
/* bits in R/WR13 -- upper byte of time constant for baud rate generator */
/* bits in R/WR15 -- interrupt enables for status conditions */
/* bits in WR0 -- common commands and register pointers */
#define WR0_BITS3_5 0x38 /* wr0 bits 3 through 5 */
#define WR0_BITS4_5 0x30 /* wr0 bits 4 through 5 */
#define WR0_BITS0_4 0xe0 /* Clear WR0 bits 0 through 4 */
#define CMDCODE_MASK 0x38
#define RESET_XS_INT 0x10 /* reset Ext/Stat interrupts */
#define RESET_TX_INT 0x28 /* reset TxINT Pending */
#define ENABLE_RX_INT 0x20 /* enable INT on next Rx character */
#define RESET_ERROR 0x30 /* error reset */
#define RESET_IUS 0x38 /* reset highest Interrupt Under Service */
/* bits in WR1 -- Tx/Rx Interrupt & data tranfer mode register */
#define XS_INT_ENABLED 0x01 /* External/Status Master Interrupt Enable */
#define Tx_INT_ENABLED 0x02 /* Transmit Interrupt Enabled */
#define Rx_INT_ENABLED 0x18 /* Receive Interrupt Enabled */
#define Rx_INT_ALL_d4 0x10 /* Int on all Rx chars (bit d4) */
#define Rx_INT_ALL_d3 0xf7 /* Int on all Rx chars (bit d3) */
/* bits in WR2 -- are defined above as R/WR2. */
/* bits in WR5 -- transmit parameter & controls */
#define RTS 0x02 /* Request To Send */
#define DTR 0x80 /* Data Terminal Ready */
* bits in WR9 -- master interrupt control and reset.
* Accessible thru either channel, there's only one of them.
#define VIS 0x01 /* vector includes status */
#define MIE 0x08 /* master interrupt enable */
/*--------------------------------------------------------------------
* #defines for register manipulation
*--------------------------------------------------------------------
/* Receive interrupt enabled ? */
#define RCV_INT_ENABLED(msp, portnum) \
(msp->scc.port[portnum].wr[1] & Rx_INT_ENABLED ? 1 : 0)
#define SET_RCV_INT_ENABLE(msp, portnum) (msp->scc.port[portnum].wr[1] = \
(msp->scc.port[portnum].wr[1] | Rx_INT_ALL_d4) & Rx_INT_ALL_d3)
/* Transmit interrupt enabled ? */
#define TX_INT_ENABLED(msp, portnum) \
(msp->scc.port[portnum].wr[1] & Tx_INT_ENABLED ? 1 : 0)
/* Master Interrupt Enabled ? */
#define INTERRUPTS_ENABLED(msp, portnum) \
(msp->scc.port[portnum].wr[9] & MIE ? 1 : 0)
#define SET_INTERRUPTS_ENABLE(msp, portnum) (msp->scc.port[portnum].wr[9] |= MIE)
#define CLEAR_INTERRUPTS_ENABLE(msp, portnum) (msp->scc.port[portnum].wr[9] &= ~MIE)
* Vector Include Status kept on RR2 Channel B only
#define SET_VIS_RX_CHAR_AVAIL(msp,portnum) \
( msp->scc.port[PORT_B].rr[2] |= ((portnum == PORT_A) ? \
(CHAN_A | RX_CHAR_AVAIL) : (CHAN_B | RX_CHAR_AVAIL)) )
#define CLEAR_VIS_RX_CHAR_AVAIL(msp) (msp->scc.port[PORT_B].rr[2] &= ~RX_CHAR_AVAIL)
#define SET_VIS_TX_BUF_EMPTY(msp,portnum) \
( msp->scc.port[PORT_B].rr[2] |= ((portnum == PORT_A) ? \
(CHAN_A | TX_BUF_EMPTY) : (CHAN_B | TX_BUF_EMPTY)) )
#define SET_VIS_XS_CHANGE(msp,portnum) \
( msp->scc.port[PORT_B].rr[2] |= ((portnum == PORT_A) ? \
(CHAN_A | XS_CHANGE) : (CHAN_B | XS_CHANGE)) )
#define CLEAR_VIS_XS_CHANGE(msp) \
( msp->scc.port[PORT_B].rr[2] &= ~XS_CHANGE )
* Interrupt status kept on RR3 Channel A only
/* Rcv Interrupt Pending set? */
#define RCV_INT_PENDING(msp, portnum) \
( (msp->scc.port[PORT_A].rr[3] & (portnum == PORT_A ? A_RX_IP : B_RX_IP)) \
#define SET_RCV_INT_PENDING(msp, portnum) \
( msp->scc.port[PORT_A].rr[3] |= ((portnum == PORT_A) ? A_RX_IP : B_RX_IP) )
#define CLEAR_RCV_INT_PENDING(msp, portnum) \
(msp->scc.port[PORT_A].rr[3] &= ((portnum == PORT_A) ? ~A_RX_IP : ~B_RX_IP))
/* Tx Interrupt Pending set? */
#define TX_INT_PENDING(msp, portnum) \
( (msp->scc.port[PORT_A].rr[3] & (portnum == PORT_A ? A_TX_IP : B_TX_IP)) \
#define SET_TX_INT_PENDING(msp, portnum) \
( msp->scc.port[PORT_A].rr[3] |= ((portnum == PORT_A) ? A_TX_IP : B_TX_IP) )
#define CLEAR_TX_INT_PENDING(msp, portnum) \
(msp->scc.port[PORT_A].rr[3] &= ((portnum == PORT_A) ? ~A_TX_IP : ~B_TX_IP))
/* Ext/Status Interrupt Pending set? */
#define XS_INT_PENDING(msp, portnum) \
( (msp->scc.port[PORT_A].rr[3] & (portnum == PORT_A ? A_XS_IP : B_XS_IP)) \
#define SET_XS_INT_PENDING(msp, portnum) \
( msp->scc.port[PORT_A].rr[3] |= ((portnum == PORT_A) ? A_XS_IP : B_XS_IP) )
#define CLEAR_XS_INT_PENDING(msp, portnum) \
(msp->scc.port[PORT_A].rr[3] &= ((portnum == PORT_A) ? ~A_XS_IP : ~B_XS_IP))
// FlexConfig related additions
typedef int (*serial_reg_acc
)(void *, char *buf
, uint64_t paddr
, bool_t wr
);
typedef void (*serial_send
)(void *, char *, int portnum
);
projects / OpenSPARC-T2-SAM / blob