sam-t2/sam/include/dev_props.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dev_props.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
*
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*
* The above named program is distributed in the hope that it will be
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*
* ========== Copyright Header End ============================================
*/

/*
 * Copyright (c) 1992,1993,2000 by Sun Microsystems, Inc
 */

#ifndef _DEVPROPS_H
#define _DEVPROPS_H

#include <sys/pci.h>
#include "property.h"

typedef unsigned long long cell_t;

typedef int     ihandle_t;
typedef void    *phandle_t;
typedef void    *dnode_t;


#define STDIN_DEV       (ihandle_t)1
#define STDOUT_DEV      (ihandle_t)2
#define MAXMLIST        150
#define NUMMLIST        4
#define MAXTLIST        1024

/* will be drived in scsi.so with sysconf param*/
#define PCIA_SCSI00_OFFSET_1         0x0000
#define PCIA_SCSI00_OFFSET_2         0x0100
#define PCIA_SCSI00_OFFSET_3         0x1000

#define PCIA_SCSI01_OFFSET_1         0x2000
#define PCIA_SCSI01_OFFSET_2         0x2100
#define PCIA_SCSI01_OFFSET_3         0x3000

#define SCSI_CTRL_RSIZE_1       0x00100
#define SCSI_CTRL_RSIZE_2       0x00100
#define SCSI_CTRL_RSIZE_3       0x01000
#define SCSI_CTRL_RSIZE         0x02000


char psname[]           = "name";
char psreg[]            = "reg";
char psexist[]          = "existing";
char psinterrupts[]     = "interrupts";
char psavail[]          = "available";
char psunit[]           = "unit";
char psrange[]          = "ranges";
char psccoher[]         = "cache-coherence?";
char pspagesize[]       = "page-size";
char psdevtype[]        = "device_type";
char psmmc[]            = "memory-controller";
char psvme[]            = "vme";
char psiommu[]          = "iommu";
char psproc[]           = "processor";
char psgraph[]          = "graphics";
char psblock[]          = "block";
char psnetwork[]        = "network";
char psaddress[]        = "address";
char psclasscode[]      = "class-code";
char psaddresscells[]   = "#address-cells";
char pssizecells[]      = "#size-cells";
char psdevicetype[]        = "device_type";
char psclockfrequency[]    = "clock-frequency";
char psmodel[]             = "model";
char pscompatible[]        = "compatible";
char psdevselspeed[]       = "devsel-speed";
char psmaxlatency[]        = "max-latency";
char psmingrant[]          = "min-grant";
char psrevisionid[]        = "revision-id";
char psdeviceid[]          = "device-id";
char psvendorid[]          = "vendor-id";
char psversion[]           ="version";


#if 0// also defined in type.h
struct property {
        char    *name;
        int     size;
        caddr_t value;
};
#endif

typedef struct dev_element {
        struct dev_element *next;
        struct dev_element *slaves;
        struct property    *props;
} devnode_t;

struct dev_range {
        u_int rng_cbustype;             /* Child's address, hi order */
        u_int rng_coffset;              /* Child's address, lo order */
        u_int rng_bustype;              /* Parent's address, hi order */
        u_int rng_offset;               /* Parent's address, lo order */
        u_int rng_size;                 /* size of space for this entry */
};

struct dev_reg64 {
        uint_t addr_hi;
        uint_t addr_lo;
        uint_t size_hi;
        uint_t size_lo;
};

struct pci_range {
        u_int   child_hi;
        u_int   child_mid;
        u_int   child_lo;
        u_int   parent_hi;
        u_int   parent_lo;
        u_int   size_hi;
        u_int   size_lo;
};

struct sun4u_prom_memlist {
        u_longlong_t    addr;
        u_longlong_t    size;
};

struct ihandleops {
        void (* method1) (caddr_t);
        void (* method2) (caddr_t);
};


/* root node:
 */

typedef struct idprom {
         uint8_t id_format;      /* format identifier */
         /*
          * The following fields are valid only in format IDFORM_1.
          */
         uint8_t id_machine;     /* machine type */
         uint8_t id_ether[6];    /* ethernet address */
         int32_t id_date;        /* date of manufacture */
         uint32_t id_serial:24;  /* serial number */
         uint8_t id_xsum;        /* xor checksum */
         uint8_t id_undef[16];   /* undefined */
 } idprom_t;

idprom_t idprom = {

        0x01,
        /* The following fields are valid only in format IDFORM_1.
         */
        0x80,           /* machine type */
        0x08,0x00,0x20,0x00,0x00,0x00,  /* ethernet address */
        0x00000000,     /* date of manufacture */
        0x000000,       /* serial number - 24bits */
        0xa9,           /* xor checksum */
        0,0,0,0,0,0     /* undefined - 16 bytes */
};

static int cpu_tick_freq=900000000;
static int excalibur_stick_freq=12500000;
static unsigned long long ramsize;

int size_cells = 0x2;

ihandle_t stdin_dev = STDIN_DEV;
ihandle_t stdout_dev = STDOUT_DEV;

static caddr_t pci_a_address[] = { 0, 0, 0 };
static caddr_t pci_b_address[] = { 0, 0, 0 };
static int three = 3;
static int two = 2;
static int zero = 0;
static int four = 4;

#define SCHIZO_IO_SAFARI_PORTID 31
#define SCHIZO_INTR(n)          ((n) | (SCHIZO_IO_SAFARI_PORTID << 6))


/*
 * pcidisk node:
 */

#define BUS(n)          ((n) << 16)
#define DEV(n)          ((n) << 11)
#define FUN(n)          ((n) << 8)

#define CONFIG_ADDR(b,d,f)      \
        { PCI_ADDR_CONFIG|BUS(b)|DEV(d)|FUN(f), 0x0, 0x0, 0x0, 0x0 }

#define MEMORY_ADDR(b,d,f,a,s)  \
        { PCI_RELOCAT_B|PCI_ADDR_MEM32|BUS(b)|DEV(d)|FUN(f), 0x0, (a), 0x0, (s) }

#define MEMORY_ADDR_BOOTBUS(b,d,f,a,s)  \
        { PCI_RELOCAT_B|PCI_ADDR_MEM32|BUS(b)|DEV(d)|FUN(f)|0x10, 0x0, (a), 0x0, (s) }


#if 0
static int pciA_scsi00_intr = SCHIZO_INTR(0x0);
static int pciA_scsi01_intr = SCHIZO_INTR(0x1);
static int scsi_ctrl_clock_freq   = 0x02625A00;
static int scsi_ctrl_devsel_speed = 0x00000001;
static int scsi_ctrl_classcode    = 0x00010000;
static int scsi_ctrl_max_latency  = 0x00000040;
static int scsi_ctrl_min_grant    = 0x00000011;
static int scsi_ctrl_revision_id  = 0x00000003;
static int scsi_ctrl_device_id    = 0x0000000F;
static int scsi_ctrl_vendor_id    = 0x00001000;
static pci_regspec_t  pciA_scsi00_reg[] = {
        CONFIG_ADDR(0, 0, 0),
        MEMORY_ADDR(0, 0, 0, PCIA_SCSI00_OFFSET_1, SCSI_CTRL_RSIZE_1),
        MEMORY_ADDR(0, 0, 0, PCIA_SCSI00_OFFSET_2, SCSI_CTRL_RSIZE_2),
        MEMORY_ADDR(0, 0, 0, PCIA_SCSI00_OFFSET_3, SCSI_CTRL_RSIZE_3)
};
static struct property pciA_scsi00_props[] = {
        { psname,                5, "scsi" },
        { psinterrupts,         ARRAY(pciA_scsi00_intr) },
        { psdevicetype,         7, "scsi-2" },
        { psclockfrequency,     ARRAY(scsi_ctrl_clock_freq) },
        { psreg,                RARRAY(pciA_scsi00_reg) },
        { psmodel,              15, "Symbios,53C875" },
        { psaddresscells,         ARRAY(three) },
        { pssizecells,                 ARRAY(two) },
        { pscompatible,         4, "glm" },
        { psdevselspeed,        ARRAY(scsi_ctrl_devsel_speed) },
        { psclasscode,          ARRAY(scsi_ctrl_classcode) },
        { psmaxlatency,         ARRAY(scsi_ctrl_max_latency) },
        { psmingrant,           ARRAY(scsi_ctrl_min_grant) },
        { psrevisionid,         ARRAY(scsi_ctrl_revision_id) },
        { psdeviceid,           ARRAY(scsi_ctrl_device_id) },
        { psvendorid,           ARRAY(scsi_ctrl_vendor_id) },
        { NULL }
};

static pci_regspec_t pciA_scsi01_reg[] = {
        CONFIG_ADDR(0, 1, 0),
        MEMORY_ADDR(0, 1, 0, PCIA_SCSI01_OFFSET_1, SCSI_CTRL_RSIZE_1),
        MEMORY_ADDR(0, 1, 0, PCIA_SCSI01_OFFSET_2, SCSI_CTRL_RSIZE_2),
        MEMORY_ADDR(0, 1, 0, PCIA_SCSI01_OFFSET_3, SCSI_CTRL_RSIZE_3)
};


static struct property pciA_scsi01_props[] = {
        { psname,                5, "scsi" },
        { psinterrupts,         ARRAY(pciA_scsi01_intr) },
        { psdevicetype,         7, "scsi-2" },
        { psclockfrequency,     ARRAY(scsi_ctrl_clock_freq) },
        { psreg,                RARRAY(pciA_scsi01_reg) },
        { psmodel,              15, "Symbios,53C875" },
        { psaddresscells,         ARRAY(three) },
        { pssizecells,                 ARRAY(two) },
        { pscompatible,         4, "glm" },
        { psdevselspeed,        ARRAY(scsi_ctrl_devsel_speed) },
        { psclasscode,          ARRAY(scsi_ctrl_classcode) },
        { psmaxlatency,         ARRAY(scsi_ctrl_max_latency) },
        { psmingrant,           ARRAY(scsi_ctrl_min_grant) },
        { psrevisionid,         ARRAY(scsi_ctrl_revision_id) },
        { psdeviceid,           ARRAY(scsi_ctrl_device_id) },
        { psvendorid,           ARRAY(scsi_ctrl_vendor_id) },
        { NULL }
};
#endif

/* bootbus controller */
#define BOOTBUS_CTRL_OFFSET          0x90000
#define BOOTBUS_CTRL_RSIZE           0x8000000

/*
 * bootbus controller node:
 */
static pci_regspec_t bootbus_ctrl_reg[] =
        { CONFIG_ADDR(1, 4, 0),
          MEMORY_ADDR_BOOTBUS(1, 4, 0, BOOTBUS_CTRL_OFFSET, BOOTBUS_CTRL_RSIZE)
        };

static int bootbus_ctrl_intr = SCHIZO_INTR(0x1d);               //use the interrupe for diskB4

static int bootbus_ctrl_classcode = 0x00068000;
static int bootbus_ctrl_devsel_speed = 0x00000001;
static int bootbus_ctrl_max_latency  = 0x000000;
static int bootbus_ctrl_min_grant    = 0x000000;
static int bootbus_ctrl_device_id    = 0x0000c416;
static int bootbus_ctrl_vendor_id    = 0x0000108e;
static int bootbus_ctrl_revision_id  = 0x00000002;
static int bootbus_ctrl_latency_timer = 0x40;
static int bootbus_ctrl_cache_line_size = 0x10;

static struct property bootbus_ctrl_props[] =
        {       { psname,               19, "bootbus-controller" },
                { "model",              12, "SUNW,sgsbbc" },
                { psreg,                RARRAY(bootbus_ctrl_reg) },
                { psinterrupts,         ARRAY(bootbus_ctrl_intr) },
                { psclasscode,          ARRAY(bootbus_ctrl_classcode)},
                { psdevselspeed,        ARRAY(bootbus_ctrl_devsel_speed) },
                { psmaxlatency,         ARRAY(bootbus_ctrl_max_latency) },
                { psmingrant,           ARRAY(bootbus_ctrl_min_grant) },
                { psrevisionid,         ARRAY(bootbus_ctrl_revision_id) },
                { "latency-timer",      ARRAY(bootbus_ctrl_latency_timer) },
                { "cache-line-size",    ARRAY(bootbus_ctrl_cache_line_size)},
                { psdeviceid,           ARRAY(bootbus_ctrl_device_id) },
                { psvendorid,           ARRAY(bootbus_ctrl_vendor_id) },
                { "compatible",         7, "sgsbbc"},
                { NULL },
        };

devnode_t bootbus_ctrl_info = {NULL, NULL, bootbus_ctrl_props, }; // on pciB slot 4
/*
 * pcisimc node:
 */
/* pcisimc (bus b) */
#define PCISIMC_OFFSET          0x32000
#define PCISIMC_RSIZE           0x1000

static pci_regspec_t pcisimc_reg[] =
        { CONFIG_ADDR(1, 25, 0),
          MEMORY_ADDR(1, 25, 0, PCISIMC_OFFSET, PCISIMC_RSIZE)
        };

static int pcisimc_intr = SCHIZO_INTR(0x36);


static int pcisimc_classcode = 0x0;

static struct property pcisimc_props[] =
        {       { psname,               8, "pcisimc" },
                { psreg,                RARRAY(pcisimc_reg) },
                { psaddresscells,       ARRAY(three) },
                { pssizecells,          ARRAY(two) },
                { psdevtype,            7, "serial" },
                { psinterrupts,         ARRAY(pcisimc_intr) },
                { "port-b-ignore-cd", 0, 0 },
                { "port-a-ignore-cd", 0, 0 },
                { psclasscode,          ARRAY(pcisimc_classcode)},
                { NULL },
        };
static caddr_t fp_reg = 0;
static struct property fp_props[] = {
        { psdevicetype,         3, "fp" },
        { psname,               3, "fp" },
        { psaddresscells,       ARRAY(four) },
        { pssizecells,          ARRAY(zero) },
        { psreg,                ARRAY(fp_reg) },
        { NULL }
};
/*
 *  disk node:
 */

static struct property ssd_disk_props[] = {
        { psdevicetype,         6, "block" },
        { "compatible",         3, "ssd" },
        { psname,               5, "disk" },
        { "lun",                ARRAY(zero) },
        { NULL }
};
/*
 * rtc node:
 */
static uint32_t rtc_addr;

static struct property rtc_props[] = {
        { psname,               4, "rtc" },
        { "model",              7, "ds1287" },
        { psaddresscells,       ARRAY(two) },
        { psaddress,            ARRAY(rtc_addr) },
        { NULL },
};

/*
 * Children of pci B
 */
/* ll (bus b) */
#define LL_OFFSET               0x34000
#define LL_RSIZE                0x2000

/* bid (bus a) */
#define BID_OFFSET              0x32000
#define BID_RSIZE               0x2000

static pci_regspec_t ll_reg[] = {
        CONFIG_ADDR(1, 26, 0),
        MEMORY_ADDR(1, 26, 0, LL_OFFSET, LL_RSIZE)
};

static int ll_classcode = 0x0;

static struct property ll_props[] = {
        { psname,               3, "ll" },
        { psreg,                RARRAY(ll_reg) },
        { psaddresscells,       ARRAY(three) },
        { pssizecells,          ARRAY(two) },
        { psclasscode,          ARRAY(ll_classcode)},
        { NULL },
};

/*
 * bid node:
 */
static pci_regspec_t bid_reg[] = {
        CONFIG_ADDR(0, 25, 0),
        MEMORY_ADDR(0, 25, 0, BID_OFFSET, BID_RSIZE)
};

static int bid_classcode = 0x0;

static struct property bid_props[] = {
        { psname,               4, "bid" },
        { psreg,                RARRAY(bid_reg) },
        { psaddresscells,       ARRAY(three) },
        { pssizecells,          ARRAY(two) },
        { psclasscode,          ARRAY(bid_classcode)},
        { NULL },
};

/*
 * Root
 */
devnode_t root_info =           { NULL, NULL, NULL, };

devnode_t *memory_info_p = NULL;
devnode_t *vmemory_info_p = NULL;

#endif /* _DEVPROPS_H */