| 1 | @ Test 0 v 0 = 0 |
| 2 | SSSSN | PUSH 0 |
| 3 | SSSSN | PUSH 0 |
| 4 | NSTTSTSTSN | JSR > 101010 (or) |
| 5 | NSTTTTTSTN | JSR > 111101 (debug:printsignednumber) |
| 6 | |
| 7 | @ Test 0 v 1 = 1 |
| 8 | SSSSN | PUSH 0 |
| 9 | SSSTN | PUSH +1 |
| 10 | NSTTSTSTSN | JSR > 101010 (or) |
| 11 | NSTTTTTSTN | JSR > 111101 (debug:printsignednumber) |
| 12 | |
| 13 | @ Test 1 v 1 = 1 |
| 14 | SSSTN | PUSH +1 |
| 15 | SSSTN | PUSH +1 |
| 16 | NSTTSTSTSN | JSR > 101010 (or) |
| 17 | NSTTTTTSTN | JSR > 111101 (debug:printsignednumber) |
| 18 | |
| 19 | @ Test 1 v 1...1 = 1...1 |
| 20 | SSSTN | PUSH +1 |
| 21 | SSTTN | PUSH -1 |
| 22 | NSTTSTSTSN | JSR > 101010 (or) |
| 23 | NSTTTTTSTN | JSR > 111101 (debug:printsignednumber) |
| 24 | |
| 25 | @ Test 1010...1010 v 0101...0101 = 1...1 |
| 26 | @ Note that -6148914691236517206 = 1010...1010 in twos-complement but we |
| 27 | @ enter it in sign magnitude format so the bit pattern appears different. |
| 28 | SSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTTSN | PUSH -6148914691236517206 |
| 29 | SSSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTSTN | PUSH +6148914691236517205 |
| 30 | NSTTSTSTSN | JSR > 101010 (or) |
| 31 | NSTTTTTSTN | JSR > 111101 (debug:printsignednumber) |
| 32 | |
| 33 | @ All done. |
| 34 | NNN | DIE |
| 35 | |
| 36 | #include <logic.pvvs> |
| 37 | #include <debug.pvvs> |