| 1 | NED - Architecture Manual |
| 2 | ========================= |
| 3 | |
| 4 | Instruction Word Formats |
| 5 | ------------------------ |
| 6 | |
| 7 | All instruction words in NED are 32-bits long and fall into one of three |
| 8 | possible formats. |
| 9 | |
| 10 | +---------+-----+-----+--------+--------+--------+--------+--------+ |
| 11 | | Format | 31 | 30 | 29..24 | 23..18 | 17..12 | 11..6 | 5..0 | |
| 12 | +---------+-----+-----+--------+--------+--------+--------+--------+ |
| 13 | | A | 1 | 31-bit Immediate | |
| 14 | +---------+-----+-----+--------------------------------------------+ |
| 15 | | B | 0 | 1 | Unassigned | |
| 16 | +---------+-----+-----+--------+--------+--------+--------+--------+ |
| 17 | | C | 0 | 0 | Syl. 1 | Syl. 2 | Syl. 3 | Syl. 4 | Syl. 5 | |
| 18 | +---------+-----+-----+--------+--------+--------+--------+--------+ |
| 19 | |
| 20 | Format A contains a 31-bit field which is placed on the stack after shifting |
| 21 | left one position and padding with a zero. For example, the instruction |
| 22 | |
| 23 | 11000000 01000000 01000000 01000000 |
| 24 | |
| 25 | will place the value |
| 26 | |
| 27 | 10000000 10000000 10000000 10000000 |
| 28 | |
| 29 | on the TOS. |
| 30 | |
| 31 | Format B is reserved for future instructions. |
| 32 | |
| 33 | Format C packs five syllables per instruction word, executed in order from 1 to 5. |
| 34 | Syllables are defined as follows. |
| 35 | |
| 36 | | Bits | Name | Description | |
| 37 | | ------ | ------ | ---------------------------------------------------------- | |
| 38 | | 1xxxxx | IM_x | Push a 5-bit immediate to TOS. | |
| 39 | | 011xxx | LDSP+x | Copy the value stored at TOS+x and push to TOS. | |
| 40 | | 010xxx | STSP+x | Pop from TOS and overwrite value at TOS+x. | |
| 41 | | 001000 | AND | Logical AND of TOS and NOS, pushed to TOS. | |
| 42 | | 001001 | OR | Logical OR of TOS and NOS, pushed to TOS. | |
| 43 | | 001010 | NOT | Logical NOT of TOS, pushed to TOS. | |
| 44 | | 001011 | XOR | Logical XOR of TOS and NOS, pushed to TOS. | |
| 45 | | 001100 | ADD | Signed, twos-complement addition. TOS <- TOS + NOS | |
| 46 | | 001101 | SWAP | Swap TOS and NOS. | |
| 47 | | 001110 | JMP | Pop TOS and set PC to popped value. | |
| 48 | | 001111 | MVSTCK | Pop the TOS and context switch to that state ID. | |
| 49 | | 000100 | SHIFT | Pop TOS & NOS. Shift NOS by TOS bits to the left/right. | |
| 50 | | 000101 | CMPSWP | Compare-and-swap with ptr, old_val & new_val on stack. | |
| 51 | | 000110 | TEST | Pop TOS and set PSW according to value. | |
| 52 | | 000111 | BRZ | Pop TOS & NOS. If NOS==0, then set PC to TOS value. | |
| 53 | | 000010 | LOAD | Pop address from TOS, dereference and store to TOS. | |
| 54 | | 000011 | STORE | Pop address from TOS, pop data from NOS, deref and store. | |
| 55 | | 000001 | NOP | Do nothing. | |
| 56 | | 000000 | HALT | Halt the CPU. | |
| 57 | |
| 58 | The Instruction Reference contains a more complete description of these operations. |
| 59 | |
| 60 | Processor State |
| 61 | --------------- |
| 62 | |
| 63 | The Processor Status Word (PSW) contains *N*egative and *Z*ero flags in the |
| 64 | following bit positions. See the Instruction Reference for details on which |
| 65 | operations set these flags. |
| 66 | |
| 67 | +-------+------------+-----+-----+ |
| 68 | | Bits | 31..2 | 1 | 0 | |
| 69 | +-------+------------+-----+-----+ |
| 70 | | Flags | Unassigned | N | Z | |
| 71 | +-------+------------+-----+-----+ |
| 72 | |
| 73 | In addition to a traditional Program Counter (PC), the processor also includes |
| 74 | a Syllable Counter (SC) which ranges from 0 to 4. Both the PC and SC point to |
| 75 | the next instruction to be executed. Thus, when executing the middle syllable |
| 76 | of a word located at address 0x200, the PC is 0x204 and the SC is 3. |
| 77 | |
| 78 | Since the CPU is stack based, it includes a Stack Pointer (SP). |
| 79 | |
| 80 | Memory Map |
| 81 | ---------- |
| 82 | |
| 83 | The address space is laid out with memory mapped I/O below 512 MB and RAM above. |
| 84 | |
| 85 | 4 GB |
| 86 | |-------- Data |
| 87 | 512 MB |
| 88 | |-------- I/O (general purpose) |
| 89 | 128 MB |
| 90 | |-------- I/O (reserved for processors in 16 MB chucks x 8 CPUs) |
| 91 | 0 Mb |
| 92 | |
| 93 | Temporarily, there are four read-only registers accessible in the lowest four |
| 94 | words of memory. Writes to these registers are ignored. |
| 95 | |
| 96 | | Address | Name | Description | |
| 97 | | ------- | ----------------- | ------------------------------- | |
| 98 | | 0x0 | Zero Register | Constant 0x0 | |
| 99 | | 0x4 | Negative Register | Constant 0x80000000 | |
| 100 | | 0x8 | PC Register | PC of currently active thread. | |
| 101 | | 0xC | PSW Register | PSW of currently active thread. | |
| 102 | |
| 103 | Also temporarily, a UART-like peripheral is present with the following registers. |
| 104 | |
| 105 | | Address | Name | Description | |
| 106 | | --------- | --------------- | ----------------------------------------------- | |
| 107 | | 0x8000000 | Transmit Buffer | Accepts one byte and transmits to stdout. | |
| 108 | | 0x8000004 | Transmit Status | Bit 0 is set when UART is ready to send a byte. | |
| 109 | | 0x8000008 | Receive Buffer | Contains one byte from stdin. | |
| 110 | | 0x800000C | Receive Status | Bit 0 is set when a byte is ready to be read. | |