projects / xeon-phi-kernel-module / blame
| Commit | Line | Data |
|---|---|---|
| 800f879a AT |
1 | /* |
| 2 | * Copyright 2010-2017 Intel Corporation. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms of the GNU General Public License, version 2, | |
| 6 | * as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope that it will be useful, | |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 11 | * General Public License for more details. | |
| 12 | * | |
| 13 | * Disclaimer: The codes contained in these modules may be specific to | |
| 14 | * the Intel Software Development Platform codenamed Knights Ferry, | |
| 15 | * and the Intel product codenamed Knights Corner, and are not backward | |
| 16 | * compatible with other Intel products. Additionally, Intel will NOT | |
| 17 | * support the codes or instruction set in future products. | |
| 18 | * | |
| 19 | * Intel offers no warranty of any kind regarding the code. This code is | |
| 20 | * licensed on an "AS IS" basis and Intel is not obligated to provide | |
| 21 | * any support, assistance, installation, training, or other services | |
| 22 | * of any kind. Intel is also not obligated to provide any updates, | |
| 23 | * enhancements or extensions. Intel specifically disclaims any warranty | |
| 24 | * of merchantability, non-infringement, fitness for any particular | |
| 25 | * purpose, and any other warranty. | |
| 26 | * | |
| 27 | * Further, Intel disclaims all liability of any kind, including but | |
| 28 | * not limited to liability for infringement of any proprietary rights, | |
| 29 | * relating to the use of the code, even if Intel is notified of the | |
| 30 | * possibility of such liability. Except as expressly stated in an Intel | |
| 31 | * license agreement provided with this code and agreed upon with Intel, | |
| 32 | * no license, express or implied, by estoppel or otherwise, to any | |
| 33 | * intellectual property rights is granted herein. | |
| 34 | */ | |
| 35 | ||
| 36 | /* | |
| 37 | * Trace Capture module common declarations | |
| 38 | * | |
| 39 | * Contains configuration, constants and function prototypes | |
| 40 | * for the Trace Capture module. | |
| 41 | */ | |
| 42 | ||
| 43 | #ifndef _MICTC_H_ | |
| 44 | #define _MICTC_H_ 1 | |
| 45 | ||
| 46 | #include <linux/types.h> | |
| 47 | #include <linux/errno.h> | |
| 48 | #include <linux/init.h> | |
| 49 | #include <linux/kernel.h> | |
| 50 | //#include <linux/sched.h> | |
| 51 | #include <linux/module.h> | |
| 52 | #include <linux/delay.h> | |
| 53 | #include <linux/init.h> | |
| 54 | #include <linux/smp.h> | |
| 55 | #include <linux/nmi.h> | |
| 56 | #include <linux/kdebug.h> | |
| 57 | #include <linux/slab.h> | |
| 58 | #include <linux/ratelimit.h> | |
| 59 | #include <linux/fs.h> | |
| 60 | ||
| 61 | #include <asm/uaccess.h> // for get_user and put_user | |
| 62 | #include <asm/processor.h> | |
| 63 | #include <asm/debugreg.h> | |
| 64 | #include <asm/apicdef.h> | |
| 65 | #include <asm/system.h> | |
| 66 | #include <asm/apic.h> | |
| 67 | #include <asm/nmi.h> | |
| 68 | #include <asm/irq_regs.h> | |
| 69 | #include <asm/svm.h> | |
| 70 | #include <asm/desc.h> | |
| 71 | #include <linux/ioctl.h> | |
| 72 | ||
| 73 | #ifndef __SCIF_H__ | |
| 74 | #include <scif.h> | |
| 75 | #endif | |
| 76 | ||
| 77 | /* | |
| 78 | * Version info: M.NP | |
| 79 | */ | |
| 80 | ||
| 81 | #define TC_MAJOR "0" | |
| 82 | #define TC_MINOR "1" | |
| 83 | #define TC_PATCH "a" | |
| 84 | #define TC_VER TC_MAJOR "." TC_MINOR TC_PATCH | |
| 85 | ||
| 86 | // These are common to the Host App | |
| 87 | // and the MIC driver Trace Capture Feature | |
| 88 | // COMMON DEFINES START HERE | |
| 89 | enum TRACE_COMMAND | |
| 90 | { | |
| 91 | TRACE_NOP = 100, | |
| 92 | TRACE_DATA, | |
| 93 | TRACE_HOST_READY, | |
| 94 | TRACE_DONE, | |
| 95 | TRACE_ERROR, | |
| 96 | TRACE_PRINT, | |
| 97 | TRACE_GET_FILE, | |
| 98 | TRACE_PAGE_READY, | |
| 99 | TRACE_REG_COMPLETE, | |
| 100 | TRACE_MEM_COMPLETE, | |
| 101 | TRACE_COMPLETE, | |
| 102 | TRACE_ABORTED | |
| 103 | }; | |
| 104 | ||
| 105 | // IOCTL | |
| 106 | #define MICTC_MAJOR_NUM 's' | |
| 107 | #define MICTC_DEVICE_NAME "trace_capture" | |
| 108 | #define MICTC_FILE_NAME "/dev/trace_capture" | |
| 109 | ||
| 110 | #define MICTC_START_CAPTURE _IOW(MICTC_MAJOR_NUM, 0xff, int) | |
| 111 | ||
| 112 | // Use 2MB for KNF and 4MB for K1OM (auto-detected). | |
| 113 | #define MICTC_XML_BUFFER_SIZE (2 * 1024UL * 1024UL) | |
| 114 | ||
| 115 | #define MICTC_MEM_BUFFER_SIZE (1 * 1024UL * 1024UL * 1024UL) | |
| 116 | ||
| 117 | // Shared memory constants | |
| 118 | #define TRACE_STATUS_OFFSET 8 | |
| 119 | #define TRACE_SIZE_OFFSET 16 | |
| 120 | ||
| 121 | // Enable/Disable Memory Test. | |
| 122 | // This MUST be enabled simultaneously on Host App as well. | |
| 123 | #define MIC_TRACE_CAPTURE_MEMORY_TEST 0 | |
| 124 | ||
| 125 | #if MIC_TRACE_CAPTURE_MEMORY_TEST | |
| 126 | #define TRACE_CHECKSUM_OFFSET 24 | |
| 127 | #endif | |
| 128 | ||
| 129 | #define TRACE_TRIGGER_MAX 10 | |
| 130 | #define TRACE_TRIGGER_OFFSET 28 | |
| 131 | #define TRACE_DATA_OFFSET 4096 | |
| 132 | ||
| 133 | // Used to indicate the end of the list for trace triggers. | |
| 134 | #define TRACE_EOL 0xffffffff | |
| 135 | // Used for trace counts to indicate that the driver should ignore current trace. | |
| 136 | // Only meaningful when it is first in the list of trace triggers -- the entries | |
| 137 | // after it are ignored. Trace counts supersede trace triggers. | |
| 138 | #define TRACE_IGNORE 0xfffffffe | |
| 139 | ||
| 140 | // Types of Triggers - Refer to uOS Trace Capture Wiki for Usage | |
| 141 | // Generic counter | |
| 142 | #define TRACE_HOST_GENERIC_COUNTER 0x1 | |
| 143 | // Async Flip counter | |
| 144 | #define TRACE_HOST_FRAME_COUNTER 0x2 | |
| 145 | // COMMON DEFINES END HERE | |
| 146 | ||
| 147 | // MSR's defined in the trace file sent during REQs | |
| 148 | // Are these all valid for L1OM?? | |
| 149 | #define P6_CR_TSC 0x10 | |
| 150 | #define X86_CR_APICBASE 0x1b | |
| 151 | #define MIC_CR_SPUBASE 0x1c | |
| 152 | #define IA32_CR_MISC 0x1a0 | |
| 153 | #define WMT_CR_LASTBRANCH_0 0x1db | |
| 154 | #define WMT_CR_LASTBRANCH_1 0x1dc | |
| 155 | #define X86_CR_MTRRphysMask0 0x201 | |
| 156 | #define X86_CR_MTRRphysMask1 0x203 | |
| 157 | #define X86_CR_MTRRphysMask2 0x205 | |
| 158 | #define X86_CR_MTRRphysMask3 0x207 | |
| 159 | #define X86_CR_MTRRphysMask4 0x209 | |
| 160 | #define X86_CR_MTRRphysMask5 0x20b | |
| 161 | #define X86_CR_MTRRphysMask6 0x20d | |
| 162 | #define X86_CR_MTRRphysMask7 0x20f | |
| 163 | #define IA32_CR_PAT 0x277 | |
| 164 | #define IA32_MTRR_DEF_TYPE 0x2ff | |
| 165 | #define VMX_MSR_BASE 0x480 | |
| 166 | #define VMX_MSR_BASE_PLUS_1 0x481 | |
| 167 | #define VMX_MSR_BASE_PLUS_2 0x482 | |
| 168 | #define VMX_MSR_BASE_PLUS_3 0x483 | |
| 169 | #define VMX_MSR_BASE_PLUS_4 0x484 | |
| 170 | #define VMX_MSR_BASE_PLUS_5 0x485 | |
| 171 | #define VMX_MSR_BASE_PLUS_6 0x486 | |
| 172 | #define VMX_MSR_BASE_PLUS_7 0x487 | |
| 173 | #define VMX_MSR_BASE_PLUS_8 0x488 | |
| 174 | #define VMX_MSR_BASE_PLUS_9 0x489 | |
| 175 | #define TIME 0x4711 | |
| 176 | #define PINFO 0x4712 | |
| 177 | #define X86_CR_MTRRdefType 0x2ff | |
| 178 | #define X86_CR_MTRRcap 0xfe | |
| 179 | #define X86_CR_MTRRphysBase0 0x200 | |
| 180 | #define X86_CR_MTRRphysBase1 0x202 | |
| 181 | #define X86_CR_MTRRphysBase2 0x204 | |
| 182 | #define X86_CR_MTRRphysBase3 0x206 | |
| 183 | #define X86_CR_MTRRphysBase4 0x208 | |
| 184 | #define X86_CR_MTRRphysBase5 0x20a | |
| 185 | #define X86_CR_MTRRphysBase6 0x20c | |
| 186 | #define X86_CR_MTRRphysBase7 0x20e | |
| 187 | #define X86_CR_MTRRfix64K_00000 0x250 | |
| 188 | #define X86_CR_MTRRfix16K_80000 0x258 | |
| 189 | #define X86_CR_MTRRfix16K_A0000 0x259 | |
| 190 | #define X86_CR_MTRRfix4K_C0000 0x268 | |
| 191 | #define X86_CR_MTRRfix4K_C8000 0x269 | |
| 192 | #define X86_CR_MTRRfix4K_D0000 0x26a | |
| 193 | #define X86_CR_MTRRfix4K_D8000 0x26b | |
| 194 | #define X86_CR_MTRRfix4K_E0000 0x26c | |
| 195 | #define X86_CR_MTRRfix4K_E8000 0x26d | |
| 196 | #define X86_CR_MTRRfix4K_F0000 0x26e | |
| 197 | #define X86_CR_MTRRfix4K_F8000 0x26f | |
| 198 | #define P5_MC_ADDR 0x0 | |
| 199 | #define P5_MC_TYPE 0x1 | |
| 200 | #define MSR_TR1 0x2 | |
| 201 | #define MSR_TR2 0x4 | |
| 202 | #define MSR_TR3 0x5 | |
| 203 | #define MSR_TR4 0x6 | |
| 204 | #define MSR_TR5 0x7 | |
| 205 | #define MSR_TR6 0x8 | |
| 206 | #define MSR_TR7 0x9 | |
| 207 | #define MSR_TR9 0xb | |
| 208 | #define MSR_TR10 0xc | |
| 209 | #define MSR_TR11 0xd | |
| 210 | #define MSR_TR12 0xe | |
| 211 | #define IA32_APIC_BASE 0x1b | |
| 212 | #define IA32_TIME_STAMP_COUNTER 0x10 | |
| 213 | #define IA32_PerfCntr0 0x20 | |
| 214 | #define IA32_PerfCntr1 0x21 | |
| 215 | #define IA32_PerfCntr2 0x22 | |
| 216 | #define IA32_PerfCntr3 0x23 | |
| 217 | #define PerfFilteredCntr0 0x24 | |
| 218 | #define PerfFilteredCntr1 0x25 | |
| 219 | #define PerfFilteredCntr2 0x26 | |
| 220 | #define PerfFilteredCntr3 0x27 | |
| 221 | #define IA32_PerfEvtSel0 0x28 | |
| 222 | #define IA32_PerfEvtSel1 0x29 | |
| 223 | #define IA32_PerfEvtSel2 0x2a | |
| 224 | #define IA32_PerfEvtSel3 0x2b | |
| 225 | #define PerfFilterMask 0x2c | |
| 226 | #define IA32_PERF_GLOBAL_STATUS 0x2d | |
| 227 | #define IA32_PERF_GLOBAL_OVF_CONTROL 0x2e | |
| 228 | #define IA32_PERF_GLOBAL_CTRL 0x2f | |
| 229 | #define IA32_MCG_CTL 0x17b | |
| 230 | #define IA32_MC0_CTRL 0x400 | |
| 231 | #define IA32_MC0_STAT 0x401 | |
| 232 | #define IA32_MC0_ADDR 0x402 | |
| 233 | #define IA32_MC0_MISC 0x403 | |
| 234 | #define IA32_MC1_CTRL 0x404 | |
| 235 | #define IA32_MC1_STAT 0x405 | |
| 236 | #define IA32_MC1_ADDR 0x406 | |
| 237 | #define IA32_MC1_MISC 0x407 | |
| 238 | #define STAR 0xc0000081 | |
| 239 | #define LSTAR 0xc0000082 | |
| 240 | #define SYSCALL_FLAG_MASK 0xc0000084 | |
| 241 | #define X86_PAT 0x277 | |
| 242 | #define SPU_BASE 0x1C | |
| 243 | ||
| 244 | ||
| 245 | #endif /* Recursion block */ |