| 1 | /* |
| 2 | * Copyright 2010-2017 Intel Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License, version 2, |
| 6 | * as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 11 | * General Public License for more details. |
| 12 | * |
| 13 | * Disclaimer: The codes contained in these modules may be specific to |
| 14 | * the Intel Software Development Platform codenamed Knights Ferry, |
| 15 | * and the Intel product codenamed Knights Corner, and are not backward |
| 16 | * compatible with other Intel products. Additionally, Intel will NOT |
| 17 | * support the codes or instruction set in future products. |
| 18 | * |
| 19 | * Intel offers no warranty of any kind regarding the code. This code is |
| 20 | * licensed on an "AS IS" basis and Intel is not obligated to provide |
| 21 | * any support, assistance, installation, training, or other services |
| 22 | * of any kind. Intel is also not obligated to provide any updates, |
| 23 | * enhancements or extensions. Intel specifically disclaims any warranty |
| 24 | * of merchantability, non-infringement, fitness for any particular |
| 25 | * purpose, and any other warranty. |
| 26 | * |
| 27 | * Further, Intel disclaims all liability of any kind, including but |
| 28 | * not limited to liability for infringement of any proprietary rights, |
| 29 | * relating to the use of the code, even if Intel is notified of the |
| 30 | * possibility of such liability. Except as expressly stated in an Intel |
| 31 | * license agreement provided with this code and agreed upon with Intel, |
| 32 | * no license, express or implied, by estoppel or otherwise, to any |
| 33 | * intellectual property rights is granted herein. |
| 34 | */ |
| 35 | |
| 36 | /* |
| 37 | * Definition of the public MC interface. |
| 38 | * Access to MC event features provided through SCIF only. |
| 39 | */ |
| 40 | |
| 41 | #ifndef _MICMCA_API_H_ |
| 42 | #define _MICMCA_API_H_ 1 |
| 43 | |
| 44 | #ifdef __cplusplus |
| 45 | extern "C" { /* C++ guard */ |
| 46 | #endif |
| 47 | |
| 48 | /* |
| 49 | * Configuration manifests |
| 50 | */ |
| 51 | |
| 52 | #pragma pack(push, 4) /* Windows requirement */ |
| 53 | |
| 54 | |
| 55 | /* |
| 56 | * Machine check info is reported on this port. Only one consumer can |
| 57 | * (and must) connect in order to be notified about MC events. |
| 58 | */ |
| 59 | |
| 60 | #define MR_MCE_PORT SCIF_RAS_PORT_1 |
| 61 | |
| 62 | |
| 63 | /* |
| 64 | * MC events are provide in raw form, i.e. as close to the |
| 65 | * contents of MCA register banks as possible. It is not |
| 66 | * the responsibility of the MCA event handler to perform |
| 67 | * analysis and interpretation of these registers, beyond |
| 68 | * determining whether the event was deadly to the uOS. |
| 69 | * |
| 70 | * Any data or context corruption _IS_ deadly by definition! |
| 71 | * |
| 72 | * Source identifiers: |
| 73 | * org id |
| 74 | * 0 Bank 0 CPU #, core event, range 0..CPU_MAX |
| 75 | * 1 Bank 1 CPU #, core event, range 0..CPU_MAX |
| 76 | * 2 Bank 2 CPU #, core event, range 0..CPU_MAX |
| 77 | * 3 DBOX #, uncore event, range 0..DBOX_MAX |
| 78 | * 4 SBOX, uncore event, range 0 |
| 79 | * 5 GBOX #, uncore event, range 0..GBOX_MAX |
| 80 | * 6 TBOX #, uncore event, range 0..TBOX_MAX |
| 81 | * |
| 82 | * Report flags bits (when set) representing: |
| 83 | * [31:5] Unused (and reserved) |
| 84 | * [4] Filter event, uOS side disabled this event |
| 85 | * [3] Status event, no failure (just MCA bank dump) |
| 86 | * [2] Injected or artificially generated event |
| 87 | * [1] This event has been recorded in EEPROM |
| 88 | * [0] Fatal, the uOS is toast (card needs reset) |
| 89 | * |
| 90 | * MCA bank register sizes are not the same on all banks: |
| 91 | * |
| 92 | * CTL STATUS ADDR MISC Notes |
| 93 | * CPU 0: 32 64 - - A,M not implemented, always 0 |
| 94 | * CPU 1: 32 64 64 32 |
| 95 | * CPU 2: 32 64 64 - M not implemented, always 0 |
| 96 | * DBOX: 32 64 64 - M not implemented, always 0 |
| 97 | * SBOX: 32 64 64 64 |
| 98 | * GBOX: 64 64 64 32 |
| 99 | * TBOX: 64 64 32 - M not implemented, not there |
| 100 | */ |
| 101 | |
| 102 | #define MC_ORG_BNK0 0 |
| 103 | #define MC_ORG_BNK1 1 |
| 104 | #define MC_ORG_BNK2 2 |
| 105 | #define MC_ORG_DBOX 3 |
| 106 | #define MC_ORG_SBOX 4 |
| 107 | #define MC_ORG_GBOX 5 |
| 108 | #define MC_ORG_TBOX 6 |
| 109 | |
| 110 | #define MC_FLG_FATAL (1 << 0) |
| 111 | #define MC_FLG_LOG (1 << 1) |
| 112 | #define MC_FLG_FALSE (1 << 2) |
| 113 | #define MC_FLG_STATUS (1 << 3) |
| 114 | #define MC_FLG_FILTER (1 << 4) |
| 115 | |
| 116 | typedef struct mce_info { |
| 117 | uint16_t org; /* Source of event */ |
| 118 | uint16_t id; /* Identifier of source */ |
| 119 | uint16_t flags; /* Report flags */ |
| 120 | uint16_t pid; /* Alternate source ID */ |
| 121 | uint64_t stamp; /* Time stamp of event */ |
| 122 | uint64_t ctl; /* MCA bank register 'CTL' */ |
| 123 | uint64_t status; /* MCA bank register 'STATUS' */ |
| 124 | uint64_t addr; /* MCA bank register 'ADDR' */ |
| 125 | uint64_t misc; /* MCA bank register 'MISC' */ |
| 126 | } MceInfo; |
| 127 | |
| 128 | |
| 129 | #pragma pack(pop) /* Restore to entry conditions */ |
| 130 | |
| 131 | #ifdef __cplusplus |
| 132 | } /* C++ guard */ |
| 133 | #endif |
| 134 | |
| 135 | #endif /* Recursion block */ |