| 1 | /* |
| 2 | * Copyright 2010-2017 Intel Corporation. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License, version 2, |
| 6 | * as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 11 | * General Public License for more details. |
| 12 | * |
| 13 | * Disclaimer: The codes contained in these modules may be specific to |
| 14 | * the Intel Software Development Platform codenamed Knights Ferry, |
| 15 | * and the Intel product codenamed Knights Corner, and are not backward |
| 16 | * compatible with other Intel products. Additionally, Intel will NOT |
| 17 | * support the codes or instruction set in future products. |
| 18 | * |
| 19 | * Intel offers no warranty of any kind regarding the code. This code is |
| 20 | * licensed on an "AS IS" basis and Intel is not obligated to provide |
| 21 | * any support, assistance, installation, training, or other services |
| 22 | * of any kind. Intel is also not obligated to provide any updates, |
| 23 | * enhancements or extensions. Intel specifically disclaims any warranty |
| 24 | * of merchantability, non-infringement, fitness for any particular |
| 25 | * purpose, and any other warranty. |
| 26 | * |
| 27 | * Further, Intel disclaims all liability of any kind, including but |
| 28 | * not limited to liability for infringement of any proprietary rights, |
| 29 | * relating to the use of the code, even if Intel is notified of the |
| 30 | * possibility of such liability. Except as expressly stated in an Intel |
| 31 | * license agreement provided with this code and agreed upon with Intel, |
| 32 | * no license, express or implied, by estoppel or otherwise, to any |
| 33 | * intellectual property rights is granted herein. |
| 34 | */ |
| 35 | |
| 36 | /* |
| 37 | * RAS EEPROM log driver |
| 38 | * |
| 39 | * Contains code to handle creation of MC event records in |
| 40 | * the designated EEPROM hanging off the 'OverClocking' I2C bus. |
| 41 | * |
| 42 | * Since it is not clear for the moment for how long the serial |
| 43 | * port on the POST card needs to (or will) be supported, it is |
| 44 | * not safe to assume we just can tap into the Linux I2C frame |
| 45 | * work to access the 'OverClocking' I2C bus. |
| 46 | * |
| 47 | * Furthermore, we need access from exception context, and cannot |
| 48 | * run a driver that has spinlocks, mutexes and sleeps in it's path |
| 49 | * like the current PXA-derived driver has. |
| 50 | * |
| 51 | * Therefore, a local exception safe driver is included here. |
| 52 | */ |
| 53 | |
| 54 | #include <linux/types.h> |
| 55 | #include <linux/errno.h> |
| 56 | #include <linux/kernel.h> |
| 57 | #include <linux/types.h> |
| 58 | #include <linux/ctype.h> |
| 59 | #include <linux/mm.h> |
| 60 | #include <linux/mm_types.h> |
| 61 | #include <linux/io.h> |
| 62 | #include <linux/module.h> |
| 63 | #include <linux/serial_reg.h> |
| 64 | #include <linux/proc_fs.h> |
| 65 | #include <linux/seq_file.h> |
| 66 | #include <asm/uaccess.h> |
| 67 | #include <asm/mic/mic_knc/autobaseaddress.h> |
| 68 | #include <asm/mic/mic_knc/micsboxdefine.h> |
| 69 | #include "micras.h" |
| 70 | |
| 71 | #ifdef MIC_IS_EMULATION |
| 72 | /* |
| 73 | * Emulation does not handle I2C busses. |
| 74 | * Therefore all code that deals with I2C needs to be |
| 75 | * replaced with harmless substitutes in emulation. |
| 76 | * The following stubs are for emulation only. |
| 77 | */ |
| 78 | |
| 79 | #if 0 |
| 80 | /* |
| 81 | * Probably don't need exclusive locks in emulation |
| 82 | */ |
| 83 | atomic_t pxa_block = ATOMIC_INIT(0); |
| 84 | |
| 85 | static void |
| 86 | ee_lock(void) |
| 87 | { |
| 88 | while(atomic_xchg(&pxa_block, 1)) |
| 89 | myDELAY(50); |
| 90 | } |
| 91 | |
| 92 | static void |
| 93 | ee_unlock(void) |
| 94 | { |
| 95 | atomic_xchg(&pxa_block, 0); |
| 96 | } |
| 97 | #endif |
| 98 | |
| 99 | char ee_buf[EE_BUF_COUNT * EE_BUF_LINELEN]; |
| 100 | atomic_t ee_msg = ATOMIC_INIT(-1); |
| 101 | atomic_t ee_seen = ATOMIC_INIT(0); |
| 102 | int ee_rdy; |
| 103 | |
| 104 | char * |
| 105 | ee_fmt(char * fmt, va_list args) |
| 106 | { |
| 107 | char * buf; |
| 108 | int msg_id, msg_btm; |
| 109 | |
| 110 | msg_btm = atomic_read(&ee_seen); |
| 111 | msg_id = atomic_inc_return(&ee_msg); |
| 112 | if ((msg_id - msg_btm) < (EE_BUF_COUNT - 1)) { |
| 113 | buf = ee_buf + (msg_id % EE_BUF_COUNT) * EE_BUF_LINELEN; |
| 114 | vsnprintf(buf, EE_BUF_LINELEN - 1, fmt, args); |
| 115 | return buf; |
| 116 | } |
| 117 | return 0; |
| 118 | } |
| 119 | |
| 120 | int |
| 121 | ee_printk(char * fmt, ...) |
| 122 | { |
| 123 | va_list args; |
| 124 | char * buf; |
| 125 | |
| 126 | va_start(args, fmt); |
| 127 | buf = ee_fmt(fmt, args); |
| 128 | va_end(args); |
| 129 | |
| 130 | return buf ? strlen(buf) : 0; |
| 131 | } |
| 132 | |
| 133 | int |
| 134 | ee_print(char * fmt, ...) |
| 135 | { |
| 136 | va_list args; |
| 137 | char * buf; |
| 138 | |
| 139 | va_start(args, fmt); |
| 140 | buf = ee_fmt(fmt, args); |
| 141 | va_end(args); |
| 142 | |
| 143 | return buf ? strlen(buf) : 0; |
| 144 | } |
| 145 | EXPORT_SYMBOL_GPL(ee_print); |
| 146 | |
| 147 | |
| 148 | int |
| 149 | ee_init(void) |
| 150 | { |
| 151 | ee_rdy = 1; |
| 152 | |
| 153 | if (mce_disabled) |
| 154 | printk("RAS.elog (EMU): disabled\n"); |
| 155 | else |
| 156 | printk("RAS.elog (EMU): init complete\n"); |
| 157 | return 0; |
| 158 | } |
| 159 | |
| 160 | int |
| 161 | ee_exit(void) |
| 162 | { |
| 163 | ee_rdy = 0; |
| 164 | |
| 165 | printk("RAS.elog (EMU): exit complete\n"); |
| 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | void |
| 170 | micras_mc_log(struct mce_info * event) |
| 171 | { |
| 172 | if (mce_disabled) |
| 173 | return; |
| 174 | |
| 175 | /* |
| 176 | * Print entry on serial console (copy in kernel log) |
| 177 | */ |
| 178 | ee_printk("RAS.elog (EMU): bnk %d, id %d, ctl %llx, stat %llx, addr %llx, misc %llx\n", |
| 179 | event->org, event->id, event->ctl, event->status, event->addr, event->misc); |
| 180 | } |
| 181 | |
| 182 | #else |
| 183 | |
| 184 | /* |
| 185 | ** |
| 186 | ** Exception safe I2C driver for the 'OverClocking' bus. |
| 187 | ** The driver is a derivative of the FreeBSD driver that |
| 188 | ** Ben W wrote. I.e. it is safe to re-use here because we |
| 189 | ** wrote it in the first place, copyright is ours. |
| 190 | ** |
| 191 | ** NOTE: This I2C bus is usually run by the PXA driver, |
| 192 | ** which means that the activities of this driver |
| 193 | ** may interrupt the PXA driver's activity, i.e. |
| 194 | ** interrupt the serial console. |
| 195 | ** This is by design, the alternative was major |
| 196 | ** hacking of the PXA driver to support use in |
| 197 | ** exception context. |
| 198 | ** |
| 199 | ** NOTE: This code is currently exclusively designed to |
| 200 | ** run on a KnF or KnC device, i.e. we know what |
| 201 | ** hardware is present and we know the location |
| 202 | ** of the CSRs. This code does very little for |
| 203 | ** niceties like device discovery and registration. |
| 204 | ** |
| 205 | ** NOTE: Timing is altered slightly from the FreeBSD code. |
| 206 | ** The I2C bus should run in 400 kHz mode, which at |
| 207 | ** optimal conditions can transmit a byte in about |
| 208 | ** 25 uSec (8 bits + ack/nak + a little overhead). |
| 209 | ** Therefore it does not make much sense to poll |
| 210 | ** much faster than 1 uSec anywhere in this driver. |
| 211 | ** However, experiments show that timing is far |
| 212 | ** from optimal, though it is not clear whether |
| 213 | ** it is the UART or the controller that's slow. |
| 214 | ** Update: In fact some of the boards cannot run |
| 215 | ** reliably at 400 kHz, so we switched to 100 kHz. |
| 216 | */ |
| 217 | |
| 218 | #define REG_DBG 0 /* Debug I2C Layer 1 */ |
| 219 | #define I2C_DBG 0 /* Debug I2C Layer 2 */ |
| 220 | #define XFR_DBG 0 /* Debug I2C Layer 3 */ |
| 221 | #define CON_DBG 0 /* Debug I2C UART */ |
| 222 | #define EPR_DBG 0 /* Debug EEPROM log */ |
| 223 | |
| 224 | #if REG_DBG |
| 225 | #define REG_REG reg_dmp |
| 226 | #else |
| 227 | #define REG_REG(s); /* As nothing */ |
| 228 | #endif |
| 229 | |
| 230 | #if I2C_DBG |
| 231 | #define I2C_PRT ee_printk |
| 232 | #else |
| 233 | #define I2C_PRT(s,...); /* As nothing */ |
| 234 | #endif |
| 235 | |
| 236 | #if XFR_DBG |
| 237 | #define XFR_PRT ee_printk |
| 238 | #else |
| 239 | #define XFR_PRT(s,...); /* As nothing */ |
| 240 | #endif |
| 241 | |
| 242 | #if CON_DBG |
| 243 | #define CON_PRT ee_printk |
| 244 | #else |
| 245 | #define CON_PRT(s,...); /* As nothing */ |
| 246 | #endif |
| 247 | |
| 248 | #if EPR_DBG |
| 249 | #define EPR_PRT ee_printk |
| 250 | #else |
| 251 | #define EPR_PRT(s,...); /* As nothing */ |
| 252 | #endif |
| 253 | |
| 254 | |
| 255 | #include <mic/micsboxdefine.h> |
| 256 | #include "monahan.h" |
| 257 | |
| 258 | |
| 259 | /* |
| 260 | *TBD: Get rid of Pascal relics! |
| 261 | */ |
| 262 | |
| 263 | #ifndef FALSE |
| 264 | #define FALSE false |
| 265 | #endif |
| 266 | #ifndef TRUE |
| 267 | #define TRUE true |
| 268 | #endif |
| 269 | |
| 270 | |
| 271 | /* |
| 272 | * Local timer routine. |
| 273 | * Similar to the udelay function, just simpler. |
| 274 | * |
| 275 | * The delay instruction can only go upto 1023 clocks, |
| 276 | * and larger delay needs to be split into two or more |
| 277 | * delay instructions. |
| 278 | * According to Kn{F|C} errata, delay disables interrupts. |
| 279 | * Want to play nice and allow interrupts every 250 clocks. |
| 280 | * For now the overhead of the loop is ignored. |
| 281 | */ |
| 282 | |
| 283 | #define MAX_DELAY 250 |
| 284 | |
| 285 | void |
| 286 | myDELAY(uint64_t usec) |
| 287 | { |
| 288 | uint64_t num_cpu_clks, tick; |
| 289 | |
| 290 | /* |
| 291 | * Convert usec count into CPU clock cycles. |
| 292 | * Similar to set_cyc2ns_scale() we have: |
| 293 | * us = cycles / (freq / us_per_sec) |
| 294 | * us = cycles * (us_per_sec / freq) |
| 295 | * us = cycles * (10^6 / (cpu_khz * 10^3)) |
| 296 | * us = cycles * (10^3 / cpu_khz) |
| 297 | * cycles = us / ((10^3 / cpu_khz)) |
| 298 | * cycles = (us * cpu_khz) / 10^3 |
| 299 | */ |
| 300 | num_cpu_clks = (usec * tsc_khz) / 1000; |
| 301 | |
| 302 | if (num_cpu_clks <= MAX_DELAY) { |
| 303 | __asm__ __volatile__("delay %0"::"r"(num_cpu_clks):"memory"); |
| 304 | } else { |
| 305 | for(tick = MAX_DELAY; num_cpu_clks > tick; num_cpu_clks -= tick) |
| 306 | __asm__ __volatile__("delay %0"::"r"(tick):"memory"); |
| 307 | __asm__ __volatile__("delay %0"::"r"(num_cpu_clks):"memory"); |
| 308 | } |
| 309 | } |
| 310 | |
| 311 | |
| 312 | /* |
| 313 | * Layer 1 abstraction: device bus (controller register access) |
| 314 | * |
| 315 | * Access API to provide read/write to the I2C controller. |
| 316 | * Simply use a local copy of the SBOX MMIO routines, where the |
| 317 | * 'OverClocking' I2C controller CSRs starts at offset 0x1000. |
| 318 | * We use a local copy in order to not mix I2C register traces |
| 319 | * with those of the SBOX MMIO routines in micras_main.c. |
| 320 | * |
| 321 | *TBD: Shall debug features stay in the code? |
| 322 | */ |
| 323 | |
| 324 | #if REG_DBG |
| 325 | |
| 326 | /* |
| 327 | * I2C controller register dump utilities. |
| 328 | * Traces go to the kernel log. |
| 329 | */ |
| 330 | |
| 331 | struct bits { |
| 332 | uint32_t mask; |
| 333 | char *set; |
| 334 | char *unset; |
| 335 | }; |
| 336 | |
| 337 | #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } |
| 338 | |
| 339 | static struct bits icr_bits[] = { |
| 340 | PXA_BIT(ICR_START, "START", 0), |
| 341 | PXA_BIT(ICR_STOP, "STOP", 0), |
| 342 | PXA_BIT(ICR_ACKNAK, "NAK", "ACK"), |
| 343 | PXA_BIT(ICR_TB, "TB", 0), |
| 344 | PXA_BIT(ICR_MA, "MA", 0), |
| 345 | PXA_BIT(ICR_SCLE, "SCLE", 0), |
| 346 | PXA_BIT(ICR_IUE, "IUE", 0), |
| 347 | PXA_BIT(ICR_GCD, "GCD", 0), |
| 348 | PXA_BIT(ICR_ITEIE, "ITEIE", 0), |
| 349 | PXA_BIT(ICR_DRFIE, "DRFIE", 0), |
| 350 | PXA_BIT(ICR_BEIE, "BEIE", 0), |
| 351 | PXA_BIT(ICR_SSDIE, "SSDIE", 0), |
| 352 | PXA_BIT(ICR_ALDIE, "ALDIE", 0), |
| 353 | PXA_BIT(ICR_SADIE, "SADIE", 0), |
| 354 | PXA_BIT(ICR_UR, "UR", 0), |
| 355 | }; |
| 356 | |
| 357 | static struct bits isr_bits[] = { |
| 358 | PXA_BIT(ISR_RWM, "RX", "TX"), |
| 359 | PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), |
| 360 | PXA_BIT(ISR_UB, "UB", 0), |
| 361 | PXA_BIT(ISR_IBB, "IBB", 0), |
| 362 | PXA_BIT(ISR_SSD, "SSD", 0), |
| 363 | PXA_BIT(ISR_ALD, "ALD", 0), |
| 364 | PXA_BIT(ISR_ITE, "ITE", 0), |
| 365 | PXA_BIT(ISR_IRF, "IRF", 0), |
| 366 | PXA_BIT(ISR_GCAD, "GCAD", 0), |
| 367 | PXA_BIT(ISR_SAD, "SAD", 0), |
| 368 | PXA_BIT(ISR_BED, "BED", 0), |
| 369 | }; |
| 370 | |
| 371 | |
| 372 | static void |
| 373 | decode_bits(char *prefix, struct bits *bits, int num, uint32_t val) |
| 374 | { |
| 375 | char * str; |
| 376 | |
| 377 | printk(" %s: ", prefix); |
| 378 | while (num--) { |
| 379 | str = (val & bits->mask) ? bits->set : bits->unset; |
| 380 | if (str) |
| 381 | printk("%s ", str); |
| 382 | bits++; |
| 383 | } |
| 384 | } |
| 385 | |
| 386 | static void reg_ICR(uint32_t val) |
| 387 | { |
| 388 | decode_bits("ICR", icr_bits, ARRAY_SIZE(icr_bits), val); |
| 389 | printk("\n"); |
| 390 | } |
| 391 | |
| 392 | static void reg_ISR(uint32_t val) |
| 393 | { |
| 394 | decode_bits("ISR", isr_bits, ARRAY_SIZE(isr_bits), val); |
| 395 | printk("\n"); |
| 396 | } |
| 397 | |
| 398 | |
| 399 | static void |
| 400 | reg_dmp(char * str) |
| 401 | { |
| 402 | printk("%s: ICR %08x, ISR %08x, ISAR %08x, IDBR %08x, IBMR %08x\n", str, |
| 403 | mr_sbox_rl(0, SBOX_OC_I2C_ICR + ICR_OFFSET), |
| 404 | mr_sbox_rl(0, SBOX_OC_I2C_ICR + ISR_OFFSET), |
| 405 | mr_sbox_rl(0, SBOX_OC_I2C_ICR + ISAR_OFFSET), |
| 406 | mr_sbox_rl(0, SBOX_OC_I2C_ICR + IDBR_OFFSET), |
| 407 | mr_sbox_rl(0, SBOX_OC_I2C_ICR + IBMR_OFFSET)); |
| 408 | } |
| 409 | |
| 410 | #endif /* REG_DBG */ |
| 411 | |
| 412 | |
| 413 | /* |
| 414 | * Local versions of SBOX access routines, that |
| 415 | * does not leave trace messages in kernel log. |
| 416 | */ |
| 417 | |
| 418 | uint32_t |
| 419 | lmr_sbox_rl(int dummy, uint32_t roff) |
| 420 | { |
| 421 | uint32_t val; |
| 422 | |
| 423 | val = * (volatile uint32_t *)(micras_sbox + roff); |
| 424 | return val; |
| 425 | } |
| 426 | |
| 427 | void |
| 428 | lmr_sbox_wl(int dummy, uint32_t roff, uint32_t val) |
| 429 | { |
| 430 | * (volatile uint32_t *)(micras_sbox + roff) = val; |
| 431 | } |
| 432 | |
| 433 | static uint32_t |
| 434 | reg_read(uint32_t reg) |
| 435 | { |
| 436 | uint32_t val; |
| 437 | |
| 438 | val = lmr_sbox_rl(0, SBOX_OC_I2C_ICR + reg); |
| 439 | |
| 440 | #if REG_DBG |
| 441 | printk("%s: %4x -> %08x", "rd", SBOX_OC_I2C_ICR + reg, val); |
| 442 | switch(reg) { |
| 443 | case ICR_OFFSET: reg_ICR(val); break; |
| 444 | case ISR_OFFSET: reg_ISR(val); break; |
| 445 | default: |
| 446 | printk("\n"); |
| 447 | } |
| 448 | #endif |
| 449 | |
| 450 | return val; |
| 451 | } |
| 452 | |
| 453 | static void |
| 454 | reg_write(uint32_t reg, uint32_t val) |
| 455 | { |
| 456 | #if REG_DBG |
| 457 | printk("%s: %4x <- %08x", "wr", SBOX_OC_I2C_ICR + reg, val); |
| 458 | switch(reg) { |
| 459 | case ICR_OFFSET: reg_ICR(val); break; |
| 460 | default: |
| 461 | printk("\n"); |
| 462 | } |
| 463 | #endif |
| 464 | |
| 465 | lmr_sbox_wl(0, SBOX_OC_I2C_ICR + reg, val); |
| 466 | } |
| 467 | |
| 468 | |
| 469 | /* |
| 470 | * Layer 2 abstraction: I2C bus driver (byte access to I2C bus) |
| 471 | * |
| 472 | * Mostly a re-implementation of Ben W's low level FreeBSD driver. |
| 473 | * Provides an API to control what goes onto the I2C bus on a |
| 474 | * per individual byte basis. |
| 475 | * |
| 476 | * i2c_reset Reset bus controller |
| 477 | * i2c_init Setup trasaction parameters (speed & mode) |
| 478 | * i2c_start Send slave address + R/W bit |
| 479 | * i2c_rd_byte Read data byte |
| 480 | * i2c_wr_byte Send data byte |
| 481 | * i2c_stop Stop current transaction |
| 482 | * |
| 483 | * NOTE: It seems that the controller lacks means to reset the |
| 484 | * I2C bus (i.e. other devices on it). The controller |
| 485 | * resets fine, but at least the UART has been seen |
| 486 | * locking up and blocking the bus entirely. |
| 487 | */ |
| 488 | |
| 489 | static uint8_t hnd_addr = 0; /* Target address */ |
| 490 | static int hnd_freq = FREQ_100K; /* Target speed */ |
| 491 | |
| 492 | static uint8_t bus_slave_addr = ISAR_SLADDR; /* Our I2C slave address */ |
| 493 | static int bus_start_op = I2C_NOP; /* Bus command: R or W */ |
| 494 | static int bus_freq = 0; /* Bus speed (actual) */ |
| 495 | static int bus_inited = 0; /* Bus initialized */ |
| 496 | |
| 497 | |
| 498 | /* |
| 499 | * Master abort. |
| 500 | * Flip the ICR:MA bit long enough for current |
| 501 | * byte transfer to clock in/out on the wire. |
| 502 | */ |
| 503 | |
| 504 | static int |
| 505 | i2c_master_abort(void) { |
| 506 | I2C_PRT("i2c_master_abort: entry\n"); |
| 507 | |
| 508 | reg_write(ICR_OFFSET, reg_read(ICR_OFFSET) | ICR_MA); |
| 509 | myDELAY(25); |
| 510 | reg_write(ICR_OFFSET, reg_read(ICR_OFFSET) & ~ICR_MA); |
| 511 | |
| 512 | I2C_PRT("i2c_master_abort: exit\n"); |
| 513 | return 0; |
| 514 | } |
| 515 | |
| 516 | |
| 517 | /* |
| 518 | * Receive completion helper. |
| 519 | * Transmission ended (we got IRF), check if it was OK. |
| 520 | * We get ISR and whether a stop condition was expected. |
| 521 | */ |
| 522 | |
| 523 | static int |
| 524 | check_rx_isr(uint32_t isr, bool stop) |
| 525 | { |
| 526 | I2C_PRT("check_rx_isr: entry, isr %02x, stop %d\n", isr, stop); |
| 527 | REG_REG("+check_rx_isr"); |
| 528 | |
| 529 | if (stop) { |
| 530 | /* |
| 531 | * Last byte read, controller is expected to give a |
| 532 | * NAK to slave. Verify that indeed is set in ISR. |
| 533 | */ |
| 534 | if (!(isr & ISR_ACKNAK)) { |
| 535 | REG_REG("-check_rx_isr"); |
| 536 | I2C_PRT("check_rx_isr: !ISR_ACKNAK, rtn %d\n", RX_SEVERE_ERROR); |
| 537 | return RX_SEVERE_ERROR; |
| 538 | } |
| 539 | |
| 540 | /* |
| 541 | * The controller is expected to set the STOP condition. |
| 542 | * Once completed the controller clears the RWM bit of the ISR. |
| 543 | * Wait for this to happen in max 200 uSec. |
| 544 | */ |
| 545 | if (isr & ISR_RWM) { |
| 546 | int counter; |
| 547 | |
| 548 | I2C_PRT("check_rx_isr: RWM\n"); |
| 549 | counter = 100; |
| 550 | while((reg_read(ISR_OFFSET) & ISR_RWM) && --counter) |
| 551 | myDELAY(2); |
| 552 | if(! counter) { |
| 553 | REG_REG("-check_rx_isr"); |
| 554 | I2C_PRT("check_rx_isr: timeout, RWM wait %d uSec, rtn %d\n", 2 * 100, RX_BIZARRE_ERROR); |
| 555 | return RX_BIZARRE_ERROR; |
| 556 | } |
| 557 | I2C_PRT("check_rx_isr: RWM clear, waited %d uSec\n", 2 * (100 - counter)); |
| 558 | } |
| 559 | } else { |
| 560 | /* |
| 561 | * Mid-message, verify that unit is still busy, received |
| 562 | * no NAK and that message operation is still 'read'. |
| 563 | */ |
| 564 | if (!(isr & ISR_UB)) { |
| 565 | REG_REG("-check_rx_isr"); |
| 566 | I2C_PRT("check_rx_isr: !UB, rtn %d\n", RX_SEVERE_ERROR); |
| 567 | return RX_SEVERE_ERROR; |
| 568 | } |
| 569 | |
| 570 | if (isr & ISR_ACKNAK) { |
| 571 | REG_REG("-check_rx_isr"); |
| 572 | I2C_PRT("check_rx_isr: ISR_ACKNAK, rtn %d\n", RX_SEVERE_ERROR); |
| 573 | return RX_SEVERE_ERROR; |
| 574 | } |
| 575 | |
| 576 | if (!(isr & ISR_RWM)) { |
| 577 | REG_REG("-check_rx_isr"); |
| 578 | I2C_PRT("check_rx_isr: !ISR_RWM, rtn %d\n", RX_BIZARRE_ERROR); |
| 579 | return RX_BIZARRE_ERROR; |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | REG_REG("-check_rx_isr"); |
| 584 | I2C_PRT("check_rx_isr: done, rtn %d\n", XFER_SUCCESS); |
| 585 | return XFER_SUCCESS; |
| 586 | } |
| 587 | |
| 588 | /* |
| 589 | * Wait for receive completion. |
| 590 | * We get if stop condition expected. |
| 591 | */ |
| 592 | |
| 593 | static int |
| 594 | i2c_wait_rx_full(bool stop) |
| 595 | { |
| 596 | int uwt, counter, err; |
| 597 | uint32_t temp; |
| 598 | |
| 599 | I2C_PRT("i2c_wait_rx_full: entry, stop %d\n", stop); |
| 600 | REG_REG("+i2c_wait_rx_full"); |
| 601 | |
| 602 | /* |
| 603 | * Guess on how long one I2C clock cycle is (in uSec) |
| 604 | */ |
| 605 | uwt = (bus_freq == FREQ_400K) ? 3 : 10; |
| 606 | |
| 607 | /* |
| 608 | * Wait for receive to end (IRF set). |
| 609 | * Since slave can hold the SCL to reduce the speed |
| 610 | * we wait longer than we expect the receive to last. |
| 611 | */ |
| 612 | counter = 100; |
| 613 | err = INCOMPLETE_XFER; |
| 614 | while(counter) { |
| 615 | temp = reg_read(ISR_OFFSET); |
| 616 | if (temp & ISR_IRF) { |
| 617 | I2C_PRT("i2c_wait_rx_full: IRF, ISR %02x\n", temp); |
| 618 | err = check_rx_isr(temp, stop); |
| 619 | reg_write(ISR_OFFSET, reg_read(ISR_OFFSET) | ISR_IRF); |
| 620 | switch(err) { |
| 621 | case XFER_SUCCESS: |
| 622 | break; |
| 623 | case RX_SEVERE_ERROR: |
| 624 | break; |
| 625 | case RX_END_WITHOUT_STOP: |
| 626 | i2c_master_abort(); |
| 627 | break; |
| 628 | default: |
| 629 | /* |
| 630 | * This is odd/unexpected, but not |
| 631 | * something we can do anything about. |
| 632 | */ |
| 633 | err = XFER_SUCCESS; |
| 634 | } |
| 635 | break; |
| 636 | } |
| 637 | myDELAY(uwt); |
| 638 | counter--; |
| 639 | } |
| 640 | |
| 641 | REG_REG("-i2c_wait_rx_full"); |
| 642 | I2C_PRT("i2c_wait_rx_full: done, IRF wait %d uSec, err %d\n", uwt * (100 - counter), err); |
| 643 | return err; |
| 644 | } |
| 645 | |
| 646 | |
| 647 | /* |
| 648 | * Transmit completion helper. |
| 649 | * Transmission ended (we got ITE), check if it was OK. |
| 650 | * We get ISR, the current operation and whether a stop |
| 651 | * condition was expected (last byte of transmission). |
| 652 | */ |
| 653 | |
| 654 | static int |
| 655 | check_tx_isr(uint32_t isr, bool stop, int op) |
| 656 | { |
| 657 | I2C_PRT("check_tx_isr: entry, isr %02x, stop %d, op %d\n", isr, stop, op); |
| 658 | REG_REG("+check_tx_isr"); |
| 659 | |
| 660 | if (isr & ISR_BED) { /* Bus error */ |
| 661 | REG_REG("-check_tx_isr"); |
| 662 | I2C_PRT("check_tx_isr: BED, rtn %d\n", TX_NAK); |
| 663 | return TX_NAK; |
| 664 | } |
| 665 | |
| 666 | if(stop) { |
| 667 | /* |
| 668 | * Last byte write, controller expected to |
| 669 | * set the stop condition. This may take a |
| 670 | * while to complete, controller holds the |
| 671 | * UB flag of ISR until finished. |
| 672 | */ |
| 673 | if(isr & ISR_UB) { |
| 674 | int counter; |
| 675 | |
| 676 | I2C_PRT("check_rx_isr: UB\n"); |
| 677 | counter = 100; |
| 678 | while((reg_read(ISR_OFFSET) & ISR_UB) && --counter) |
| 679 | myDELAY(2); |
| 680 | if (! counter) { |
| 681 | REG_REG("-check_tx_isr"); |
| 682 | I2C_PRT("check_tx_isr: UB, timeout %d uSec, rtn %d\n", 2 * 100, TX_CONTROLLER_ERROR); |
| 683 | return TX_CONTROLLER_ERROR; |
| 684 | } |
| 685 | I2C_PRT("check_tx_isr: !UB, waited %d uSec\n", 2 * (100 - counter)); |
| 686 | } |
| 687 | } else { |
| 688 | /* |
| 689 | * Mid-message, the bus is expected to be busy. |
| 690 | */ |
| 691 | if(!(isr & ISR_UB)) { |
| 692 | REG_REG("-check_tx_isr"); |
| 693 | I2C_PRT("check_tx_isr: !UB, rtn %d\n", TX_CONTROLLER_ERROR); |
| 694 | return TX_CONTROLLER_ERROR; |
| 695 | } |
| 696 | } |
| 697 | |
| 698 | /* |
| 699 | * Assert that message operation hasn't changed |
| 700 | */ |
| 701 | if ((isr & 0x1) != op) { |
| 702 | REG_REG("-check_tx_isr"); |
| 703 | I2C_PRT("check_tx_isr: ISR %d != %d, rtn %d\n", isr & 0x1, op, TX_CONTROLLER_ERROR); |
| 704 | return TX_CONTROLLER_ERROR; |
| 705 | } |
| 706 | |
| 707 | REG_REG("-check_tx_isr"); |
| 708 | I2C_PRT("check_tx_isr: done, rtn %d\n", XFER_SUCCESS); |
| 709 | return XFER_SUCCESS; |
| 710 | } |
| 711 | |
| 712 | /* |
| 713 | * Wait for transmit completion |
| 714 | * We get the current operation and if a stop |
| 715 | * condition was expected (last byte of transmission). |
| 716 | */ |
| 717 | |
| 718 | static int |
| 719 | i2c_wait_tx_empty(bool stop, int op) |
| 720 | { |
| 721 | int counter, uwt, err; |
| 722 | uint32_t temp; |
| 723 | |
| 724 | I2C_PRT("i2c_wait_tx_empty: entry, stop %d, op %d\n", stop, op); |
| 725 | REG_REG("+i2c_wait_tx_empty"); |
| 726 | |
| 727 | /* |
| 728 | * Guess on how long one I2C clock cycle is (in uSec) |
| 729 | */ |
| 730 | uwt = (bus_freq == FREQ_400K) ? 3 : 10; |
| 731 | |
| 732 | /* |
| 733 | * Wait for transmission to end (ITE set) |
| 734 | * Since slave can hold the SCL to lower the speed |
| 735 | * we wait longer than we expect the transmission |
| 736 | * to last. |
| 737 | */ |
| 738 | counter = 100; |
| 739 | err = INCOMPLETE_XFER; |
| 740 | while(counter) { |
| 741 | temp = reg_read(ISR_OFFSET); |
| 742 | if (temp & ISR_ITE) { |
| 743 | I2C_PRT("i2c_wait_tx_empty: ITE, ISR %02x\n", temp); |
| 744 | myDELAY(uwt); |
| 745 | temp = reg_read(ISR_OFFSET); |
| 746 | err = check_tx_isr(temp, stop, op); |
| 747 | reg_write(ISR_OFFSET, reg_read(ISR_OFFSET) | ISR_ITE); |
| 748 | break; |
| 749 | } |
| 750 | myDELAY(uwt); |
| 751 | counter--; |
| 752 | } |
| 753 | |
| 754 | REG_REG("-i2c_wait_tx_empty"); |
| 755 | I2C_PRT("i2c_wait_tx_empty: done, ITE wait %d uSec, err %d\n", uwt * (100 - counter), err); |
| 756 | return err; |
| 757 | } |
| 758 | |
| 759 | |
| 760 | /* |
| 761 | * Setup for a transaction. |
| 762 | * Determine transmission speed and program ICR accordingly. |
| 763 | * Also sets ISAR, though we probably don't neeed that. |
| 764 | */ |
| 765 | |
| 766 | static int |
| 767 | i2c_init(uint8_t slave_addr) |
| 768 | { |
| 769 | uint32_t speed; |
| 770 | |
| 771 | I2C_PRT("i2c_init: entry, slave_addr %02x, hnd_speed %d\n", slave_addr, hnd_freq); |
| 772 | REG_REG("+i2c_init"); |
| 773 | |
| 774 | switch(hnd_freq) { |
| 775 | case FREQ_MAX: |
| 776 | speed = I2C_HS_FAST; |
| 777 | break; |
| 778 | case FREQ_400K: |
| 779 | speed = I2C_FAST; |
| 780 | break; |
| 781 | case FREQ_100K: |
| 782 | speed = I2C_STANDARD; |
| 783 | break; |
| 784 | case FREQ_AUTO: |
| 785 | #if I2C_SLOW |
| 786 | hnd_freq = FREQ_100K; |
| 787 | speed = I2C_STANDARD; |
| 788 | #else |
| 789 | hnd_freq = FREQ_400K; |
| 790 | speed = I2C_FAST; |
| 791 | #endif |
| 792 | break; |
| 793 | default: |
| 794 | return -EINVAL; |
| 795 | } |
| 796 | if (bus_inited && hnd_freq == bus_freq) { |
| 797 | REG_REG("-i2c_init"); |
| 798 | I2C_PRT("i2c_init: exit, bus_inited %d, hnd_freq %d\n", bus_inited, hnd_freq); |
| 799 | return 0; |
| 800 | } |
| 801 | I2C_PRT("i2c_init: speed %d, hnd_freq %d\n", bus_inited, hnd_freq); |
| 802 | |
| 803 | bus_slave_addr = ISAR_SLADDR; |
| 804 | reg_write(ISAR_OFFSET, bus_slave_addr); |
| 805 | reg_write(ICR_OFFSET, (reg_read(ICR_OFFSET) & ~ICR_MODE) | ICR_ON | speed); |
| 806 | bus_freq = hnd_freq; |
| 807 | bus_inited = 1; |
| 808 | |
| 809 | REG_REG("-i2c_init"); |
| 810 | I2C_PRT("i2c_init: done, bus_inited %d, bus_freq %d\n", bus_inited, bus_freq); |
| 811 | return 0; |
| 812 | } |
| 813 | |
| 814 | |
| 815 | /* |
| 816 | * Stop current transaction. |
| 817 | * If transmitting then do a master abort, otherwise |
| 818 | * just ensure that no new transmission starts. |
| 819 | */ |
| 820 | |
| 821 | static int |
| 822 | i2c_stop(void) |
| 823 | { |
| 824 | I2C_PRT("i2c_stop: entry, bus_inited %d, bus_start_op %d\n", bus_inited, bus_start_op); |
| 825 | REG_REG("+i2c_stop"); |
| 826 | |
| 827 | if (reg_read(ISR_OFFSET) & ISR_UB) { |
| 828 | I2C_PRT("i2c_stop: Unit busy\n"); |
| 829 | i2c_master_abort(); |
| 830 | } |
| 831 | |
| 832 | switch(bus_start_op) { |
| 833 | case I2C_WRITE: |
| 834 | I2C_PRT("i2c_stop: Stop Write\n"); |
| 835 | reg_write(ICR_OFFSET, reg_read(ICR_OFFSET) & ~(ICR_STOP | ICR_TB)); |
| 836 | break; |
| 837 | case I2C_READ: |
| 838 | I2C_PRT("i2c_stop: Stop Read\n"); |
| 839 | reg_write(ICR_OFFSET, reg_read(ICR_OFFSET) & ~(ICR_STOP | ICR_TB | ICR_ACKNAK)); |
| 840 | break; |
| 841 | } |
| 842 | bus_start_op = I2C_NOP; |
| 843 | |
| 844 | REG_REG("-i2c_stop"); |
| 845 | I2C_PRT("i2c_stop: bus_start_op %d\n", bus_start_op); |
| 846 | return 0; |
| 847 | } |
| 848 | |
| 849 | |
| 850 | /* |
| 851 | * Reset I2C controller. |
| 852 | * Try to be nice and wait for current transaction to finish |
| 853 | */ |
| 854 | |
| 855 | static int |
| 856 | i2c_reset(void) |
| 857 | { |
| 858 | I2C_PRT("i2c_reset: entry, bus_inited %d\n", bus_inited); |
| 859 | REG_REG("+i2c_reset"); |
| 860 | |
| 861 | i2c_stop(); |
| 862 | |
| 863 | reg_write(ICR_OFFSET, ICR_UR); |
| 864 | myDELAY(1); |
| 865 | reg_write(ISR_OFFSET, ~ISR_RESERVED); |
| 866 | myDELAY(1); |
| 867 | reg_write(ICR_OFFSET, 0); |
| 868 | myDELAY(1); |
| 869 | reg_write(ISAR_OFFSET, 0); |
| 870 | myDELAY(1); |
| 871 | reg_write(ICR_OFFSET, ICR_INIT_BITS); |
| 872 | bus_inited = 0; |
| 873 | |
| 874 | REG_REG("-i2c_reset"); |
| 875 | I2C_PRT("i2c_reset: exit, bus_inited %d\n", bus_inited); |
| 876 | return 0; |
| 877 | } |
| 878 | |
| 879 | |
| 880 | /* |
| 881 | * Start transaction using current setup. |
| 882 | * This is always a send of the target id and the R/W bit. |
| 883 | */ |
| 884 | |
| 885 | static int |
| 886 | i2c_start(int rw) |
| 887 | { |
| 888 | int err; |
| 889 | uint32_t temp; |
| 890 | |
| 891 | I2C_PRT("i2c_start: entry, rw %d, bus_slave_addr %02x, bus_start_op %d\n", rw, bus_slave_addr, bus_start_op); |
| 892 | REG_REG("+i2c_start"); |
| 893 | |
| 894 | if (hnd_addr == bus_slave_addr) { |
| 895 | bus_slave_addr = bus_slave_addr - 1; |
| 896 | I2C_PRT("i2c_start: reset slave %02x\n", bus_slave_addr); |
| 897 | reg_write(ISAR_OFFSET, bus_slave_addr); |
| 898 | } |
| 899 | |
| 900 | reg_write(IDBR_OFFSET, (hnd_addr << 1) | rw); |
| 901 | temp = reg_read(ICR_OFFSET); |
| 902 | temp |= ICR_START | ICR_TB; |
| 903 | temp &= ~(ICR_STOP | ICR_ALDIE); |
| 904 | reg_write(ISR_OFFSET, ~ISR_RESERVED); |
| 905 | reg_write(ICR_OFFSET, temp); |
| 906 | |
| 907 | err = i2c_wait_tx_empty(FALSE, rw); |
| 908 | if (err) { |
| 909 | i2c_reset(); |
| 910 | I2C_PRT("i2c_start: exit, err %d\n", err); |
| 911 | REG_REG("-i2c_start"); |
| 912 | return err; |
| 913 | } |
| 914 | bus_start_op = rw; |
| 915 | |
| 916 | REG_REG("-i2c_start"); |
| 917 | I2C_PRT("i2c_start: done, bus_start_op %d\n", bus_start_op); |
| 918 | return 0; |
| 919 | } |
| 920 | |
| 921 | |
| 922 | /* |
| 923 | * Read next byte of transaction |
| 924 | * Must follow a 'start' in READ mode. |
| 925 | */ |
| 926 | |
| 927 | static int |
| 928 | i2c_rd_byte(bool sendStop, uint8_t *data) |
| 929 | { |
| 930 | int retval; |
| 931 | uint32_t temp; |
| 932 | |
| 933 | I2C_PRT("i2c_rd_byte: entry, stop %d\n", sendStop); |
| 934 | |
| 935 | if (bus_start_op != I2C_READ) { |
| 936 | I2C_PRT("i2c_rd_byte: exit, called during WR\n"); |
| 937 | return -EINVAL; |
| 938 | } |
| 939 | |
| 940 | REG_REG("+i2c_rd_byte"); |
| 941 | |
| 942 | temp = reg_read(ICR_OFFSET); |
| 943 | temp |= (ICR_ALDIE | ICR_TB); |
| 944 | temp &= ~(ICR_START | ICR_STOP | ICR_ACKNAK); |
| 945 | if (sendStop) |
| 946 | temp |= ICR_STOP | ICR_ACKNAK; |
| 947 | |
| 948 | reg_write(ISR_OFFSET, ~ISR_RESERVED); |
| 949 | reg_write(ICR_OFFSET, temp); |
| 950 | retval = i2c_wait_rx_full(sendStop); |
| 951 | if (retval) { |
| 952 | REG_REG("-i2c_rd_byte"); |
| 953 | I2C_PRT("i2c_rd_byte: exit, err %d\n", retval); |
| 954 | return retval; |
| 955 | } |
| 956 | |
| 957 | temp = reg_read(IDBR_OFFSET); |
| 958 | if (data) |
| 959 | *data = temp; |
| 960 | |
| 961 | if (sendStop) |
| 962 | i2c_stop(); |
| 963 | |
| 964 | REG_REG("-i2c_rd_byte"); |
| 965 | I2C_PRT("i2c_rd_byte: done, data %02x\n", temp); |
| 966 | return 0; |
| 967 | } |
| 968 | |
| 969 | /* |
| 970 | * Write next byte of transaction |
| 971 | * Must follow a 'start' in WRITE mode. |
| 972 | */ |
| 973 | |
| 974 | static int |
| 975 | i2c_wr_byte(bool sendStop, uint8_t data) |
| 976 | { |
| 977 | int retval; |
| 978 | uint32_t temp; |
| 979 | |
| 980 | I2C_PRT("i2c_wr_byte: entry, stop %d, data %02x\n", sendStop, data); |
| 981 | |
| 982 | if (bus_start_op != I2C_WRITE) { |
| 983 | I2C_PRT("i2c_wr_byte: exit, called during RD\n"); |
| 984 | return EINVAL; |
| 985 | } |
| 986 | |
| 987 | REG_REG("+i2c_wr_byte"); |
| 988 | |
| 989 | reg_write(IDBR_OFFSET, data); |
| 990 | |
| 991 | temp = reg_read(ICR_OFFSET); |
| 992 | temp |= (ICR_ALDIE | ICR_TB); |
| 993 | temp &= ~(ICR_START | ICR_STOP); |
| 994 | if (sendStop) |
| 995 | temp |= ICR_STOP; |
| 996 | |
| 997 | reg_write(ISR_OFFSET, ~ISR_RESERVED); |
| 998 | reg_write(ICR_OFFSET, temp); |
| 999 | retval = i2c_wait_tx_empty(sendStop, I2C_WRITE); |
| 1000 | if (retval) { |
| 1001 | REG_REG("-i2c_wr_byte"); |
| 1002 | I2C_PRT("i2c_wr_byte: exit, err %d\n", retval); |
| 1003 | return retval; |
| 1004 | } |
| 1005 | |
| 1006 | if (sendStop) |
| 1007 | i2c_stop(); |
| 1008 | |
| 1009 | REG_REG("-i2c_wr_byte"); |
| 1010 | I2C_PRT("i2c_wr_byte: done\n"); |
| 1011 | return 0; |
| 1012 | } |
| 1013 | |
| 1014 | |
| 1015 | /* |
| 1016 | * Get exclusive access to the I2C bus at _any_ given time. |
| 1017 | * |
| 1018 | * If a transaction is in progress then try to complete it |
| 1019 | * in a non-destructive way. We know that the interupted |
| 1020 | * activity was from the console access to the UART, which |
| 1021 | * boils down to just two possible sequences, read UART |
| 1022 | * register or write UART register. The acting code paths is |
| 1023 | * sc16is_serial_in() |
| 1024 | * -> i2c_smbus_read_byte_data |
| 1025 | * -> i2c_smbus_xfer |
| 1026 | * -> i2c_smbus_xfer_emulated |
| 1027 | * -> i2c_transfer |
| 1028 | * -> i2c_pxa_pio_xfer |
| 1029 | * -> i2c_pxa_do_pio_xfer |
| 1030 | * -> i2c_pxa_set_master |
| 1031 | * -> i2c_pxa_start_message |
| 1032 | * -> i2c_pxa_handler (repeat for all bytes) |
| 1033 | * -> i2c_pxa_irq_txempty (on writes) |
| 1034 | * -> i2c_pxa_irq_rxfull (on reads) |
| 1035 | * -> i2c_pxa_stop_message |
| 1036 | * |
| 1037 | * Function i2c_pxa_handler (designed as an interrupt handler) |
| 1038 | * is polled every 10 uSec, which is pretty fast for a line that |
| 1039 | * clocks at 400 kHz (minimum 20 uSec to send one byte). |
| 1040 | * |
| 1041 | * The two sequences on the I2C bus for the UART are: |
| 1042 | * |
| 1043 | * Write: S <addr | W> A <reg> A <data byte> A P |
| 1044 | * Read: S <addr | W> A <reg> A Sr <addr | R> A <data byte> A P |
| 1045 | * |
| 1046 | * where |
| 1047 | * S Start sequence |
| 1048 | * P Stop sequence |
| 1049 | * Sr Repeated start |
| 1050 | * W Write flag |
| 1051 | * R Read flag |
| 1052 | * A Ack (send or recv) |
| 1053 | * |
| 1054 | * We need the abilitity to 'borrow' the I2C bus from the PXA driver |
| 1055 | * both when it is running (say on another CPU) or when it has been |
| 1056 | * interrupted (NMI and Exception context). |
| 1057 | * |
| 1058 | * From trackers in the PXA driver we get to know the current state |
| 1059 | * of the I2C transaction with the following granularity: |
| 1060 | * |
| 1061 | * '-' Idle |
| 1062 | * 'B' Waiting for bus free |
| 1063 | * 'I' Initiating transfer (i.e. send addr & direction flag) |
| 1064 | * 'S' Sending byte |
| 1065 | * 'R' Receving byte |
| 1066 | * |
| 1067 | * Last byte of the transaction can be identified by the STOP flag. |
| 1068 | * |
| 1069 | * The take-over sequence starts by setting an atomic variable which |
| 1070 | * tells the PXA driver to wait (and retry the I2C transaction when |
| 1071 | * the variable gets cleared). Then we look at the controller status |
| 1072 | * and command registers to determine whether it is active or not. |
| 1073 | * |
| 1074 | * Simple cases: |
| 1075 | * ------------- |
| 1076 | * state = '-' |
| 1077 | * Controller is not in use by PXA driver. |
| 1078 | * |
| 1079 | * state 'B' |
| 1080 | * Controller not actively in use yet. |
| 1081 | * At worst the SCLE bit will be set, which won't affect |
| 1082 | * anything in this driver since we always run as master. |
| 1083 | * |
| 1084 | * STOP bit set |
| 1085 | * This is last byte of a transaction, we have two cases: |
| 1086 | * a) Last part of a write UART register transaction. |
| 1087 | * - Wait for the byte to clock out |
| 1088 | * b) Last part of a read UART register transaction. |
| 1089 | * - Wait for the byte to clock in, then preserve IDBR. |
| 1090 | * |
| 1091 | * Other cases: |
| 1092 | * ------------ |
| 1093 | * state 'I' |
| 1094 | * Starting an I2C command (Start or Start-Repeat), |
| 1095 | * we have 3 sub-cases of this: |
| 1096 | * a) Starting a write UART register transaction: |
| 1097 | * - Wait for the byte to clock out, then transmit a |
| 1098 | * 0 byte with STOP bit set. This selects RX/TX |
| 1099 | * UART register without accessing it. |
| 1100 | * b) Starting a read UART register transaction: |
| 1101 | * - Same as case a), turn it into a NOP. |
| 1102 | * c) Reversing direction during read UART register, |
| 1103 | * probably need to finish the read operation: |
| 1104 | * - Wait for the byte to clock out, send STOP + ACK |
| 1105 | * and wait for the receive to clock in. |
| 1106 | * |
| 1107 | * state 'S' |
| 1108 | * Since STOP bit is not set, then this is the <reg> |
| 1109 | * index being transfered, two sub-cases: |
| 1110 | * a) Sending <reg> of a write UART register. |
| 1111 | * - Wait for the byte to clock out, then transmit a |
| 1112 | * 0 byte with the STOP bit set. This inadvertantly |
| 1113 | * and temporarily clears a random UART register, |
| 1114 | * which may result in a null byte transmitted |
| 1115 | * Since there is a retry associated, the intended |
| 1116 | * register value will be written later. |
| 1117 | * b) Sending <reg> of a read UART register. |
| 1118 | * - Same as state 'I' case c). |
| 1119 | * |
| 1120 | * state 'R' |
| 1121 | * Should not occur, because communications with the |
| 1122 | * UART only have single byte reads, which always is |
| 1123 | * accompanied by a STOP bit, and thus is covered by |
| 1124 | * the simple case above. If multi-byte reads were to |
| 1125 | * be used then we'd have to terminate it: |
| 1126 | * - Wait for the byte to clock in, send STOP + ACK |
| 1127 | * and wait for the 2nd byte to clock in. |
| 1128 | * Both bytes received can be discarded, as there |
| 1129 | * is no easy way to pass them to the PXA driver. |
| 1130 | * |
| 1131 | * Warning: |
| 1132 | * Beyond this being an ugly hack, it is also not re-entrant. |
| 1133 | * It can reliably interrupt the console and return it without |
| 1134 | * causing too much breakage, but it cannot grab the I2C bus |
| 1135 | * from itself due to the use of global variables. |
| 1136 | * |
| 1137 | * Warning: |
| 1138 | * The synchronization between i2c_grap/i2c_release and the |
| 1139 | * PXA driver can still wreck the I2C controller. Cause not |
| 1140 | * known, but when it happens the PXA driver ends up repeating |
| 1141 | * these log messages: |
| 1142 | * i2c: error: pxa_pio_set_master: timeout |
| 1143 | * i2c: msg_num: 0 msg_idx: 1 msg_ptr: 0 |
| 1144 | * i2c: ICR: 000017e0 ISR: 00000044 |
| 1145 | * i2c: log: [000000c6:000017e0:00:9a] |
| 1146 | * i2c i2c-0: i2c_pxa: timeout waiting for bus free |
| 1147 | * pxa_do_pio_xfer: timeout to become master |
| 1148 | * pxa_pio_set_master 'B': ISR 00044, ICR 7e0, IDBR 28, IBMR 1 |
| 1149 | * Looks like the I2C controller gets stuck, ISR: IRF + IBB, |
| 1150 | * The code failing is i2c_pxa_pio_set_master(), which points |
| 1151 | * to the I2C UART as the culprit. One such case was during |
| 1152 | * module load on KnF, where the only activity in the module |
| 1153 | * was one ee_lock/ee_release pair, which in state 'B' should |
| 1154 | * be straight forward to handle. |
| 1155 | */ |
| 1156 | |
| 1157 | #ifdef CONFIG_I2C_PXA |
| 1158 | #define PXA_SYNC 1 |
| 1159 | #else |
| 1160 | #define PXA_SYNC 0 |
| 1161 | #endif |
| 1162 | |
| 1163 | #if PXA_SYNC |
| 1164 | static uint32_t sv_icr, sv_isr, sv_isar, sv_idbr, ee_term; |
| 1165 | extern char pxa_state; |
| 1166 | extern atomic_t pxa_block; |
| 1167 | #endif |
| 1168 | |
| 1169 | static void |
| 1170 | i2c_grab(void) |
| 1171 | { |
| 1172 | int uwt, n; |
| 1173 | uint32_t icr, isr; |
| 1174 | char * w; |
| 1175 | |
| 1176 | I2C_PRT("i2c_grab: entry\n"); |
| 1177 | REG_REG("+i2c_grab"); |
| 1178 | |
| 1179 | #if PXA_SYNC |
| 1180 | sv_isar = reg_read(ISAR_OFFSET); |
| 1181 | sv_idbr = reg_read(IDBR_OFFSET); |
| 1182 | sv_icr = reg_read(ICR_OFFSET); |
| 1183 | isr = sv_isr = reg_read(ISR_OFFSET); |
| 1184 | if ((pxa_state == '-' || pxa_state == 'B') && !(isr & ISR_UB)) { |
| 1185 | REG_REG("-i2c_grab"); |
| 1186 | I2C_PRT("i2c_grab: controller idle, isr %08x\n", isr); |
| 1187 | return; |
| 1188 | } |
| 1189 | ee_term = 1; |
| 1190 | I2C_PRT("i2c_grab: controller active, pxa %c\n", pxa_state); |
| 1191 | #else |
| 1192 | isr = reg_read(ISR_OFFSET); |
| 1193 | if (!(isr & ISR_UB)) { |
| 1194 | REG_REG("-i2c_grab"); |
| 1195 | I2C_PRT("i2c_grab: controller idle, isr %08x\n", isr); |
| 1196 | return; |
| 1197 | } |
| 1198 | I2C_PRT("i2c_grab: controller active\n"); |
| 1199 | w = "-"; |
| 1200 | #endif |
| 1201 | |
| 1202 | /* |
| 1203 | * Guess on how long one I2C clock cycle is (in uSec) |
| 1204 | * Note: ignore High-Speed modes, they are not used. |
| 1205 | */ |
| 1206 | icr = reg_read(ICR_OFFSET); |
| 1207 | uwt = (icr & ICR_FAST_MODE) ? 3 : 10; |
| 1208 | |
| 1209 | /* |
| 1210 | * Wait here long enough that current byte transaction |
| 1211 | * on the I2C controller must have clocked all on its bus. |
| 1212 | * Imperically, we've determined that length of this wait |
| 1213 | * can to be in range up to a dozen I2C clocks. |
| 1214 | * We probe state once per I2C clock cycle. |
| 1215 | */ |
| 1216 | for(n = 0; n < 100 && (isr & ISR_UB); n++) { |
| 1217 | /* |
| 1218 | * Controller busy doing something. Whatever it is |
| 1219 | * doing, it should set either ITE or IRF when done. |
| 1220 | * Need to check for this independently because UB |
| 1221 | * is asserted all the way from START thru STOP. |
| 1222 | */ |
| 1223 | if (isr & (ISR_ITE | ISR_IRF)) |
| 1224 | break; |
| 1225 | myDELAY(uwt); |
| 1226 | isr = reg_read(ISR_OFFSET); |
| 1227 | } |
| 1228 | I2C_PRT("i2c_grab: ITE/IRF wait %d uSec, isr %02x, UB %d\n", |
| 1229 | n * uwt, isr, (isr & ISR_UB) == ISR_UB); |
| 1230 | |
| 1231 | /* |
| 1232 | * Controller should have finished current byte transfer by now. |
| 1233 | * If it was last byte of a transaction, we are done. |
| 1234 | * In read mode we preserve the received data. |
| 1235 | */ |
| 1236 | if (icr & ICR_STOP) { |
| 1237 | #if PXA_SYNC |
| 1238 | if (isr & ISR_RWM) |
| 1239 | sv_idbr = reg_read(IDBR_OFFSET); |
| 1240 | #endif |
| 1241 | for(n = 0; n < 100 && (isr & ISR_UB); n++) { |
| 1242 | myDELAY(uwt); |
| 1243 | isr = reg_read(ISR_OFFSET); |
| 1244 | } |
| 1245 | |
| 1246 | REG_REG("-i2c_grab"); |
| 1247 | I2C_PRT("i2c_grab: easy case, UB wait %d uSec, bus %sclear, icr %08x, isr %08x\n", |
| 1248 | n * uwt, (isr & ISR_UB) ? "NOT " : "", icr, isr); |
| 1249 | return; |
| 1250 | } |
| 1251 | |
| 1252 | #if PXA_SYNC |
| 1253 | w = "?"; |
| 1254 | |
| 1255 | if (pxa_state == 'I') { |
| 1256 | isr &= ~ISR_INTS; |
| 1257 | reg_write(ISR_OFFSET, isr); |
| 1258 | |
| 1259 | if (isr & ISR_RWM) { |
| 1260 | /* |
| 1261 | * Sub-case c) |
| 1262 | * Start byte read and send nak+stop when received. |
| 1263 | */ |
| 1264 | I2C_PRT("i2c_grab: state 'I', sub-case c\n"); |
| 1265 | icr = (icr & ~ICR_START) | (ICR_STOP | ICR_ACKNAK | ICR_TB); |
| 1266 | reg_write(ICR_OFFSET, icr); |
| 1267 | w = "c"; |
| 1268 | } |
| 1269 | else { |
| 1270 | /* |
| 1271 | * Sub-case a) and b) |
| 1272 | * Send a null byte and stop the transaction. |
| 1273 | */ |
| 1274 | I2C_PRT("i2c_grab: state 'I', sub-case a & b\n"); |
| 1275 | icr = (icr & ~ICR_START) | (ICR_STOP | ICR_TB); |
| 1276 | reg_write(IDBR_OFFSET, 0); |
| 1277 | reg_write(ICR_OFFSET, icr); |
| 1278 | w = "a & b"; |
| 1279 | } |
| 1280 | |
| 1281 | myDELAY(8 * uwt); |
| 1282 | isr = reg_read(ISR_OFFSET); |
| 1283 | for(n = 0; n < 100 && (isr & ISR_UB); n++) { |
| 1284 | myDELAY(uwt); |
| 1285 | isr = reg_read(ISR_OFFSET); |
| 1286 | } |
| 1287 | if (*w == 'c') |
| 1288 | sv_idbr = reg_read(IDBR_OFFSET); |
| 1289 | } |
| 1290 | |
| 1291 | if (pxa_state == 'S') { |
| 1292 | isr &= ~ISR_INTS; |
| 1293 | reg_write(ISR_OFFSET, isr); |
| 1294 | |
| 1295 | if (isr & ISR_RWM) { |
| 1296 | I2C_PRT("i2c_grab: state 'S', sub-case b\n"); |
| 1297 | icr = (icr & ~ICR_START) | (ICR_STOP | ICR_ACKNAK | ICR_TB); |
| 1298 | reg_write(ICR_OFFSET, icr); |
| 1299 | w = "b"; |
| 1300 | } |
| 1301 | else { |
| 1302 | I2C_PRT("i2c_grab: state 'S', sub-case a\n"); |
| 1303 | icr = (icr & ~ICR_START) | (ICR_STOP | ICR_TB); |
| 1304 | reg_write(IDBR_OFFSET, 0); |
| 1305 | reg_write(ICR_OFFSET, icr); |
| 1306 | w = "a"; |
| 1307 | } |
| 1308 | |
| 1309 | myDELAY(8 * uwt); |
| 1310 | isr = reg_read(ISR_OFFSET); |
| 1311 | for(n = 0; n < 100 && (isr & ISR_UB); n++) { |
| 1312 | myDELAY(uwt); |
| 1313 | isr = reg_read(ISR_OFFSET); |
| 1314 | } |
| 1315 | if (*w == 'b') |
| 1316 | sv_idbr = reg_read(IDBR_OFFSET); |
| 1317 | } |
| 1318 | #endif /* PXA_SYNC */ |
| 1319 | |
| 1320 | REG_REG("-i2c_grab"); |
| 1321 | I2C_PRT("i2c_grab: controller %sclear, icr %08x, isr %08x, w %s\n", |
| 1322 | (isr & ISR_UB) ? "NOT " : "", icr, isr, w); |
| 1323 | } |
| 1324 | |
| 1325 | static void |
| 1326 | i2c_release(void) |
| 1327 | { |
| 1328 | I2C_PRT("i2c_release: entry\n"); |
| 1329 | REG_REG("+i2c_release"); |
| 1330 | |
| 1331 | #if PXA_SYNC |
| 1332 | #if 0 |
| 1333 | /* |
| 1334 | * Reset I2C controller before returning it to PXA driver |
| 1335 | *TBD: Usually not necessary, remove? |
| 1336 | */ |
| 1337 | if (ee_term) { |
| 1338 | I2C_PRT("i2c_release: resetting bus\n"); |
| 1339 | reg_write(ICR_OFFSET, ICR_UR); |
| 1340 | myDELAY(2); |
| 1341 | reg_write(ICR_OFFSET, 0); |
| 1342 | } |
| 1343 | #endif |
| 1344 | |
| 1345 | I2C_PRT("i2c_release: restore controller state\n"); |
| 1346 | reg_write(ISR_OFFSET, sv_isr); |
| 1347 | reg_write(ICR_OFFSET, sv_icr & ~ICR_TB); |
| 1348 | reg_write(ISAR_OFFSET, sv_isar); |
| 1349 | reg_write(IDBR_OFFSET, sv_idbr); |
| 1350 | |
| 1351 | if (ee_term) |
| 1352 | ee_term = 0; |
| 1353 | #endif /* PXA_SYNC */ |
| 1354 | |
| 1355 | if (reg_read(IBMR_OFFSET) != 3) |
| 1356 | I2C_PRT("i2c_release: WARNING: bus active!!!\n"); |
| 1357 | |
| 1358 | REG_REG("-i2c_release"); |
| 1359 | I2C_PRT("i2c_release: exit\n"); |
| 1360 | } |
| 1361 | |
| 1362 | |
| 1363 | /* |
| 1364 | * Layer 3 abstraction: I2C driver API (message passing). |
| 1365 | * |
| 1366 | * Controls data transfers to/from devices on the I2C bus. |
| 1367 | * This is what device drivers should use. |
| 1368 | * |
| 1369 | * xfr_configure Set target address and speed |
| 1370 | * xfr_start Start R/W operation |
| 1371 | * xfr_write Write buffer to target |
| 1372 | * xfr_read Read buffer from target |
| 1373 | * xfr_rept_start Repeat-start new R/W operation |
| 1374 | * xfr_reset Reset driver |
| 1375 | */ |
| 1376 | |
| 1377 | static int |
| 1378 | xfr_configure(uint8_t addr, int freq) |
| 1379 | { |
| 1380 | XFR_PRT("xfr_configure: entry, addr %02x, freq %d\n", addr, freq); |
| 1381 | |
| 1382 | if (freq > FREQ_AUTO || freq <= FREQ_MAX) { |
| 1383 | XFR_PRT("xfr_configure: exit, invalid freq\n"); |
| 1384 | return -EINVAL; |
| 1385 | } |
| 1386 | |
| 1387 | if (addr & 0x80) { |
| 1388 | XFR_PRT("xfr_configure: exit, invalid addr\n"); |
| 1389 | return -EINVAL; |
| 1390 | } |
| 1391 | |
| 1392 | hnd_addr = addr; |
| 1393 | hnd_freq = freq; |
| 1394 | XFR_PRT("xfr_configure: done, hnd_addr %02x, hnd_freq %d\n", hnd_addr, hnd_freq); |
| 1395 | return 0; |
| 1396 | } |
| 1397 | |
| 1398 | |
| 1399 | static int |
| 1400 | xfr_start(int rw) |
| 1401 | { |
| 1402 | int err; |
| 1403 | |
| 1404 | XFR_PRT("xfr_start: entry, rw %d, hnd_addr %02x\n", rw, hnd_addr); |
| 1405 | |
| 1406 | if (rw != I2C_WRITE && rw != I2C_READ) { |
| 1407 | XFR_PRT("xfr_start: exit, op invalid\n"); |
| 1408 | return -EINVAL; |
| 1409 | } |
| 1410 | |
| 1411 | if (hnd_addr & 0x80) { |
| 1412 | XFR_PRT("xfr_start: exit, hnd_addr %02x invalid\n", hnd_addr); |
| 1413 | return -EINVAL; |
| 1414 | } |
| 1415 | |
| 1416 | err = i2c_init(hnd_addr); |
| 1417 | if (err) { |
| 1418 | XFR_PRT("xfr_start: i2c_init failed, err %d\n", err); |
| 1419 | i2c_reset(); |
| 1420 | return -EIO; |
| 1421 | } |
| 1422 | |
| 1423 | err = i2c_start(rw); |
| 1424 | if (err) |
| 1425 | XFR_PRT("xfr_start: i2c_start failed, err %d\n", err); |
| 1426 | switch(err) { |
| 1427 | case INCOMPLETE_XFER: |
| 1428 | i2c_stop(); |
| 1429 | err = -EBUSY; |
| 1430 | break; |
| 1431 | case TX_CONTROLLER_ERROR: |
| 1432 | i2c_reset(); |
| 1433 | err = -ENODEV; |
| 1434 | break; |
| 1435 | case TX_NAK: |
| 1436 | i2c_stop(); |
| 1437 | err = -ENXIO; |
| 1438 | break; |
| 1439 | } |
| 1440 | |
| 1441 | XFR_PRT("xfr_start: done, err %d\n", err); |
| 1442 | return err; |
| 1443 | } |
| 1444 | |
| 1445 | |
| 1446 | static int |
| 1447 | xfr_rept_start(int rw) |
| 1448 | { |
| 1449 | int err; |
| 1450 | |
| 1451 | XFR_PRT("xfr_rept_start: entry, rw %d, bus_start_op %d\n", rw, bus_start_op); |
| 1452 | |
| 1453 | if (bus_start_op != I2C_READ && bus_start_op != I2C_WRITE) { |
| 1454 | XFR_PRT("xfr_rept_start: exit, mode change %d\n", -ENXIO); |
| 1455 | return -ENXIO; |
| 1456 | } |
| 1457 | |
| 1458 | err = i2c_start(rw); |
| 1459 | if (err) |
| 1460 | XFR_PRT("xfr_rept_start: i2c_start err %d\n", err); |
| 1461 | switch(err) { |
| 1462 | case INCOMPLETE_XFER: |
| 1463 | i2c_stop(); |
| 1464 | err = -EBUSY; |
| 1465 | break; |
| 1466 | case TX_CONTROLLER_ERROR: |
| 1467 | i2c_reset(); |
| 1468 | err = -ENODEV; |
| 1469 | break; |
| 1470 | case TX_NAK: |
| 1471 | i2c_stop(); |
| 1472 | err = -ENXIO; |
| 1473 | break; |
| 1474 | } |
| 1475 | |
| 1476 | XFR_PRT("xfr_rept_start: done, err %d\n", err); |
| 1477 | return err; |
| 1478 | } |
| 1479 | |
| 1480 | |
| 1481 | static int |
| 1482 | xfr_write(bool sendStop, int cnt, uint8_t *data) |
| 1483 | { |
| 1484 | int retval, i; |
| 1485 | |
| 1486 | XFR_PRT("xfr_write: entry, sendStop %d, cnt %d\n", sendStop, cnt); |
| 1487 | |
| 1488 | if (cnt < 0) { |
| 1489 | XFR_PRT("xfr_write: exit, bad count %d\n", cnt); |
| 1490 | return -EINVAL; |
| 1491 | } |
| 1492 | |
| 1493 | if (! cnt) { |
| 1494 | XFR_PRT("xfr_write: null write\n"); |
| 1495 | retval = i2c_stop(); |
| 1496 | goto out; |
| 1497 | } |
| 1498 | |
| 1499 | if (cnt == 1) { |
| 1500 | XFR_PRT("xfr_write: 1-byte write, '%02x'\n", *data); |
| 1501 | retval = i2c_wr_byte(sendStop, *data); |
| 1502 | goto out; |
| 1503 | } |
| 1504 | |
| 1505 | for (i = 0; i < cnt - 1; i++) { |
| 1506 | XFR_PRT("xfr_write: multi-byte write %d, '%02x'\n", i, data[i]); |
| 1507 | retval = i2c_wr_byte(FALSE, data[i]); |
| 1508 | if (retval) |
| 1509 | goto out; |
| 1510 | } |
| 1511 | |
| 1512 | XFR_PRT("xfr_write: last of multi-byte write %d, '%02x'\n", cnt - 1, data[cnt - 1]); |
| 1513 | retval = i2c_wr_byte(sendStop, data[cnt - 1]); |
| 1514 | |
| 1515 | out: |
| 1516 | if (retval) |
| 1517 | XFR_PRT("xfr_write: post val %d\n", retval); |
| 1518 | switch(retval) { |
| 1519 | case INCOMPLETE_XFER: |
| 1520 | i2c_stop(); |
| 1521 | retval = -EBUSY; |
| 1522 | break; |
| 1523 | case TX_CONTROLLER_ERROR: |
| 1524 | i2c_reset(); |
| 1525 | retval = -ENODEV; |
| 1526 | break; |
| 1527 | case TX_NAK: |
| 1528 | i2c_stop(); |
| 1529 | retval = -ENXIO; |
| 1530 | break; |
| 1531 | } |
| 1532 | |
| 1533 | XFR_PRT("xfr_write: done, val %d\n", retval); |
| 1534 | return retval; |
| 1535 | } |
| 1536 | |
| 1537 | |
| 1538 | static int |
| 1539 | xfr_read(bool sendStop, int cnt, uint8_t *data) |
| 1540 | { |
| 1541 | int retval, i; |
| 1542 | |
| 1543 | XFR_PRT("xfr_read: entry, stop %d, cnt %d\n", sendStop, cnt); |
| 1544 | |
| 1545 | if (cnt < 0) { |
| 1546 | XFR_PRT("xfr_read: exit, bad count %d\n", cnt); |
| 1547 | return -EINVAL; |
| 1548 | } |
| 1549 | |
| 1550 | if (! cnt) { |
| 1551 | XFR_PRT("xfr_read: null read\n"); |
| 1552 | retval = i2c_stop(); |
| 1553 | goto out; |
| 1554 | } |
| 1555 | |
| 1556 | if (cnt == 1) { |
| 1557 | XFR_PRT("xfr_read: 1-byte read\n"); |
| 1558 | retval = i2c_rd_byte(sendStop, data); |
| 1559 | goto out; |
| 1560 | } |
| 1561 | |
| 1562 | for (i = 0; i < cnt - 1; i++) { |
| 1563 | XFR_PRT("xfr_read: multi-byte read %d\n", i); |
| 1564 | retval = i2c_rd_byte(FALSE, data ? &data[i] : data); |
| 1565 | if (retval) |
| 1566 | goto out; |
| 1567 | } |
| 1568 | |
| 1569 | XFR_PRT("xfr_read: last of multi-byte read %d\n", cnt - 1); |
| 1570 | retval = i2c_rd_byte(sendStop, data ? &data[cnt - 1] : data); |
| 1571 | |
| 1572 | out: |
| 1573 | if (retval) { |
| 1574 | XFR_PRT("xfr_read: post val %d\n", retval); |
| 1575 | i2c_reset(); |
| 1576 | retval = -ENXIO; |
| 1577 | } |
| 1578 | |
| 1579 | XFR_PRT("xfr_read: done, err %d\n", retval); |
| 1580 | return retval; |
| 1581 | } |
| 1582 | |
| 1583 | |
| 1584 | #if NOT_YET |
| 1585 | static void |
| 1586 | xfr_reset(void) |
| 1587 | { |
| 1588 | i2c_reset(); |
| 1589 | } |
| 1590 | #endif |
| 1591 | |
| 1592 | |
| 1593 | |
| 1594 | /* |
| 1595 | ** |
| 1596 | ** UART support for printing from exception context. |
| 1597 | ** A somewhat crude implementation of two low level |
| 1598 | ** routines that write/read CSRs on the I2C UART. |
| 1599 | ** On top of these two functions, a set of mid-layer |
| 1600 | ** routines adds init/exit and character based I/O. |
| 1601 | ** We try not to alter the UART's transmission setup |
| 1602 | ** in order lower the risk of corrupting normal use. |
| 1603 | ** |
| 1604 | ** All UART support routines assume I2C controller |
| 1605 | ** to be initialized by xfr_configure() and expects |
| 1606 | ** exclusive access to the device |
| 1607 | ** |
| 1608 | */ |
| 1609 | |
| 1610 | |
| 1611 | /* |
| 1612 | * Weird way to say that the I2C UART has slave address |
| 1613 | * 0x4D (or 0x48) and the UART registers are in bits |
| 1614 | * [6:3] of the register address byte. |
| 1615 | * KnF has both I2C UART address pins wired to Vss. |
| 1616 | * KnC MPI has the address pins wired to Vdd instead. |
| 1617 | *TBD: That's according to the schematics, in reality |
| 1618 | * on A0 CRBs the address of the onboard UART is |
| 1619 | * 0x4D, which matches address pins wired to Vss. |
| 1620 | * Not sure why that changed. |
| 1621 | */ |
| 1622 | |
| 1623 | #ifdef CONFIG_ML1OM |
| 1624 | #define SC16IS_ADDR_0 1 |
| 1625 | #define SC16IS_ADDR_1 1 |
| 1626 | #endif |
| 1627 | #ifdef CONFIG_MK1OM /* KAA: MPI specific or KnC specific ? */ |
| 1628 | #define SC16IS_ADDR_0 1 |
| 1629 | #define SC16IS_ADDR_1 1 |
| 1630 | #endif |
| 1631 | #define SC16IS_ADDR(a1, a0) \ |
| 1632 | (0x40 | (((a1 + 8) + (a1 * 3)) | a0)) |
| 1633 | #define SC16IS_SUBADDR(addr, ch) \ |
| 1634 | ((addr & 0xf) << 3) | ((ch & 3) << 1) |
| 1635 | |
| 1636 | |
| 1637 | static uint8_t |
| 1638 | cons_getreg(int reg) |
| 1639 | { |
| 1640 | uint8_t sub, val; |
| 1641 | int err; |
| 1642 | |
| 1643 | CON_PRT("cons_getreg: reg %02x\n", reg); |
| 1644 | |
| 1645 | /* |
| 1646 | * The SC16IS740 device reads 8-bit UART registers |
| 1647 | * by first writing the register index and then in |
| 1648 | * an subsequent read operation gets the register |
| 1649 | * value. The two operations can (and probably |
| 1650 | * should) be joined by a repeated start to save |
| 1651 | * the intermediate stop signaling. |
| 1652 | */ |
| 1653 | val = 0; |
| 1654 | sub = (uint8_t) SC16IS_SUBADDR(reg, 0); |
| 1655 | err = xfr_start(I2C_WRITE); |
| 1656 | if (err) { |
| 1657 | CON_PRT("cons_getreg: xfr_start (WR) err %d\n", err); |
| 1658 | return 0; |
| 1659 | } |
| 1660 | err = xfr_write(FALSE, 1, &sub); |
| 1661 | if (err) { |
| 1662 | CON_PRT("cons_getreg: xfr_write (%02x) err %d\n", sub, err); |
| 1663 | return 0; |
| 1664 | } |
| 1665 | err = xfr_rept_start(I2C_READ); |
| 1666 | if (err) { |
| 1667 | CON_PRT("cons_getreg: xfr_rept_start (RD) err %d\n", err); |
| 1668 | return 0; |
| 1669 | } |
| 1670 | err = xfr_read(TRUE, 1, &val); |
| 1671 | if (err) { |
| 1672 | CON_PRT("cons_getreg: xfr_read err %d\n", err); |
| 1673 | return 0; |
| 1674 | } |
| 1675 | |
| 1676 | CON_PRT("cons_getreg: reg %02x, val %02x\n", reg, val); |
| 1677 | return val; |
| 1678 | } |
| 1679 | |
| 1680 | |
| 1681 | static void |
| 1682 | cons_setreg(int reg, int val) |
| 1683 | { |
| 1684 | uint8_t payload[2]; |
| 1685 | int err; |
| 1686 | |
| 1687 | CON_PRT("cons_setreg: reg %02x, val %02x\n", reg, val); |
| 1688 | |
| 1689 | payload[0] = (uint8_t) SC16IS_SUBADDR(reg, 0); |
| 1690 | payload[1] = (uint8_t) val; |
| 1691 | CON_PRT("cons_setreg: I2C payload %02x, %02x\n", payload[0], payload[1]); |
| 1692 | err = xfr_start(I2C_WRITE); |
| 1693 | if (err) { |
| 1694 | CON_PRT("cons_setreg: xfr_start (WR) err %d\n", err); |
| 1695 | return; |
| 1696 | } |
| 1697 | err = xfr_write(TRUE, 2, payload); |
| 1698 | if (err) |
| 1699 | CON_PRT("cons_getreg: xfr_write (%02x, %02x) err %d\n", payload[0], payload[1], err); |
| 1700 | } |
| 1701 | |
| 1702 | |
| 1703 | static void |
| 1704 | cons_init(void) |
| 1705 | { |
| 1706 | /* |
| 1707 | * For now assume that the kernel LXA driver or the |
| 1708 | * bootstrap code has setup the I2C uart properly, i.e. |
| 1709 | * we don't need to alter speed/databits/stopbits/parity |
| 1710 | * or any other serial properties. |
| 1711 | * |
| 1712 | *WARNING: Since the switch of console from the I2C uart to |
| 1713 | * the virtual console, the uart is left with default |
| 1714 | * serial port speed of 9600 baud. Bootstrap blasts |
| 1715 | * it's messages at 115200 baud, so now the choice |
| 1716 | * of getting garbage from this routine or from the |
| 1717 | * bootstrap. Using program stty from userspace may |
| 1718 | * set any baudrate, we cannot override it here! |
| 1719 | * # stty 115200 < /dev/ttyS0 |
| 1720 | *TBD: make 115200 baud default on I2C uart! |
| 1721 | */ |
| 1722 | CON_PRT("cons_init: pass\n"); |
| 1723 | } |
| 1724 | |
| 1725 | |
| 1726 | static void |
| 1727 | cons_exit(void) |
| 1728 | { |
| 1729 | CON_PRT("cons_exit: pass\n"); |
| 1730 | } |
| 1731 | |
| 1732 | |
| 1733 | #if NOT_YET |
| 1734 | static int |
| 1735 | cons_rxrdy(void) |
| 1736 | { |
| 1737 | int val; |
| 1738 | |
| 1739 | CON_PRT("cons_rxrdy: check console RxRdy\n"); |
| 1740 | |
| 1741 | val = (cons_getreg(UART_LSR) & UART_LSR_DR) ? 1 : 0; |
| 1742 | |
| 1743 | CON_PRT("cons_rxrdy: RxRdy %d\n", val); |
| 1744 | return val; |
| 1745 | } |
| 1746 | |
| 1747 | |
| 1748 | static int |
| 1749 | cons_getc(void) |
| 1750 | { |
| 1751 | int c; |
| 1752 | |
| 1753 | CON_PRT("cons_getc: rd from console\n"); |
| 1754 | |
| 1755 | while((cons_getreg(UART_LSR) & UART_LSR_DR) == 0) |
| 1756 | myDELAY(1000); |
| 1757 | c = cons_getreg(UART_RX); |
| 1758 | |
| 1759 | CON_PRT("cons_getc: read '%02x'\n", c); |
| 1760 | return c; |
| 1761 | } |
| 1762 | #endif |
| 1763 | |
| 1764 | |
| 1765 | static void |
| 1766 | cons_putc(int c) |
| 1767 | { |
| 1768 | int limit; |
| 1769 | |
| 1770 | CON_PRT("cons_putc: wr '%02x' to console\n", c); |
| 1771 | |
| 1772 | limit = 10; |
| 1773 | while((cons_getreg(UART_LSR) & UART_LSR_THRE) == 0 && --limit) ; |
| 1774 | CON_PRT("cons_putc: THRE ready, limit %d\n", limit); |
| 1775 | cons_setreg(UART_TX, c); |
| 1776 | |
| 1777 | #if 0 |
| 1778 | /* |
| 1779 | * No reason to wait for it to clock out |
| 1780 | */ |
| 1781 | limit = 10; |
| 1782 | while((cons_getreg(UART_LSR) & UART_LSR_TEMT) == 0 && --limit) ; |
| 1783 | CON_PRT("cons_putc: TEMT ready, limit %d\n", limit); |
| 1784 | #endif |
| 1785 | |
| 1786 | CON_PRT("cons_putc: done printing '%02x'\n", c); |
| 1787 | } |
| 1788 | |
| 1789 | |
| 1790 | /* |
| 1791 | * Simple exclusive access method for the 'OverClock' I2C bus. |
| 1792 | * The POST-card UART is the only known other party using this |
| 1793 | * bus under normal circumstances (because it is the console). |
| 1794 | * If the POST-card UART is built into the kernel, the lock is |
| 1795 | * in file 'drivers/serial/8250_sc16is7xx.c'. Otherwise the lock |
| 1796 | * is local to the RAS module. |
| 1797 | * |
| 1798 | * Warning: |
| 1799 | * This locking works perfectly in standard contexts and in |
| 1800 | * the MCA handling contexts. However, they do not mix safely. |
| 1801 | * If the ee_lock is taken from standard context, then an |
| 1802 | * MCA event may hang because it cannot get the lock, ever! |
| 1803 | * This can happen when/if ee_print() is used. |
| 1804 | */ |
| 1805 | |
| 1806 | #ifdef CONFIG_I2C_PXA |
| 1807 | extern atomic_t pxa_block; |
| 1808 | extern char pxa_state; |
| 1809 | #else |
| 1810 | atomic_t pxa_block = ATOMIC_INIT(0); |
| 1811 | char pxa_state = '-'; |
| 1812 | #endif |
| 1813 | |
| 1814 | static void |
| 1815 | ee_lock(void) |
| 1816 | { |
| 1817 | /* |
| 1818 | * Wait here until lock ackquired |
| 1819 | */ |
| 1820 | while(atomic_xchg(&pxa_block, 1)) |
| 1821 | myDELAY(50); |
| 1822 | |
| 1823 | /* |
| 1824 | * Lock taken, I2C transaction could be underway. |
| 1825 | * Wait for it to end or forcefully terminate it. |
| 1826 | */ |
| 1827 | i2c_grab(); |
| 1828 | } |
| 1829 | |
| 1830 | static void |
| 1831 | ee_unlock(void) |
| 1832 | { |
| 1833 | i2c_release(); |
| 1834 | atomic_xchg(&pxa_block, 0); |
| 1835 | } |
| 1836 | |
| 1837 | |
| 1838 | /* |
| 1839 | * Printf to the POST card UART. |
| 1840 | * |
| 1841 | * Function ee_printk() and ee_print() both creates |
| 1842 | * a message into a local buffer from where the RAS |
| 1843 | * timer will synch them into the kernel log about |
| 1844 | * once a second. ee_printk() is thread safe. |
| 1845 | * |
| 1846 | * Function ee_print() will also attempt to write to |
| 1847 | * the POST card serial port, which may be useful |
| 1848 | * from exception context where OS services are out |
| 1849 | * of the question. |
| 1850 | * |
| 1851 | * WARNING: ee_print() takes the same lock as |
| 1852 | * the machine checks does, so if a machine check |
| 1853 | * happens while a standard context thread are in |
| 1854 | * this code we'll have an instant kernel hang. |
| 1855 | */ |
| 1856 | |
| 1857 | char ee_buf[EE_BUF_COUNT * EE_BUF_LINELEN]; |
| 1858 | atomic_t ee_msg = ATOMIC_INIT(-1); |
| 1859 | atomic_t ee_seen = ATOMIC_INIT(-1); |
| 1860 | int ee_rdy; |
| 1861 | |
| 1862 | #define EE_TSC 0 /* 1 to get rdtsc() included */ |
| 1863 | |
| 1864 | char * |
| 1865 | ee_fmt(char * fmt, va_list args) |
| 1866 | { |
| 1867 | char * buf; |
| 1868 | int msg_id, tsl; |
| 1869 | #if EE_TSC |
| 1870 | uint64_t ts = rdtsc(); |
| 1871 | #endif |
| 1872 | |
| 1873 | msg_id = atomic_inc_return(&ee_msg); |
| 1874 | buf = ee_buf + (msg_id % EE_BUF_COUNT) * EE_BUF_LINELEN; |
| 1875 | if (! *buf) { |
| 1876 | #if EE_TSC |
| 1877 | tsl = snprintf(buf, EE_BUF_LINELEN - 1, "[%lld] ", ts); |
| 1878 | #else |
| 1879 | tsl = 0; |
| 1880 | #endif |
| 1881 | vsnprintf(buf + tsl, EE_BUF_LINELEN - 1 - tsl, fmt, args); |
| 1882 | return buf; |
| 1883 | } |
| 1884 | return 0; |
| 1885 | } |
| 1886 | |
| 1887 | int |
| 1888 | ee_printk(char * fmt, ...) |
| 1889 | { |
| 1890 | va_list args; |
| 1891 | char * buf; |
| 1892 | |
| 1893 | va_start(args, fmt); |
| 1894 | buf = ee_fmt(fmt, args); |
| 1895 | va_end(args); |
| 1896 | |
| 1897 | return buf ? strlen(buf) : 0; |
| 1898 | } |
| 1899 | |
| 1900 | int |
| 1901 | ee_print(char * fmt, ...) |
| 1902 | { |
| 1903 | char ch, * buf; |
| 1904 | va_list args; |
| 1905 | int len; |
| 1906 | |
| 1907 | va_start(args, fmt); |
| 1908 | buf = ee_fmt(fmt, args); |
| 1909 | va_end(args); |
| 1910 | |
| 1911 | len = 0; |
| 1912 | if (ee_rdy && buf) { |
| 1913 | /* |
| 1914 | * Get I2C bus exclusive access, |
| 1915 | * setup for targeting the UART and |
| 1916 | * send string one byte at a time |
| 1917 | * with lf -> lr/cr translation. |
| 1918 | */ |
| 1919 | ee_lock(); |
| 1920 | xfr_configure(SC16IS_ADDR(SC16IS_ADDR_1, SC16IS_ADDR_0), FREQ_AUTO); |
| 1921 | while((ch = *(buf++))) { |
| 1922 | if (ch == '\n') { |
| 1923 | cons_putc('\r'); |
| 1924 | len++; |
| 1925 | } |
| 1926 | cons_putc(ch); |
| 1927 | len++; |
| 1928 | } |
| 1929 | ee_unlock(); |
| 1930 | } |
| 1931 | |
| 1932 | return len; |
| 1933 | } |
| 1934 | EXPORT_SYMBOL_GPL(ee_print); |
| 1935 | |
| 1936 | |
| 1937 | |
| 1938 | /* |
| 1939 | ** |
| 1940 | ** EEPROM support routines |
| 1941 | ** |
| 1942 | ** The device is a 1 Mbit Atmel AT24C1024 which has 128 |
| 1943 | ** KByte addressable storage over 2 slave addresses. |
| 1944 | ** Lower 64 KB is at slave address 0x54 and upper |
| 1945 | ** 64KB is at slave address 0x55, i.e. it uses LSB of |
| 1946 | ** the slave address as bit 16 of the byte address. |
| 1947 | ** |
| 1948 | ** All EEPROM support routines assume I2C controller |
| 1949 | ** to be initialized by xfr_configure() and expects |
| 1950 | ** exclusive access to the device |
| 1951 | ** |
| 1952 | ** Only KnC has this storage |
| 1953 | */ |
| 1954 | |
| 1955 | #ifdef CONFIG_MK1OM |
| 1956 | |
| 1957 | #define MR_ELOG_SIZE (128 * 1024) /* 1 Mbit */ |
| 1958 | #define MR_ELOG_ADDR_LO 0x54 /* Lo 64K slave */ |
| 1959 | #define MR_ELOG_ADDR_HI 0x55 /* Hi 64K slave */ |
| 1960 | #define EE_PG_SIZ 256 /* Device page size */ |
| 1961 | |
| 1962 | |
| 1963 | /* |
| 1964 | * Layout of the EEPROM is roughly like this: |
| 1965 | * |
| 1966 | * Bytes Content |
| 1967 | * 0 - 15 Fixed log header |
| 1968 | * 16 - 17 Log head index (last written) |
| 1969 | * 18 - 19 Log tail index (last read) |
| 1970 | * 20 - end Log entries |
| 1971 | * |
| 1972 | * By definition, the log is fully read when head and |
| 1973 | * tail pointer are equal (initial value: last entry). |
| 1974 | * The effective log size is |
| 1975 | * (device_size - sizeof(McaHeader))/sizeof(McaRecord). |
| 1976 | * |
| 1977 | * Fields of interest in the log entry 'id' are |
| 1978 | * bits 7:0 Source index, 8 bit |
| 1979 | * bits 18:16 Source type, 3 bit |
| 1980 | * bits 22:22 Injected error flag |
| 1981 | * bits 23:23 Repaired flag |
| 1982 | * bits 24:24 Filtered flag |
| 1983 | * bits 31:31 Valid flag |
| 1984 | * |
| 1985 | * Enumeration details are in file micras_mca.h |
| 1986 | * |
| 1987 | * Time stamps in the MCA header and event records are supposed to be |
| 1988 | * standard 32-bit Unix format, i.e. seconds since 00:00 Jan 1 1979 GMT. |
| 1989 | * This will wrap some time Jan 19th 2038, which is about 25 years from |
| 1990 | * the release of KnC. Given the use of 386's (introduced 1985) in the |
| 1991 | * modern data center anno '12, 32 bit will last for all practical purposes. |
| 1992 | */ |
| 1993 | |
| 1994 | typedef struct _mca_header { |
| 1995 | uint8_t signature[8]; /* Magic */ |
| 1996 | uint8_t header_ver; /* Format revision */ |
| 1997 | uint8_t rec_start; /* Offset of 1st record */ |
| 1998 | uint16_t rec_size; /* Size of an MCA record */ |
| 1999 | uint16_t entries; /* Log size */ |
| 2000 | uint8_t logfull; /* Log has wrapped (reserved) */ |
| 2001 | uint8_t hwtype; /* Board type (reserved) */ |
| 2002 | uint16_t rec_head; /* Head index */ |
| 2003 | uint16_t rec_tail; /* Tail index */ |
| 2004 | } McaHeader; |
| 2005 | |
| 2006 | typedef struct _mca_record { |
| 2007 | uint32_t id; /* Event origin & flags */ |
| 2008 | uint32_t stamp; /* Low 32 bit of system time */ |
| 2009 | uint64_t ctl; /* MCA bank register 'CTL' */ |
| 2010 | uint64_t status; /* MCA bank register 'STATUS' */ |
| 2011 | uint64_t addr; /* MCA bank register 'ADDR' */ |
| 2012 | uint64_t misc; /* MCA bank register 'MISC' */ |
| 2013 | } McaRecord; |
| 2014 | |
| 2015 | |
| 2016 | /* |
| 2017 | * Header to drop onto un-initalized EEPROM |
| 2018 | * By definition, the EEPROM is uninitialised |
| 2019 | * if the magic signature is wrong. |
| 2020 | */ |
| 2021 | |
| 2022 | #define MR_ELOG_NUM (MR_ELOG_SIZE - sizeof(McaHeader))/sizeof(McaRecord) |
| 2023 | |
| 2024 | static McaHeader elog_preset = { |
| 2025 | .signature = {"MCA_LOG"}, |
| 2026 | .header_ver = 1, |
| 2027 | .rec_start = sizeof(McaHeader), |
| 2028 | .rec_size = sizeof(McaRecord), |
| 2029 | .entries = MR_ELOG_NUM, |
| 2030 | .logfull = -1, |
| 2031 | .hwtype = 0, |
| 2032 | .rec_head = MR_ELOG_NUM - 1, |
| 2033 | .rec_tail = MR_ELOG_NUM - 1, |
| 2034 | }; |
| 2035 | |
| 2036 | static uint16_t ee_num, ee_head, ee_tail; /* Cached log state */ |
| 2037 | |
| 2038 | |
| 2039 | #if EPR_DBG || EE_VERIFY |
| 2040 | /* |
| 2041 | * Printk from EEPROM code. |
| 2042 | * We have the lock, and the I2C target address is |
| 2043 | * set for the Atmel device, we must reset I2C for |
| 2044 | * the UART on every entry, and reset it back to the |
| 2045 | * EEPROM in order to keep this function transparent. |
| 2046 | * |
| 2047 | * Warning: this call is highly risky, particularly |
| 2048 | * in error conditions where the I2C bus is involved. |
| 2049 | * Do not call it during an EEPROM I2C transaction!! |
| 2050 | * Use for internal debug _ONLY_ and at own risk. |
| 2051 | */ |
| 2052 | |
| 2053 | int |
| 2054 | elog_print(char * fmt, ...) |
| 2055 | { |
| 2056 | char * buf, ch; |
| 2057 | va_list args; |
| 2058 | int len; |
| 2059 | |
| 2060 | va_start(args, fmt); |
| 2061 | buf = ee_fmt(fmt, args); |
| 2062 | va_end(args); |
| 2063 | |
| 2064 | if (! buf) |
| 2065 | return 0; |
| 2066 | |
| 2067 | xfr_configure(SC16IS_ADDR(SC16IS_ADDR_1, SC16IS_ADDR_0), FREQ_AUTO); |
| 2068 | |
| 2069 | len = 0; |
| 2070 | while((ch = *(buf++))) { |
| 2071 | if (ch == '\n') { |
| 2072 | cons_putc('\r'); |
| 2073 | len++; |
| 2074 | } |
| 2075 | cons_putc(ch); |
| 2076 | len++; |
| 2077 | } |
| 2078 | |
| 2079 | return len; |
| 2080 | } |
| 2081 | #endif /* EPR_DBG */ |
| 2082 | |
| 2083 | |
| 2084 | /* |
| 2085 | * Write block of data to EEPROM |
| 2086 | * The Atmel device does not allow writes to cross the |
| 2087 | * internal page size, which is 256 bytes on the 1 Mbit part. |
| 2088 | * Given the size of an McaRecord this is likely to occur, but |
| 2089 | * cannot happen more than once per call. |
| 2090 | * Must preset slave address on every call. |
| 2091 | */ |
| 2092 | |
| 2093 | static void |
| 2094 | ee_wr(uint8_t addr, uint16_t ofs, uint8_t *buf, uint8_t len) |
| 2095 | { |
| 2096 | uint16_t pix, swp; |
| 2097 | uint8_t wl; |
| 2098 | int err; |
| 2099 | |
| 2100 | if (mce_disabled) |
| 2101 | return; |
| 2102 | |
| 2103 | if ((ofs + len) < ofs) { |
| 2104 | EPR_PRT("ee_wr: address overrun\n"); |
| 2105 | return; |
| 2106 | } |
| 2107 | |
| 2108 | xfr_configure(addr, FREQ_AUTO); |
| 2109 | |
| 2110 | pix = ofs & (EE_PG_SIZ - 1); |
| 2111 | while(len) { |
| 2112 | wl = (uint8_t) min((uint16_t)len, (uint16_t)(EE_PG_SIZ - pix)); |
| 2113 | |
| 2114 | err = xfr_start(I2C_WRITE); |
| 2115 | if (err) { |
| 2116 | EPR_PRT("ee_wr: xfr_start (WR) err %d\n", err); |
| 2117 | return; |
| 2118 | } |
| 2119 | |
| 2120 | /* |
| 2121 | * Byte swap, send Most significant byte first |
| 2122 | */ |
| 2123 | swp = (ofs >> 8) | (ofs << 8); |
| 2124 | err = xfr_write(FALSE, 2, (uint8_t *) &swp); |
| 2125 | if (err) { |
| 2126 | EPR_PRT("ee_wr: xfr_write offset (%02x, %02x) err %d\n", ofs >> 8, ofs & 0xff, err); |
| 2127 | return; |
| 2128 | } |
| 2129 | |
| 2130 | /* |
| 2131 | * Write payload to device |
| 2132 | */ |
| 2133 | err = xfr_write(TRUE, wl, buf); |
| 2134 | if (err) { |
| 2135 | EPR_PRT("ee_wr: xfr_write %d bytes (%02x, %02x ..) err %d\n", wl, buf[0], buf[1], err); |
| 2136 | return; |
| 2137 | } |
| 2138 | ofs += wl; |
| 2139 | buf += wl; |
| 2140 | len -= wl; |
| 2141 | pix = 0; |
| 2142 | |
| 2143 | /* |
| 2144 | * Data sheet says wait 5 mSec before next |
| 2145 | * transaction to the device after a write. |
| 2146 | */ |
| 2147 | myDELAY(5000); |
| 2148 | } |
| 2149 | } |
| 2150 | |
| 2151 | |
| 2152 | /* |
| 2153 | * Read block of data from EEPROM |
| 2154 | * Must preset slave address on every call. |
| 2155 | */ |
| 2156 | |
| 2157 | static void |
| 2158 | ee_rd(uint8_t addr, uint16_t ofs, uint8_t *buf, uint8_t len) |
| 2159 | { |
| 2160 | uint16_t swp; |
| 2161 | int err; |
| 2162 | |
| 2163 | if ((ofs + len) < ofs) { |
| 2164 | EPR_PRT("ee_rd: address overrun\n"); |
| 2165 | return; |
| 2166 | } |
| 2167 | |
| 2168 | xfr_configure(addr, FREQ_AUTO); |
| 2169 | |
| 2170 | err = xfr_start(I2C_WRITE); |
| 2171 | if (err) { |
| 2172 | EPR_PRT("ee_rd: xfr_start (WR) err %d\n", err); |
| 2173 | return; |
| 2174 | } |
| 2175 | |
| 2176 | /* |
| 2177 | * Byte swap, send Most significant byte first |
| 2178 | */ |
| 2179 | swp = (ofs >> 8) | (ofs << 8); |
| 2180 | err = xfr_write(FALSE, 2, (uint8_t *) &swp); |
| 2181 | if (err) { |
| 2182 | EPR_PRT("ee_rd: xfr_write (%02x, %02x) err %d\n", ofs >> 8, ofs & 0xff, err); |
| 2183 | return; |
| 2184 | } |
| 2185 | |
| 2186 | /* |
| 2187 | * Change bus direction and read payload |
| 2188 | */ |
| 2189 | err = xfr_rept_start(I2C_READ); |
| 2190 | if (err) { |
| 2191 | EPR_PRT("ee_rd: xfr_rept_start (RD) err %d\n", err); |
| 2192 | return; |
| 2193 | } |
| 2194 | err = xfr_read(TRUE, len, buf); |
| 2195 | if (err) { |
| 2196 | EPR_PRT("ee_rd: xfr_read err %d\n", err); |
| 2197 | return; |
| 2198 | } |
| 2199 | } |
| 2200 | |
| 2201 | |
| 2202 | /* |
| 2203 | * Read one MCA event record from EEPROM |
| 2204 | * Handles crossing device addresses. |
| 2205 | */ |
| 2206 | |
| 2207 | static void |
| 2208 | ee_get(McaRecord * rec, int no) |
| 2209 | { |
| 2210 | uint32_t pos, mid, low; |
| 2211 | |
| 2212 | mid = MR_ELOG_SIZE / 2; |
| 2213 | memset(rec, '\0', sizeof(*rec)); |
| 2214 | pos = sizeof(McaHeader) + no * sizeof(McaRecord); |
| 2215 | if (pos < (mid - sizeof(McaRecord))) { |
| 2216 | /* |
| 2217 | * Record fit entirely in lower half of EEPROM |
| 2218 | */ |
| 2219 | ee_rd(MR_ELOG_ADDR_LO, pos, (uint8_t *) rec, sizeof(*rec)); |
| 2220 | } |
| 2221 | else |
| 2222 | if (pos > mid) { |
| 2223 | /* |
| 2224 | * Record fit entirely in upper half of EEPROM |
| 2225 | */ |
| 2226 | ee_rd(MR_ELOG_ADDR_HI, pos - mid, (uint8_t *) rec, sizeof(*rec)); |
| 2227 | } |
| 2228 | else { |
| 2229 | /* |
| 2230 | * Record spans both halves, need 2 reads. |
| 2231 | */ |
| 2232 | low = mid - pos; |
| 2233 | ee_rd(MR_ELOG_ADDR_LO, pos, (uint8_t *) rec, low); |
| 2234 | ee_rd(MR_ELOG_ADDR_HI, 0, ((uint8_t *) rec) + low, sizeof(*rec) - low); |
| 2235 | } |
| 2236 | } |
| 2237 | |
| 2238 | |
| 2239 | /* |
| 2240 | * Write one MCA event record to EEPROM |
| 2241 | * Handles crossing device addresses. |
| 2242 | */ |
| 2243 | |
| 2244 | static void |
| 2245 | ee_put(McaRecord * rec, int no) |
| 2246 | { |
| 2247 | uint32_t loc, mid, low; |
| 2248 | |
| 2249 | mid = MR_ELOG_SIZE / 2; |
| 2250 | loc = sizeof(McaHeader) + no * sizeof(McaRecord); |
| 2251 | if (loc < (mid - sizeof(McaRecord))) { |
| 2252 | /* |
| 2253 | * Record fit entirely in lower half of EEPROM |
| 2254 | */ |
| 2255 | ee_wr(MR_ELOG_ADDR_LO, loc, (uint8_t *) rec, sizeof(*rec)); |
| 2256 | } |
| 2257 | else |
| 2258 | if (loc > mid) { |
| 2259 | /* |
| 2260 | * Record fit entirely in upper half of EEPROM |
| 2261 | */ |
| 2262 | ee_wr(MR_ELOG_ADDR_HI, loc - mid, (uint8_t *) rec, sizeof(*rec)); |
| 2263 | } |
| 2264 | else { |
| 2265 | /* |
| 2266 | * Record spans both halves, need 2 writes. |
| 2267 | */ |
| 2268 | low = mid - loc; |
| 2269 | ee_wr(MR_ELOG_ADDR_LO, loc, (uint8_t *) rec, low); |
| 2270 | ee_wr(MR_ELOG_ADDR_HI, 0, ((uint8_t *) rec) + low, sizeof(*rec) - low); |
| 2271 | } |
| 2272 | } |
| 2273 | |
| 2274 | |
| 2275 | /* |
| 2276 | * Add one MCA event to the EEPROM |
| 2277 | * Store the passed event info in the EEPROM, and update write |
| 2278 | * position to next entry, just in case if there are more than |
| 2279 | * one MC event detected that needs checking in maintenance mode. |
| 2280 | * |
| 2281 | * This can be called in exception context, and therefore must |
| 2282 | * work without any kernel support whatsoever. We must assume |
| 2283 | * kernel services are not reliable at this point. |
| 2284 | */ |
| 2285 | |
| 2286 | void |
| 2287 | micras_mc_log(struct mce_info * event) |
| 2288 | { |
| 2289 | McaRecord mr; |
| 2290 | uint16_t nxt, id; |
| 2291 | |
| 2292 | if (mce_disabled) |
| 2293 | return; |
| 2294 | |
| 2295 | /* |
| 2296 | * Print entry on serial console (copy in kernel log) |
| 2297 | */ |
| 2298 | #if MC_VERBOSE |
| 2299 | ee_printk("RAS.elog: bnk %d, id %d, ctl %llx, stat %llx, addr %llx, misc %llx\n", |
| 2300 | event->org, event->id, event->ctl, event->status, event->addr, event->misc); |
| 2301 | #endif |
| 2302 | |
| 2303 | /* |
| 2304 | * Bail if EEPROM not in order (I2C lock-up or faulty device) |
| 2305 | */ |
| 2306 | if (! ee_num) |
| 2307 | return; |
| 2308 | |
| 2309 | /* |
| 2310 | * Prepare MCA error log record. |
| 2311 | * We use the pysical CPU ID in the EEPROM records. |
| 2312 | */ |
| 2313 | id = (event->org <= 2) ? event->pid : event->id; |
| 2314 | mr.id = PUT_BITS( 7, 0, id) | |
| 2315 | PUT_BITS(18, 16, event->org) | |
| 2316 | PUT_BIT(22, (event->flags & MC_FLG_FALSE) != 0) | |
| 2317 | PUT_BIT(24, (event->flags & MC_FLG_FILTER) != 0) | |
| 2318 | PUT_BIT(31, 1); |
| 2319 | mr.stamp = (uint32_t) event->stamp; |
| 2320 | mr.ctl = event->ctl; |
| 2321 | mr.status = event->status; |
| 2322 | mr.addr = event->addr; |
| 2323 | mr.misc = event->misc; |
| 2324 | |
| 2325 | #if ADD_DIE_TEMP |
| 2326 | { |
| 2327 | uint32_t tmp; |
| 2328 | tmp = mr_sbox_rl(0, SBOX_THERMAL_STATUS_2); |
| 2329 | mr.id |= PUT_BITS(15, 8, GET_BITS(19, 10, tmp)); |
| 2330 | } |
| 2331 | #endif |
| 2332 | |
| 2333 | /* |
| 2334 | * Get I2C bus exclusive access |
| 2335 | */ |
| 2336 | ee_lock(); |
| 2337 | |
| 2338 | #if EE_VERIFY |
| 2339 | { |
| 2340 | /* |
| 2341 | * Check for header corruption. |
| 2342 | * Time sink, only enable for debugging |
| 2343 | */ |
| 2344 | extern int in_sync; |
| 2345 | McaHeader hdr; |
| 2346 | |
| 2347 | ee_rd(MR_ELOG_ADDR_LO, 0, (uint8_t *) &hdr, sizeof(hdr)); |
| 2348 | if (memcmp(hdr.signature, elog_preset.signature, |
| 2349 | sizeof(elog_preset.signature))) { |
| 2350 | if (in_sync) { |
| 2351 | printk("mc_log: Header corruption detected\n"); |
| 2352 | dmp_hex(&hdr, sizeof(hdr), "mc_log: EEPROM header (entry)"); |
| 2353 | } |
| 2354 | else { |
| 2355 | elog_print("mc_log: Header corruption detected (entry)\n"); |
| 2356 | elog_print("EEPROM header: signature bad, ver %d, type %d\n", |
| 2357 | hdr.header_ver, hdr.hwtype); |
| 2358 | elog_print("EEPROM capacity: %d events, size %d, start %d\n", |
| 2359 | hdr.entries, hdr.rec_size, hdr.rec_start); |
| 2360 | elog_print("EEPROM state: head %d, tail %d, full %d\n", |
| 2361 | hdr.rec_head, hdr.rec_tail, hdr.logfull); |
| 2362 | } |
| 2363 | } |
| 2364 | } |
| 2365 | #endif |
| 2366 | |
| 2367 | nxt = (ee_head + 1) % ee_num; |
| 2368 | if (nxt == ee_tail) { |
| 2369 | ee_printk("RAS.elog: EEPROM full, dropping event\n"); |
| 2370 | ee_unlock(); |
| 2371 | return; |
| 2372 | } |
| 2373 | ee_put(&mr, nxt); |
| 2374 | |
| 2375 | #if EE_VERIFY |
| 2376 | { |
| 2377 | /* |
| 2378 | * Read back and verify with memory buffer |
| 2379 | * Note: only works on 1st half of device. |
| 2380 | * Time sink, only enable for debugging |
| 2381 | */ |
| 2382 | McaRecord tst; |
| 2383 | |
| 2384 | ee_rd(MR_ELOG_ADDR_LO, loc, (uint8_t *) &tst, sizeof(tst)); |
| 2385 | if (memcmp(&mr, &tst, sizeof(tst))) |
| 2386 | elog_print("Write event verify failed\n"); |
| 2387 | else |
| 2388 | elog_print("Write event verify OK\n"); |
| 2389 | } |
| 2390 | #endif |
| 2391 | |
| 2392 | /* |
| 2393 | * Update head pointer in EEPROM header |
| 2394 | */ |
| 2395 | ee_wr(MR_ELOG_ADDR_LO, offsetof(McaHeader, rec_head), (uint8_t *) &nxt, sizeof(nxt)); |
| 2396 | ee_head = nxt; |
| 2397 | |
| 2398 | #if EE_VERIFY |
| 2399 | { |
| 2400 | /* |
| 2401 | * Read back and verify with memory buffer |
| 2402 | * Time sink, only enable for debugging |
| 2403 | */ |
| 2404 | uint16_t tst; |
| 2405 | |
| 2406 | ee_rd(MR_ELOG_ADDR_LO, 16, (uint8_t *) &tst, 2); |
| 2407 | if (tst != nxt) |
| 2408 | elog_print("Write index verify failed\n"); |
| 2409 | else |
| 2410 | elog_print("Write index verify OK\n"); |
| 2411 | } |
| 2412 | |
| 2413 | { |
| 2414 | /* |
| 2415 | * Check again for header corruption |
| 2416 | * Time sink, only enable for debugging |
| 2417 | */ |
| 2418 | extern int in_sync; |
| 2419 | McaHeader hdr; |
| 2420 | |
| 2421 | ee_rd(MR_ELOG_ADDR_LO, 0, (uint8_t *) &hdr, sizeof(hdr)); |
| 2422 | if (memcmp(hdr.signature, elog_preset.signature, |
| 2423 | sizeof(elog_preset.signature))) { |
| 2424 | if (in_sync) { |
| 2425 | printk("mc_log: Header corruption detected (exit)\n"); |
| 2426 | dmp_hex(&hdr, sizeof(hdr), "mc_log: EEPROM header"); |
| 2427 | } |
| 2428 | else { |
| 2429 | elog_print("mc_log: Header corruption detected (exit)\n"); |
| 2430 | elog_print("EEPROM header: signature bad, ver %d, type %d\n", |
| 2431 | hdr.header_ver, hdr.hwtype); |
| 2432 | elog_print("EEPROM capacity: %d events, size %d, start %d\n", |
| 2433 | hdr.entries, hdr.rec_size, hdr.rec_start); |
| 2434 | elog_print("EEPROM state: head %d, tail %d, full %d\n", |
| 2435 | hdr.rec_head, hdr.rec_tail, hdr.logfull); |
| 2436 | } |
| 2437 | } |
| 2438 | } |
| 2439 | #endif |
| 2440 | |
| 2441 | /* |
| 2442 | * Release I2C bus exclusive lock |
| 2443 | */ |
| 2444 | ee_unlock(); |
| 2445 | } |
| 2446 | |
| 2447 | |
| 2448 | /* |
| 2449 | * Reset the EEPROM to mint condition |
| 2450 | */ |
| 2451 | |
| 2452 | #define BSIZ 0xf0 |
| 2453 | |
| 2454 | static void |
| 2455 | ee_mint(void) |
| 2456 | { |
| 2457 | uint8_t buf[EE_PG_SIZ]; |
| 2458 | McaHeader hdr; |
| 2459 | uint32_t loc, mid; |
| 2460 | uint16_t ofs; |
| 2461 | uint8_t addr; |
| 2462 | |
| 2463 | |
| 2464 | if (ee_rdy && ! mce_disabled) { |
| 2465 | printk("EEPROM erase started ..\n"); |
| 2466 | memset(buf, 0xff, sizeof(buf)); |
| 2467 | |
| 2468 | ee_lock(); |
| 2469 | |
| 2470 | /* |
| 2471 | * Several cheats in this loop. |
| 2472 | * - Despite maximum transfer per write command is 255 (8 bit count), |
| 2473 | * we send only half a 'page', i.e. 128 byte, per call to ee_wr(). |
| 2474 | * - Picking exactly half a page, starting page aligned, ensures there |
| 2475 | * will be no writes across a page boundary, i.e. ee_wr() will always |
| 2476 | * result in exactly one I2C write command per call. |
| 2477 | * - We know that MR_ELOG_SIZE / (EE_PG_SIZ / 2) is a clean integer, |
| 2478 | * and therefore will be no end condition to special case. |
| 2479 | * - Same will be true for the 'mid-chip' limit where the target |
| 2480 | * address is bumped by one. |
| 2481 | */ |
| 2482 | mid = MR_ELOG_SIZE / 2; |
| 2483 | for(loc = 0; loc < MR_ELOG_SIZE; loc += (EE_PG_SIZ / 2)) { |
| 2484 | addr = (loc < mid) ? MR_ELOG_ADDR_LO : MR_ELOG_ADDR_HI; |
| 2485 | ofs = loc & 0xffff; |
| 2486 | // printk(" -- loc %5x: addr %2x, offs %4x, len %4x\n", loc, addr, ofs, EE_PG_SIZ / 2); |
| 2487 | ee_wr(addr, ofs, buf, EE_PG_SIZ / 2); |
| 2488 | } |
| 2489 | |
| 2490 | /* |
| 2491 | * Put in a fresh header |
| 2492 | */ |
| 2493 | ee_wr(MR_ELOG_ADDR_LO, 0, (uint8_t *) &elog_preset, sizeof(elog_preset)); |
| 2494 | ee_rd(MR_ELOG_ADDR_LO, 0, (uint8_t *) &hdr, sizeof(hdr)); |
| 2495 | printk("EEPROM erase complete\n"); |
| 2496 | |
| 2497 | ee_unlock(); |
| 2498 | |
| 2499 | /* |
| 2500 | * Verify that the header stuck. |
| 2501 | * If not, then complain to kernel log and set event capacity to 0 |
| 2502 | */ |
| 2503 | if (memcmp(hdr.signature, elog_preset.signature, sizeof(elog_preset.signature)) || |
| 2504 | hdr.header_ver != elog_preset.header_ver || |
| 2505 | hdr.rec_start != elog_preset.rec_start || |
| 2506 | hdr.rec_size != elog_preset.rec_size || |
| 2507 | hdr.hwtype != elog_preset.hwtype) { |
| 2508 | /* |
| 2509 | * Write EEPROM header failed. |
| 2510 | * Leave a message in the kernel log about it. |
| 2511 | */ |
| 2512 | printk("Error: EEPROM initialization failed!\n"); |
| 2513 | printk("MCA events cannot be logged to EEPROM\n"); |
| 2514 | ee_num = 0; |
| 2515 | } |
| 2516 | else { |
| 2517 | ee_num = hdr.entries; |
| 2518 | ee_head = hdr.rec_head; |
| 2519 | ee_tail = hdr.rec_tail; |
| 2520 | printk("EEPROM ready!\n"); |
| 2521 | } |
| 2522 | |
| 2523 | |
| 2524 | } |
| 2525 | } |
| 2526 | |
| 2527 | |
| 2528 | #if EE_PROC |
| 2529 | /* |
| 2530 | * Support for user space access to the EEPROM event log. |
| 2531 | * Implemented as a 'proc' file named elog, who returns |
| 2532 | * MCE events on read and on writes of 6 hex values |
| 2533 | * per line creates new event(s) to be entered. |
| 2534 | * |
| 2535 | * Compile time configurable for disabling writes and |
| 2536 | * choice of whether to dump new events or everything. |
| 2537 | */ |
| 2538 | |
| 2539 | static struct proc_dir_entry * elog_pe; |
| 2540 | |
| 2541 | /* |
| 2542 | * Write is just a simple file operation. |
| 2543 | * We do not care about file offset since the specified event is to |
| 2544 | * be added to the EEPROM at head+1, not at any arbitrary location. |
| 2545 | */ |
| 2546 | |
| 2547 | static ssize_t |
| 2548 | elog_write(struct file * file, const char __user * buff, size_t len, loff_t * off) |
| 2549 | { |
| 2550 | char * buf; |
| 2551 | uint16_t nxt; |
| 2552 | McaRecord mr; |
| 2553 | uint64_t ull[6]; |
| 2554 | char * ep, * cp; |
| 2555 | int i, err; |
| 2556 | |
| 2557 | /* |
| 2558 | * Get input line into kernel space |
| 2559 | */ |
| 2560 | if (len > PAGE_SIZE -1) |
| 2561 | len = PAGE_SIZE -1; |
| 2562 | buf = kmalloc(PAGE_SIZE, GFP_KERNEL); |
| 2563 | if (! buf) |
| 2564 | return -ENOMEM; |
| 2565 | if (copy_from_user(buf, buff, len)) { |
| 2566 | err = -EFAULT; |
| 2567 | goto wr_out; |
| 2568 | } |
| 2569 | buf[len] = '\0'; |
| 2570 | cp = ep = (char *) buf; |
| 2571 | |
| 2572 | /* |
| 2573 | * Special case EEPROM reset option, |
| 2574 | * first 5 letters form the word 'reset' |
| 2575 | */ |
| 2576 | if (!strncmp(buf, "reset", 5)) { |
| 2577 | ee_mint(); |
| 2578 | goto wr_one; |
| 2579 | } |
| 2580 | |
| 2581 | /* |
| 2582 | * Need 6 numbers for an event record |
| 2583 | */ |
| 2584 | for(i = 0; i < 6; i++) { |
| 2585 | while(isspace(*cp)) |
| 2586 | cp++; |
| 2587 | ull[i] = simple_strtoull(cp, &ep, 16); |
| 2588 | if (ep == cp || (*ep != '\0' && !isspace(*ep))) { |
| 2589 | err = -EINVAL; |
| 2590 | goto wr_out; |
| 2591 | } |
| 2592 | cp = ep; |
| 2593 | } |
| 2594 | |
| 2595 | #if 0 |
| 2596 | /* |
| 2597 | * If we were to screen this the we should ensure that |
| 2598 | * id[7:0] < CPU_MAX on org 0, 1, 2 |
| 2599 | * < DBOX_NUM on org 3 |
| 2600 | * == 0 on org 4 |
| 2601 | * < GBOX_NUM on org 5 |
| 2602 | * < TBOX_NUM on org 6 |
| 2603 | * id[18:16] <= 6 |
| 2604 | * id[23] == 0 |
| 2605 | * id[31] == 1 |
| 2606 | */ |
| 2607 | #endif |
| 2608 | |
| 2609 | if (ee_num) { |
| 2610 | mr.id = (uint32_t) ull[0]; |
| 2611 | mr.stamp = (uint32_t) ull[1]; |
| 2612 | mr.ctl = ull[2]; |
| 2613 | mr.status = ull[3]; |
| 2614 | mr.addr = ull[4]; |
| 2615 | mr.misc = ull[5]; |
| 2616 | |
| 2617 | /* |
| 2618 | * Add event record under I2C bus exclusive access |
| 2619 | */ |
| 2620 | ee_lock(); |
| 2621 | nxt = (ee_head + 1) % ee_num; |
| 2622 | ee_put(&mr, nxt); |
| 2623 | ee_wr(MR_ELOG_ADDR_LO, offsetof(McaHeader, rec_head), (uint8_t *) &nxt, sizeof(nxt)); |
| 2624 | ee_head = nxt; |
| 2625 | ee_unlock(); |
| 2626 | } |
| 2627 | |
| 2628 | /* |
| 2629 | * Swallow any trailing junk up to next newline |
| 2630 | */ |
| 2631 | wr_one: |
| 2632 | ep = strchr(buf, '\n'); |
| 2633 | if (ep) |
| 2634 | cp = ep + 1; |
| 2635 | err = cp - buf; |
| 2636 | |
| 2637 | wr_out: |
| 2638 | kfree(buf); |
| 2639 | return err; |
| 2640 | } |
| 2641 | |
| 2642 | |
| 2643 | /* |
| 2644 | * Use the sequencer to read one event at a time, |
| 2645 | * in order of occurrence in the EEPROM. Sequence |
| 2646 | * position is event index in range 0 .. ee_num, |
| 2647 | * which will be offset by (ee_tail + 1) modulo |
| 2648 | * ee_num if EE_PROC_NEW flag is set. |
| 2649 | */ |
| 2650 | |
| 2651 | static int elog_eof; /* Elog end-of-file marker */ |
| 2652 | |
| 2653 | static int |
| 2654 | elog_seq_show(struct seq_file * f, void * v) |
| 2655 | { |
| 2656 | McaRecord mr; |
| 2657 | int pos, nxt; |
| 2658 | static int inv; |
| 2659 | |
| 2660 | pos = *(loff_t *) v; |
| 2661 | |
| 2662 | /* |
| 2663 | * Print nice header on 1st read from /proc/elog |
| 2664 | */ |
| 2665 | if (! pos) { |
| 2666 | extern struct mr_rsp_hwinf hwinf; |
| 2667 | struct mr_rsp_hwinf * r = &hwinf; |
| 2668 | |
| 2669 | inv = 0; |
| 2670 | seq_printf(f, "Card %c%c%c%c%c%c%c%c%c%c%c%c: " |
| 2671 | "brd %d, fab %d, sku %d, rev %d, stp %d, sub %d\n", |
| 2672 | r->serial[0], r->serial[1], r->serial[2], r->serial[3], |
| 2673 | r->serial[4], r->serial[5], r->serial[6], r->serial[7], |
| 2674 | r->serial[8], r->serial[9], r->serial[10], r->serial[11], |
| 2675 | r->board, r->fab, r->sku, r->rev, r->step, r->substep); |
| 2676 | if (ee_num) { |
| 2677 | seq_printf(f, "Head %d, tail %d, cap %d\n", ee_head, ee_tail, ee_num); |
| 2678 | seq_printf(f, "%5s %8s %12s %8s %16s %16s %16s %16s\n", |
| 2679 | "index", "id", "id decode", "time", "ctrl", "status", "addr", "misc"); |
| 2680 | } |
| 2681 | else |
| 2682 | seq_printf(f, "Error: EEPROM not initialized\n"); |
| 2683 | } |
| 2684 | |
| 2685 | /* |
| 2686 | * Set EOF and quit if EEPROM not accessible |
| 2687 | */ |
| 2688 | if (! ee_num) { |
| 2689 | elog_eof = 1; |
| 2690 | return 0; |
| 2691 | } |
| 2692 | |
| 2693 | /* |
| 2694 | * Get event under I2C bus exclusive access |
| 2695 | */ |
| 2696 | #if EE_PROC_NEW |
| 2697 | nxt = (pos + ee_tail + 1) % ee_num; |
| 2698 | #else |
| 2699 | nxt = pos; |
| 2700 | #endif |
| 2701 | ee_lock(); |
| 2702 | ee_get(&mr, nxt); |
| 2703 | ee_unlock(); |
| 2704 | |
| 2705 | #if ! EE_PROC_NEW |
| 2706 | /* |
| 2707 | * We refuse to print invalid entries. |
| 2708 | * However, a freshly reset EEPROM contains all 1s and |
| 2709 | * therefore we won't rely on the valid-bit alone. |
| 2710 | * Instead rely on the unused areas of 'id' to be 0s. |
| 2711 | * Probably need to stop sequencer once a bad entry is |
| 2712 | * seen because in all likelihood we've reached the |
| 2713 | * log end and reading the remainder of the EEPROM will |
| 2714 | * just be waste of time. |
| 2715 | */ |
| 2716 | if (GET_BITS(30, 25, mr.id) == 0x3f && |
| 2717 | GET_BITS(21, 19, mr.id) == 0x07 && |
| 2718 | GET_BITS(15, 8, mr.id) == 0xff) { |
| 2719 | if (inv++ > 10) |
| 2720 | elog_eof = 1; |
| 2721 | return 0; |
| 2722 | } |
| 2723 | #endif |
| 2724 | |
| 2725 | seq_printf(f, "%5d %08x [%d %3d %c%c%c%c] %08x %016llx %016llx %016llx %016llx\n", |
| 2726 | nxt, mr.id, |
| 2727 | GET_BITS(18,16,mr.id), |
| 2728 | GET_BITS(7,0,mr.id), |
| 2729 | GET_BIT(22,mr.id) ? 'I' : ' ', |
| 2730 | GET_BIT(23,mr.id) ? 'R' : ' ', |
| 2731 | GET_BIT(24,mr.id) ? 'F' : ' ', |
| 2732 | GET_BIT(31,mr.id) ? 'V' : ' ', |
| 2733 | mr.stamp, mr.ctl, mr.status, mr.addr, mr.misc); |
| 2734 | |
| 2735 | return 0; |
| 2736 | } |
| 2737 | |
| 2738 | static void * |
| 2739 | elog_seq_start(struct seq_file * f, loff_t * pos) |
| 2740 | { |
| 2741 | if (ee_num) { |
| 2742 | if (*pos >= ee_num) |
| 2743 | return NULL; |
| 2744 | #if EE_PROC_NEW |
| 2745 | /* |
| 2746 | * Skip checks if we are dumping full log |
| 2747 | */ |
| 2748 | if (ee_head == ee_tail) |
| 2749 | return NULL; |
| 2750 | if (*pos && ((*pos + ee_tail) % ee_num) == ee_head) |
| 2751 | return NULL; |
| 2752 | #endif |
| 2753 | } |
| 2754 | |
| 2755 | elog_eof = 0; |
| 2756 | |
| 2757 | return pos; |
| 2758 | } |
| 2759 | |
| 2760 | static void * |
| 2761 | elog_seq_next(struct seq_file * f, void * v, loff_t * pos) |
| 2762 | { |
| 2763 | if (elog_eof) |
| 2764 | return NULL; |
| 2765 | |
| 2766 | (*pos)++; |
| 2767 | if (*pos >= ee_num) |
| 2768 | return NULL; |
| 2769 | |
| 2770 | #if EE_PROC_NEW |
| 2771 | /* |
| 2772 | * No wrap checks if we are dumping full log |
| 2773 | */ |
| 2774 | { |
| 2775 | int nxt; |
| 2776 | |
| 2777 | nxt = ((*pos) + ee_tail) % ee_num; |
| 2778 | if (nxt == ee_head) |
| 2779 | return NULL; |
| 2780 | } |
| 2781 | #endif |
| 2782 | |
| 2783 | return pos; |
| 2784 | } |
| 2785 | |
| 2786 | static void |
| 2787 | elog_seq_stop(struct seq_file * f, void * v) |
| 2788 | { |
| 2789 | } |
| 2790 | |
| 2791 | static const struct seq_operations elog_seq_ops = { |
| 2792 | .start = elog_seq_start, |
| 2793 | .next = elog_seq_next, |
| 2794 | .stop = elog_seq_stop, |
| 2795 | .show = elog_seq_show, |
| 2796 | }; |
| 2797 | |
| 2798 | static int |
| 2799 | elog_open(struct inode *inode, struct file *filp) |
| 2800 | { |
| 2801 | return seq_open(filp, &elog_seq_ops); |
| 2802 | } |
| 2803 | |
| 2804 | static struct file_operations proc_elog_operations = { |
| 2805 | .open = elog_open, |
| 2806 | .read = seq_read, |
| 2807 | .llseek = seq_lseek, |
| 2808 | .release = seq_release, |
| 2809 | .write = elog_write, |
| 2810 | }; |
| 2811 | |
| 2812 | #endif /* EE_PROC */ |
| 2813 | |
| 2814 | |
| 2815 | |
| 2816 | /* |
| 2817 | ** |
| 2818 | ** Validation hooks. |
| 2819 | ** |
| 2820 | ** ee_list List EEPROM contents to kernel log |
| 2821 | ** ee_wipe Clear EEPROM (after RAS testing) |
| 2822 | ** |
| 2823 | ** Used by validation, exported entry point |
| 2824 | ** Do not enable this in production code. |
| 2825 | ** |
| 2826 | */ |
| 2827 | |
| 2828 | void |
| 2829 | ee_list(void) |
| 2830 | { |
| 2831 | McaHeader hdr; |
| 2832 | McaRecord rec; |
| 2833 | int pos, i; |
| 2834 | |
| 2835 | /* |
| 2836 | * Get I2C bus exclusive access |
| 2837 | */ |
| 2838 | ee_lock(); |
| 2839 | |
| 2840 | /* |
| 2841 | * Read header |
| 2842 | */ |
| 2843 | ee_rd(MR_ELOG_ADDR_LO, 0, (uint8_t *) &hdr, sizeof(hdr)); |
| 2844 | if (! strncmp(hdr.signature, "MCA_LOG", sizeof(hdr.signature))) { |
| 2845 | printk("MCE log header: signature OK, ver %d, type %d\n", |
| 2846 | hdr.header_ver, hdr.hwtype); |
| 2847 | printk("MCE log capacity: %d events, size %d, start %d\n", |
| 2848 | hdr.entries, hdr.rec_size, hdr.rec_start); |
| 2849 | printk("MCE log state: head %d, tail %d, full %d\n", |
| 2850 | hdr.rec_head, hdr.rec_tail, hdr.logfull); |
| 2851 | if (hdr.entries != MR_ELOG_NUM) { |
| 2852 | printk("MCE log check: invalid capacity, expected %ld\n", MR_ELOG_NUM); |
| 2853 | goto ee_bad; |
| 2854 | } |
| 2855 | if (hdr.rec_size != sizeof(McaRecord)) { |
| 2856 | printk("MCE log check: invalid rec size, expected %ld\n", sizeof(McaRecord)); |
| 2857 | goto ee_bad; |
| 2858 | } |
| 2859 | if (hdr.rec_tail != ee_tail || |
| 2860 | hdr.rec_head != ee_head) { |
| 2861 | printk("MCE log check: cached h/t mismatch %d/%d\n", ee_head, ee_tail); |
| 2862 | goto ee_bad; |
| 2863 | } |
| 2864 | if (hdr.entries != ee_num) { |
| 2865 | printk("MCE log check: cached capacity mismatch %d\n", ee_num); |
| 2866 | goto ee_bad; |
| 2867 | } |
| 2868 | |
| 2869 | /* |
| 2870 | * Header looks OK, |
| 2871 | * Dump all valid entries in eeprom |
| 2872 | */ |
| 2873 | for(i = 0; i < hdr.entries; i++) { |
| 2874 | ee_get(&rec, i); |
| 2875 | |
| 2876 | /* |
| 2877 | * Uninitialized parts have all FFs in them, |
| 2878 | * need to screen those before testing the valid bit |
| 2879 | */ |
| 2880 | if (rec.id != 0xffffffff && GET_BIT(31, rec.id)) { |
| 2881 | #if EE_VERIFY |
| 2882 | dmp_hex(&rec, sizeof(rec), "ee_list: Entry[%d]", i); |
| 2883 | #endif |
| 2884 | pos = hdr.rec_start + i * hdr.rec_size; |
| 2885 | printk("Log %4d (pos %06x): id %08x, " |
| 2886 | "ctrl %016llx, stat %016llx, addr %016llx, misc %016llx, time %d\n", |
| 2887 | i, pos, rec.id, rec.ctl, rec.status, |
| 2888 | rec.addr, rec.misc, rec.stamp); |
| 2889 | } |
| 2890 | } |
| 2891 | } |
| 2892 | else { |
| 2893 | printk("MCE log header: bad signature %02x%02x%02x%02x%02x%02x%02x%02x\n", |
| 2894 | hdr.signature[0], hdr.signature[1], hdr.signature[2], hdr.signature[3], |
| 2895 | hdr.signature[4], hdr.signature[5], hdr.signature[6], hdr.signature[7]); |
| 2896 | } |
| 2897 | |
| 2898 | ee_bad: |
| 2899 | /* |
| 2900 | * Release I2C bus exclusive lock |
| 2901 | */ |
| 2902 | ee_unlock(); |
| 2903 | } |
| 2904 | EXPORT_SYMBOL_GPL(ee_list); |
| 2905 | |
| 2906 | void |
| 2907 | ee_wipe(void) |
| 2908 | { |
| 2909 | #if 1 |
| 2910 | printk("Wiping EEPROM disabled, call ignored\n"); |
| 2911 | #else |
| 2912 | ee_mint(); |
| 2913 | #endif |
| 2914 | } |
| 2915 | EXPORT_SYMBOL_GPL(ee_wipe); |
| 2916 | #endif /* CONFIG_MK1OM */ |
| 2917 | |
| 2918 | |
| 2919 | /* |
| 2920 | ** |
| 2921 | ** Setup access to the EEPROM on KnC |
| 2922 | ** This include initializing the local I2C driver and |
| 2923 | ** locating the next write position in the EEPROM. |
| 2924 | ** We want to limit the exception time activity to |
| 2925 | ** a minimum and thus make preparations up front. |
| 2926 | ** This is expected to happen before enabling the |
| 2927 | ** MC event intercepts. |
| 2928 | ** |
| 2929 | */ |
| 2930 | |
| 2931 | int |
| 2932 | ee_init(void) |
| 2933 | { |
| 2934 | #if 0 |
| 2935 | /* |
| 2936 | * Clocking the delay loop. |
| 2937 | * Average results over 3 runs: |
| 2938 | * uSec % off |
| 2939 | * 1 12.46 |
| 2940 | * 2 6.22 |
| 2941 | * 4 4.34 |
| 2942 | * 8 3.41 |
| 2943 | * 16 2.90 |
| 2944 | * 32 2.65 |
| 2945 | * 64 2.52 |
| 2946 | * 128 2.46 |
| 2947 | * 256 2.43 |
| 2948 | * 512 2.41 |
| 2949 | * 1024 2.41 |
| 2950 | * 2048 6.30 |
| 2951 | * 4096 2.43 |
| 2952 | * 8192 3.28 |
| 2953 | * 16384 3.30 |
| 2954 | * 32768 3.42 |
| 2955 | * , which is fine for the purposes in this driver. |
| 2956 | */ |
| 2957 | { |
| 2958 | uint64_t t1, t2; |
| 2959 | uint64_t usec, pwr; |
| 2960 | |
| 2961 | printk("RAS.test: tsc_khz %d\n", tsc_khz); |
| 2962 | for(pwr = 0; pwr < 16; pwr++) { |
| 2963 | usec = 1UL << pwr; |
| 2964 | t1 = rdtsc(); |
| 2965 | myDELAY(usec); |
| 2966 | t2 = rdtsc(); |
| 2967 | printk("RAS.test: myDelay(%lld) => %lld clocks\n", usec, t2 - t1); |
| 2968 | } |
| 2969 | } |
| 2970 | #endif |
| 2971 | |
| 2972 | #ifdef CONFIG_MK1OM |
| 2973 | if (! mce_disabled) { |
| 2974 | McaHeader hdr; |
| 2975 | |
| 2976 | #ifndef CONFIG_I2C_PXA |
| 2977 | /* |
| 2978 | * Reset I2C controller if PXA driver is not included in the kernel. |
| 2979 | */ |
| 2980 | i2c_reset(); |
| 2981 | #endif |
| 2982 | |
| 2983 | /* |
| 2984 | * Get I2C bus exclusive access |
| 2985 | */ |
| 2986 | ee_lock(); |
| 2987 | |
| 2988 | /* |
| 2989 | * Paranoia!! |
| 2990 | * At this point the I2C controller should be inactive and |
| 2991 | * the I2C bus should be idle. Verify this to be true. |
| 2992 | * Note: This check is only applied on this very first |
| 2993 | * access to the I2C controller. If it passed the |
| 2994 | * two criterias we _assume_ we have good hardware. |
| 2995 | * TBD: should we assume that the I2C subsystem can go bad |
| 2996 | * at runtime and add more checking? |
| 2997 | */ |
| 2998 | ee_num = 0; |
| 2999 | if ((reg_read(ISR_OFFSET) & ISR_UB) || (reg_read(IBMR_OFFSET) != 3)) { |
| 3000 | printk("RAS.elog: I2C unit out of control, cannot access EEPROM\n"); |
| 3001 | } |
| 3002 | else { |
| 3003 | /* |
| 3004 | * Get EEPROM header and cache log state. |
| 3005 | */ |
| 3006 | ee_rd(MR_ELOG_ADDR_LO, 0, (uint8_t *) &hdr, sizeof(hdr)); |
| 3007 | if (memcmp(hdr.signature, elog_preset.signature, sizeof(elog_preset.signature)) || |
| 3008 | hdr.header_ver != elog_preset.header_ver || |
| 3009 | hdr.rec_start != elog_preset.rec_start || |
| 3010 | hdr.rec_size != elog_preset.rec_size || |
| 3011 | hdr.hwtype != elog_preset.hwtype) { |
| 3012 | printk("RAS.elog: Found un-initialized EEPROM, initializing ..\n"); |
| 3013 | ee_wr(MR_ELOG_ADDR_LO, 0, (uint8_t *) &elog_preset, sizeof(elog_preset)); |
| 3014 | ee_rd(MR_ELOG_ADDR_LO, 0, (uint8_t *) &hdr, sizeof(hdr)); |
| 3015 | } |
| 3016 | |
| 3017 | if (memcmp(hdr.signature, elog_preset.signature, sizeof(elog_preset.signature)) || |
| 3018 | hdr.header_ver != elog_preset.header_ver || |
| 3019 | hdr.rec_start != elog_preset.rec_start || |
| 3020 | hdr.rec_size != elog_preset.rec_size || |
| 3021 | hdr.hwtype != elog_preset.hwtype) { |
| 3022 | /* |
| 3023 | * Write to EEPROM header failed. |
| 3024 | * Leave a message in the kernel log about it and set capacity to 0. |
| 3025 | */ |
| 3026 | printk("RAS.elog: Error: EEPROM initialization failed!\n"); |
| 3027 | } |
| 3028 | else { |
| 3029 | ee_num = hdr.entries; |
| 3030 | ee_head = hdr.rec_head; |
| 3031 | ee_tail = hdr.rec_tail; |
| 3032 | printk("RAS.elog: rev %d, size %d, head %d, tail %d\n", |
| 3033 | hdr.header_ver, ee_num, ee_head, ee_tail); |
| 3034 | if (ee_head != ee_tail) { |
| 3035 | /* |
| 3036 | *TBD: should we be aggressive and replay these events to the host |
| 3037 | * when it opens the MC SCIF channel to force the issue? |
| 3038 | */ |
| 3039 | printk("RAS.elog: Warning: MCA log has unprocessed entries\n"); |
| 3040 | } |
| 3041 | } |
| 3042 | } |
| 3043 | if (!ee_num) |
| 3044 | printk("RAS.elog: MCA events cannot be logged to EEPROM\n"); |
| 3045 | |
| 3046 | /* |
| 3047 | * Release I2C bus exclusive lock |
| 3048 | */ |
| 3049 | ee_unlock(); |
| 3050 | } |
| 3051 | #endif /* CONFIG_MK1OM */ |
| 3052 | |
| 3053 | /* |
| 3054 | * Reset I2C bus & UART (sort of, internal reset only) |
| 3055 | */ |
| 3056 | xfr_configure(SC16IS_ADDR(SC16IS_ADDR_1, SC16IS_ADDR_0), FREQ_AUTO); |
| 3057 | cons_init(); |
| 3058 | ee_rdy = 1; |
| 3059 | |
| 3060 | #if defined(CONFIG_MK1OM) && EE_PROC |
| 3061 | /* |
| 3062 | * Create proc file |
| 3063 | * We allow writes if EE_INJECT is defined or during manufacturing. |
| 3064 | */ |
| 3065 | { |
| 3066 | int mode; |
| 3067 | #if EE_INJECT |
| 3068 | mode = 0644; |
| 3069 | #else |
| 3070 | uint32_t smc_err, smc_val, smc_fwv; |
| 3071 | |
| 3072 | /* |
| 3073 | * HSD 4846538 |
| 3074 | * Needs SMC FW 1.8 or later to be safe to use. |
| 3075 | * Read FW version; if failed then not at manufacturing. |
| 3076 | * If FW version 1.8 or later go read Zombie register. |
| 3077 | * If zombie register responded we're at manufacturing, |
| 3078 | */ |
| 3079 | mode = 0444; |
| 3080 | smc_err = gmbus_i2c_read(2, 0x28, 0x11, (uint8_t *) &smc_fwv, sizeof(smc_fwv)); |
| 3081 | if (smc_err == sizeof(smc_fwv) && GET_BITS(31, 16, smc_fwv) >= 0x0108) { |
| 3082 | smc_err = gmbus_i2c_read(2, 0x28, 0x1b, (uint8_t *) &smc_val, sizeof(smc_val)); |
| 3083 | if (smc_err == sizeof(uint32_t)) |
| 3084 | mode = 0644; |
| 3085 | } |
| 3086 | if (mode == 0444) |
| 3087 | proc_elog_operations.write = 0; |
| 3088 | #endif |
| 3089 | elog_pe = proc_create("elog", mode, 0, &proc_elog_operations); |
| 3090 | } |
| 3091 | #endif |
| 3092 | |
| 3093 | #if 0 |
| 3094 | /* |
| 3095 | * Say hello on the console |
| 3096 | */ |
| 3097 | ee_printk("RAS: ee_print ready, uart adr %02x\n", |
| 3098 | SC16IS_ADDR(SC16IS_ADDR_1, SC16IS_ADDR_0)); |
| 3099 | #endif |
| 3100 | |
| 3101 | if (mce_disabled) |
| 3102 | printk("RAS.elog: disabled\n"); |
| 3103 | else |
| 3104 | printk("RAS.elog: init complete\n"); |
| 3105 | return 0; |
| 3106 | } |
| 3107 | |
| 3108 | |
| 3109 | /* |
| 3110 | * Cleanup for module unload. |
| 3111 | * Free any resources held by this driver |
| 3112 | */ |
| 3113 | |
| 3114 | int |
| 3115 | ee_exit(void) |
| 3116 | { |
| 3117 | #if defined(CONFIG_MK1OM) && EE_PROC |
| 3118 | if (elog_pe) { |
| 3119 | remove_proc_entry("elog", 0); |
| 3120 | elog_pe = 0; |
| 3121 | } |
| 3122 | #endif |
| 3123 | |
| 3124 | |
| 3125 | /* |
| 3126 | * Reset I2C bus & UART (sort of, internal reset only) |
| 3127 | */ |
| 3128 | ee_rdy = 0; |
| 3129 | xfr_configure(SC16IS_ADDR(SC16IS_ADDR_1, SC16IS_ADDR_0), FREQ_AUTO); |
| 3130 | cons_exit(); |
| 3131 | |
| 3132 | printk("RAS.elog: exit complete\n"); |
| 3133 | return 0; |
| 3134 | } |
| 3135 | |
| 3136 | #endif /* EMULATION */ |