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1 | # ========== Copyright Header Begin ========================================== |
2 | # | |
3 | # OpenSPARC T2 Processor File: user_cfg.scr | |
4 | # Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | # 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | # | |
7 | # * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | # | |
9 | # This program is free software; you can redistribute it and/or modify | |
10 | # it under the terms of the GNU General Public License as published by | |
11 | # the Free Software Foundation; version 2 of the License. | |
12 | # | |
13 | # This program is distributed in the hope that it will be useful, | |
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | # GNU General Public License for more details. | |
17 | # | |
18 | # You should have received a copy of the GNU General Public License | |
19 | # along with this program; if not, write to the Free Software | |
20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | # | |
22 | # For the avoidance of doubt, and except that if any non-GPL license | |
23 | # choice is available it will apply instead, Sun elects to use only | |
24 | # the General Public License version 2 (GPLv2) at this time for any | |
25 | # software where a choice of GPL license versions is made | |
26 | # available with the language indicating that GPLv2 or any later version | |
27 | # may be used, or where a choice of which version of the GPL is applied is | |
28 | # otherwise unspecified. | |
29 | # | |
30 | # Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | # CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | # have any questions. | |
33 | # | |
34 | # ========== Copyright Header End ============================================ | |
35 | source -echo -verbose $dv_root/design/sys/synopsys/script/project_sparc_cfg.scr | |
36 | ||
37 | set rtl_files {\ | |
38 | libs/cl/cl_rtl_ext.v | |
39 | libs/cl/cl_a1/cl_a1.behV | |
40 | libs/cl/cl_u1/cl_u1.behV | |
41 | libs/cl/cl_dp1/cl_dp1.behV | |
42 | libs/cl/cl_sc1/cl_sc1.behV | |
43 | libs/cl/cl_mc1/cl_mc1.v | |
44 | ||
45 | libs/clk/rtl/clkgen_tcu_cmp.v | |
46 | libs/clk/rtl/clkgen_tcu_io.v | |
47 | ||
48 | libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v | |
49 | libs/clk/n2_clk_clstr_hdr1_cust_l/n2_clk_clstr_hdr1_cust/rtl/n2_clk_clstr_hdr1_cust.v | |
50 | libs/clk/n2_clk_pgrid_cust_l/n2_clk_tcu_cmp_cust/rtl/n2_clk_tcu_cmp_cust.v | |
51 | libs/clk/n2_clk_pgrid_cust_l/n2_clk_tcu_io_cust/rtl/n2_clk_tcu_io_cust.v | |
52 | ||
53 | libs/clk/n2_clk_clkchp_4sel_32x_cust_l/n2_clk_clkchp_4sel_32x_cust/rtl/n2_clk_clkchp_4sel_32x_cust.v | |
54 | ||
55 | design/sys/iop/tcu/rtl/tcu.v | |
56 | design/sys/iop/tcu/rtl/tcu_clkseq_ctl.v | |
57 | design/sys/iop/tcu/rtl/tcu_clkstp_ctl.v | |
58 | design/sys/iop/tcu/rtl/tcu_dbg_ctl.v | |
59 | design/sys/iop/tcu/rtl/tcu_dmo_ctl.v | |
60 | design/sys/iop/tcu/rtl/tcu_jtag_ctl.v | |
61 | design/sys/iop/tcu/rtl/tcu_jtag_tap_ctl.v | |
62 | design/sys/iop/tcu/rtl/tcu_mbist_ctl.v | |
63 | design/sys/iop/tcu/rtl/tcu_regs_ctl.v | |
64 | design/sys/iop/tcu/rtl/tcu_sigmux_ctl.v | |
65 | design/sys/iop/tcu/rtl/tcu_ucb_ctl.v | |
66 | design/sys/iop/tcu/rtl/tcu_ucbbusin8_ctl.v | |
67 | design/sys/iop/tcu/rtl/tcu_ucbbusout8_ctl.v | |
68 | } | |
69 | ||
70 | set link_library [concat $link_library \ | |
71 | dw_foundation.sldb \ | |
72 | ] | |
73 | ||
74 | ||
75 | set mix_files {} | |
76 | set top_module tcu | |
77 | ||
78 | set include_paths {\ | |
79 | } | |
80 | ||
81 | set black_box_libs {} | |
82 | set black_box_designs {} | |
83 | set mem_libs {} | |
84 | ||
85 | set dont_touch_modules {\ | |
86 | } | |
87 | ||
88 | set compile_effort "medium" | |
89 | ||
90 | set compile_flatten_all 1 | |
91 | ||
92 | set compile_no_new_cells_at_top_level false | |
93 | ||
94 | set default_clk gclk | |
95 | set default_clk_freq 350 | |
96 | set default_setup_skew 0.0 | |
97 | set default_hold_skew 0.0 | |
98 | set default_clk_transition 0.05 | |
99 | set clk_list { \ | |
100 | { gclk 350.0 0.000 0.000 0.05} \ | |
101 | } | |
102 | ||
103 | set ideal_net_list {} | |
104 | set false_path_list {} | |
105 | set enforce_input_fanout_one 0 | |
106 | set allow_outport_drive_innodes 1 | |
107 | set skip_scan 0 | |
108 | set add_lockup_latch false | |
109 | set chain_count 1 | |
110 | set scanin_port_list {} | |
111 | set scanout_port_list {} | |
112 | set scanenable_port global_shift_enable | |
113 | set has_test_stub 1 | |
114 | set scanenable_pin test_stub_no_bist/se | |
115 | set long_chain_so_0_net long_chain_so_0 | |
116 | set short_chain_so_0_net short_chain_so_0 | |
117 | set so_0_net so_0 | |
118 | set insert_extra_lockup_latch 0 | |
119 | set extra_lockup_latch_clk_list {} |