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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_clk_clstr_hdr2_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `timescale 1 ns/1 ns | |
36 | ||
37 | module n2_clk_clstr_hdr2_cust ( | |
38 | gclk, | |
39 | pc_clk, // new clock input | |
40 | l2clk, | |
41 | cluster_arst_l, | |
42 | tcu_atpg_mode, | |
43 | tcu_wr_inhibit, | |
44 | ccu_div_ph, | |
45 | // cluster_div_en, | |
46 | test_clk_sel, | |
47 | test_clk, | |
48 | pc_clk_sel, | |
49 | scan_in, | |
50 | scan_en, | |
51 | tcu_aclk, | |
52 | tcu_bclk, | |
53 | // ccu_cmp_slow_sync_en, | |
54 | // ccu_slow_cmp_sync_en, | |
55 | tcu_pce_ov, | |
56 | tcu_clk_stop, | |
57 | rst_por_, | |
58 | rst_wmr_, | |
59 | rst_wmr_protect, | |
60 | aclk_wmr, | |
61 | aclk, | |
62 | bclk, | |
63 | // cmp_slow_sync_en, | |
64 | // slow_cmp_sync_en, | |
65 | array_wr_inhibit, | |
66 | pce_ov, | |
67 | por_, | |
68 | wmr_, | |
69 | wmr_protect, | |
70 | scan_out, | |
71 | cclk | |
72 | ); | |
73 | ||
74 | // ******************************* | |
75 | // port declaration | |
76 | // ******************************* | |
77 | ||
78 | input gclk; | |
79 | input pc_clk; | |
80 | input l2clk; | |
81 | input cluster_arst_l; | |
82 | input ccu_div_ph; | |
83 | // input cluster_div_en; | |
84 | input test_clk_sel; | |
85 | input test_clk; | |
86 | input pc_clk_sel; | |
87 | input scan_in; | |
88 | input scan_en; | |
89 | input tcu_aclk; | |
90 | input tcu_bclk; | |
91 | // input ccu_cmp_slow_sync_en; | |
92 | // input ccu_slow_cmp_sync_en; | |
93 | input tcu_pce_ov; | |
94 | input tcu_clk_stop; | |
95 | input rst_por_; | |
96 | input rst_wmr_; | |
97 | input rst_wmr_protect; | |
98 | output aclk_wmr; | |
99 | output aclk; | |
100 | output bclk; | |
101 | // output cmp_slow_sync_en; | |
102 | // output slow_cmp_sync_en; | |
103 | output pce_ov; | |
104 | output por_; | |
105 | output wmr_; | |
106 | output wmr_protect; | |
107 | output scan_out; | |
108 | output cclk; | |
109 | ||
110 | output array_wr_inhibit; | |
111 | input tcu_atpg_mode; | |
112 | input tcu_wr_inhibit; | |
113 | ||
114 | // ******************************* | |
115 | // wire declaration | |
116 | // ******************************* | |
117 | ||
118 | wire gclk; | |
119 | wire l2clk; | |
120 | wire cluster_arst_l; | |
121 | wire ccu_div_ph; | |
122 | // wire cluster_div_en; | |
123 | wire test_clk_sel; | |
124 | wire test_clk; | |
125 | wire pc_clk_sel; | |
126 | wire scan_in; | |
127 | wire scan_en; | |
128 | wire tcu_aclk; | |
129 | wire tcu_bclk; | |
130 | // wire ccu_cmp_slow_sync_en; | |
131 | // wire ccu_slow_cmp_sync_en; | |
132 | wire tcu_pce_ov; | |
133 | wire tcu_clk_stop; | |
134 | wire rst_por_; | |
135 | wire rst_wmr_; | |
136 | wire rst_wmr_protect; | |
137 | wire aclk_wmr; | |
138 | wire aclk; | |
139 | wire bclk; | |
140 | // wire cmp_slow_sync_en; | |
141 | // wire slow_cmp_sync_en; | |
142 | wire pce_ov; | |
143 | wire por_; | |
144 | wire wmr_; | |
145 | wire wmr_protect; | |
146 | wire scan_out; | |
147 | wire cclk; | |
148 | ||
149 | wire tcu_atpg_mode; | |
150 | wire tcu_wr_inhibit; | |
151 | ||
152 | // additional internal nets | |
153 | ||
154 | // assign cluster_arst_l = 1'b1; | |
155 | // assign tcu_wr_inhibit = 1'b0; | |
156 | // assign tcu_atpg_mode = 1'b0; | |
157 | ||
158 | ||
159 | wire div_r; | |
160 | // wire div_f; // vlint | |
161 | ||
162 | // wire cluster_div_en_n; | |
163 | wire test_clk_sel_n; | |
164 | ||
165 | wire cmp_slow_sync_en_q1; | |
166 | wire slow_cmp_sync_en_q1; | |
167 | wire por_q1; | |
168 | wire wmr_q1; | |
169 | ||
170 | wire div_out; | |
171 | // wire div_r_n; // vlint | |
172 | // wire div_f_n; // vlint | |
173 | ||
174 | wire div_or_pc_clk_n; | |
175 | // wire gclk_n; // vlint | |
176 | ||
177 | wire slow_cmp_sync_en_q1n; | |
178 | wire cmp_slow_sync_en_q1n; | |
179 | wire por_q1n; | |
180 | wire wmr_q1n; | |
181 | ||
182 | wire cmp_slow_sync_en_muxed; | |
183 | wire slow_cmp_sync_en_muxed; | |
184 | wire rst_por_muxed; | |
185 | wire rst_wmr_muxed; | |
186 | ||
187 | wire scan_ch1; | |
188 | wire scan_ch2; | |
189 | wire scan_ch3; | |
190 | wire scan_ch4; | |
191 | wire scan_ch5; | |
192 | wire scan_ch6; | |
193 | wire scan_ch7; | |
194 | wire scan_ch8; | |
195 | wire scan_ch9; | |
196 | wire scan_ch10; | |
197 | wire scan_ch11; | |
198 | wire scan_ch12; | |
199 | ||
200 | wire pre_cclk; | |
201 | ||
202 | wire pc_test_clk_muxed; | |
203 | wire pc_clk_sel_gated; | |
204 | wire div_clk_sel_gated; | |
205 | wire mux1_out_sel; | |
206 | wire mux1_out_sel_n; | |
207 | ||
208 | ||
209 | // ********************************************************** | |
210 | // buffered & gated stuff | |
211 | // ********************************************************** | |
212 | ||
213 | cl_u1_buf_1x aclk_buf ( .in( tcu_aclk ), .out ( aclk ) ); | |
214 | cl_u1_buf_1x bclk_buf ( .in( tcu_bclk ), .out ( bclk ) ); | |
215 | cl_u1_buf_1x pce_ov_buf ( .in( tcu_pce_ov ), .out ( pce_ov ) ); | |
216 | cl_u1_buf_1x wmr_protect_buf ( .in( rst_wmr_protect ), .out ( wmr_protect ) ); | |
217 | ||
218 | // assign aclk_gated = aclk & tcu_atpg_mode; | |
219 | // assign bclk_gated = bclk & tcu_atpg_mode; | |
220 | // assign scan_en_gated = scan_en & tcu_atpg_mode; | |
221 | // implemented right here | |
222 | cl_u1_nand2_1x aclk_gated_nand ( .in0 (aclk), .in1 (tcu_atpg_mode), .out (aclk_gated_n) ); | |
223 | cl_u1_nand2_1x bclk_gated_nand ( .in0 (bclk), .in1 (tcu_atpg_mode), .out (bclk_gated_n) ); | |
224 | cl_u1_nand2_1x scan_en_gated_nand ( .in0 (scan_en), .in1 (tcu_atpg_mode), .out (scan_en_gated_n) ); | |
225 | cl_u1_inv_1x aclk_gated_inv ( .in (aclk_gated_n), .out (aclk_gated) ); | |
226 | cl_u1_inv_1x bclk_gated_inv ( .in (bclk_gated_n), .out (bclk_gated) ); | |
227 | cl_u1_inv_1x scan_en_gated_inv ( .in (scan_en_gated_n), .out (scan_en_gated) ); | |
228 | ||
229 | // assign scan_out = tcu_atpg_mode ? scan_out_pre_mux : scan_in ; | |
230 | // implemented below, and as instance "scan_chain_mux" | |
231 | cl_u1_inv_1x tcu_atpg_mode_inv ( .in (tcu_atpg_mode) , .out (tcu_atpg_mode_n) ); | |
232 | ||
233 | ||
234 | // assign aclk_wmr = ~rst_wmr_protect & tcu_aclk; | |
235 | ||
236 | ||
237 | cl_u1_inv_1x wmr_protect_inv ( .in (rst_wmr_protect) , .out (rst_wmr_protect_n) ); | |
238 | ||
239 | cl_u1_nand2_1x aclk_wmr_gate ( | |
240 | .in0 (aclk), | |
241 | .in1 (rst_wmr_protect_n), | |
242 | .out (aclk_wmr_n) | |
243 | ); | |
244 | ||
245 | cl_u1_inv_1x aclk_wmr_inv ( .in (aclk_wmr_n) , .out (aclk_wmr) ); | |
246 | ||
247 | // cl_u1_inv_1x gclk_inv ( .in (gclk) , .out (gclk_n) ); // vlint | |
248 | ||
249 | // ********************************************************** | |
250 | // l1hdr for scan | |
251 | // ********************************************************** | |
252 | ||
253 | n2_clk_clstr_hdr2_l1hdr gclk_header ( | |
254 | .l2clk(gclk), | |
255 | .l1clk(l1gclk), | |
256 | .pce(1'b1), | |
257 | .se(scan_en_gated), | |
258 | .pce_ov(1'b1), | |
259 | .stop(1'b0) // ECO1.2 - not allowed to stop local clocks | |
260 | ); | |
261 | ||
262 | n2_clk_clstr_hdr2_l1hdr l1_header ( | |
263 | .l2clk(l2clk), | |
264 | .l1clk(l1clk), | |
265 | .pce(1'b1), | |
266 | .se(scan_en_gated), | |
267 | .pce_ov(1'b1), | |
268 | .stop(1'b0) // ECO1.3 - false info; no action needed | |
269 | ); | |
270 | ||
271 | // ********************************************************** | |
272 | // make observe flops part of scan chain (observe only) | |
273 | // ********************************************************** | |
274 | ||
275 | n2_clk_clstr_hdr2_obs_flops observe_flops ( | |
276 | .tcu_clk_stop (clk_stop_synced), // .tcu_clk_stop (tcu_clk_stop), | |
277 | .ccu_div_ph (ccu_div_ph), | |
278 | .array_wr_inhibit (array_wr_inhibit), | |
279 | .l1clk (l1gclk), | |
280 | .aclk (aclk_gated), | |
281 | .bclk (bclk_gated), | |
282 | .scan_in (scan_in), | |
283 | .scan_out (scan_ch) | |
284 | ); | |
285 | ||
286 | cl_sc1_aomux2_1x scan_chain_mux ( | |
287 | .sel0 ( tcu_atpg_mode ), | |
288 | .sel1 ( tcu_atpg_mode_n ), | |
289 | .in0 ( scan_out_pre_mux ), | |
290 | .in1 ( scan_in ), | |
291 | .out ( scan_out ) | |
292 | ); | |
293 | ||
294 | // ********************************************************** | |
295 | // synchronize the control signals | |
296 | // ********************************************************** | |
297 | ||
298 | n2_clk_clstr_hdr2_sync control_sig_sync ( | |
299 | // .div_r ( div_r ), | |
300 | .gclk ( l1gclk ), // unused inside sync block | |
301 | .l1clk ( l1clk ), | |
302 | // .ccu_slow_cmp_sync_en ( ccu_slow_cmp_sync_en), | |
303 | // .ccu_cmp_slow_sync_en ( ccu_cmp_slow_sync_en), | |
304 | .rst_por_ ( rst_por_), | |
305 | .rst_wmr_ ( rst_wmr_), | |
306 | .scan_in ( scan_ch ), | |
307 | .aclk ( aclk_gated ), | |
308 | .bclk ( bclk_gated ), | |
309 | // .slow_cmp_sync_en ( slow_cmp_sync_en ), | |
310 | // .cmp_slow_sync_en ( cmp_slow_sync_en ), | |
311 | .por_ ( por_ ), | |
312 | .wmr_ ( wmr_ ), | |
313 | .scan_out ( scan_out_pre_mux ) | |
314 | ); | |
315 | ||
316 | ||
317 | // ********************************************************** | |
318 | // divider & mux model | |
319 | // ********************************************************** | |
320 | ||
321 | wire ccu_div_ph_ff; | |
322 | wire ccu_div_ph_flop_unused; | |
323 | ||
324 | // first flop ccu_div_ph | |
325 | cl_sc1_msff_1x ccu_div_ph_flop ( | |
326 | .d ( ccu_div_ph ), | |
327 | .l1clk ( gclk ), | |
328 | .si ( 1'b0 ), | |
329 | .siclk ( 1'b0 ), | |
330 | .soclk ( 1'b0 ), | |
331 | .q ( ccu_div_ph_ff ), | |
332 | .so (ccu_div_ph_flop_unused) | |
333 | ); | |
334 | ||
335 | ||
336 | ||
337 | // pc_clk_sel_gated = pc_clk_sel & ~test_clk_sel; | |
338 | // mux1_out_sel = pc_clk_sel | test_clk_sel; | |
339 | // mux1_out_sel_n = ~mux1_out_sel; | |
340 | ||
341 | cl_u1_inv_1x test_clk_inv ( .in (test_clk_sel), .out (test_clk_sel_n) ); | |
342 | cl_u1_inv_1x pc_clk_sel_inv ( .in (pc_clk_sel), .out (pc_clk_sel_n) ); | |
343 | ||
344 | cl_u1_nor2_1x pc_clk_sel_gating ( | |
345 | .in0 (pc_clk_sel_n), .in1 (test_clk_sel), .out (pc_clk_sel_gated) ); | |
346 | ||
347 | cl_u1_nor2_1x pc_clk_sel_nor ( | |
348 | .in0 (pc_clk_sel), .in1 (test_clk_sel), .out (mux1_out_sel_n) ); | |
349 | cl_u1_inv_1x mux1_out_sel_inv ( .in (mux1_out_sel_n), .out (mux1_out_sel) ); | |
350 | ||
351 | wire div_out_n; | |
352 | wire divide_flop_unused; | |
353 | ||
354 | // divider retiming | |
355 | cl_u1_buf_1x div_r_buf ( .in (ccu_div_ph_ff), .out (div_r ) ); | |
356 | ||
357 | cl_sc1_msff_1x divide_flop ( | |
358 | .d ( div_r ), | |
359 | .l1clk ( gclk ), | |
360 | .si ( 1'b0 ), | |
361 | .siclk ( 1'b0 ), | |
362 | .soclk ( 1'b0 ), | |
363 | .q ( div_out ), | |
364 | .so (divide_flop_unused) | |
365 | ); | |
366 | ||
367 | cl_u1_inv_1x div_out_inv ( .in (div_out), .out (div_out_n ) ); | |
368 | ||
369 | // pc_clk/test_clk mux | |
370 | cl_sc1_aomux2_1x pc_test_clk_mux ( | |
371 | .sel0 ( pc_clk_sel_gated ), | |
372 | .sel1 ( test_clk_sel ), | |
373 | .in0 ( pc_clk ), | |
374 | .in1 ( test_clk ), | |
375 | .out (pc_test_clk_muxed ) | |
376 | ); | |
377 | ||
378 | // final clk mux output | |
379 | cl_sc1_aomux2_1x final_mux ( | |
380 | .sel0 ( mux1_out_sel ), | |
381 | .sel1 ( mux1_out_sel_n ), | |
382 | .in0 ( pc_test_clk_muxed ), | |
383 | .in1 ( div_out_n ), | |
384 | .out ( div_clk ) | |
385 | ); | |
386 | ||
387 | ||
388 | // ********************************************************** | |
389 | // clkstop for l2clk (via control of cclk) | |
390 | // ********************************************************** | |
391 | wire clk_stop_syncff_unused; | |
392 | // 1. sync up clock stop (these are non-scanned) | |
393 | n2_clk_clstr_hdr2_sync_ff clk_stop_syncff ( | |
394 | .din ( tcu_clk_stop ), | |
395 | .synced ( clk_stop_synced ), | |
396 | .clkin ( div_clk ), // .clkin ( gclk ), | |
397 | .sync_clk ( div_clk ), | |
398 | // .sel ( div_r ), | |
399 | .siclk ( 1'b0 ), | |
400 | .soclk ( 1'b0 ), | |
401 | .si ( 1'b0 ), | |
402 | .so (clk_stop_syncff_unused ) | |
403 | ); | |
404 | ||
405 | wire clk_stop_synced_stg1; | |
406 | wire clk_stop_synced_stg2; | |
407 | ||
408 | // 2. now delay sync'd up clock stop (these are non-scanned) | |
409 | cl_sc1_msff_1x clk_stop_del_stg1 ( | |
410 | .d (clk_stop_synced), .q (clk_stop_synced_stg1), .l1clk (div_clk), | |
411 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so () | |
412 | ); | |
413 | ||
414 | cl_sc1_msff_1x clk_stop_del_stg2 ( | |
415 | .d (clk_stop_synced_stg1), .q (clk_stop_synced_stg2), .l1clk (div_clk), | |
416 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so () | |
417 | ); | |
418 | ||
419 | wire clk_stop_synced_stg2_gated; | |
420 | wire clk_stop_synced_stg2_n; | |
421 | ||
422 | cl_u1_inv_1x clk_stop_stg2_inv ( .in (clk_stop_synced_stg2), .out (clk_stop_synced_stg2_n) ); | |
423 | ||
424 | // ECO1.5 - pushed the gate after the latch in the clk-stop instance "clk_stopper" | |
425 | // cl_u1_nor2_1x clk_stop_stg2_nor ( .in0 (clk_stop_synced_stg2_n), .in1 (tcu_atpg_mode), .out (clk_stop_synced_stg2_gated) ); | |
426 | // | |
427 | // 3. use blatch & and-gate for controlling clock | |
428 | n2_clk_clstr_hdr2_clkgate clk_stopper ( | |
429 | .l2clk(div_clk), | |
430 | .l1clk(pre_cclk), | |
431 | .atpg_mode(tcu_atpg_mode), | |
432 | .clken(clk_stop_synced_stg2_n) | |
433 | ); | |
434 | ||
435 | // 4. finally gate-off with async reset | |
436 | // assign cclk = pre_cclk & cluster_arst_l; | |
437 | ||
438 | cl_u1_nand2_1x cclk_nand ( .in0 (pre_cclk), .in1 (cluster_arst_l), .out (cclk_n) ); | |
439 | cl_u1_inv_1x cclk_inv ( .in (cclk_n), .out (cclk) ); | |
440 | ||
441 | ||
442 | // ********************************************************** | |
443 | // array write inhibit operation | |
444 | // ********************************************************** | |
445 | ||
446 | wire clk_stop_synced_n; | |
447 | ||
448 | wire clk_stop_synced_stg3; | |
449 | wire clk_stop_synced_stg4; | |
450 | wire clk_stop_synced_stg5; | |
451 | ||
452 | wire array_wr_inhibit_n; | |
453 | wire array_wr_inhibit1; | |
454 | wire array_wr_inhibit2; | |
455 | ||
456 | wire array_wr_inhibit1_n; | |
457 | wire array_wr_inhibit2_n; | |
458 | wire cluster_arst; | |
459 | wire clk_stop_del_stg3_unused; | |
460 | wire clk_stop_del_stg4_unused; | |
461 | wire clk_stop_del_stg5_unused; | |
462 | ||
463 | cl_sc1_msff_1x clk_stop_del_stg3 ( | |
464 | .d (clk_stop_synced_stg2), .q (clk_stop_synced_stg3), .l1clk (div_clk), | |
465 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg3_unused) | |
466 | ); | |
467 | ||
468 | cl_sc1_msff_1x clk_stop_del_stg4 ( | |
469 | .d (clk_stop_synced_stg3), .q (clk_stop_synced_stg4), .l1clk (div_clk), | |
470 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg4_unused) | |
471 | ); | |
472 | ||
473 | cl_sc1_msff_1x clk_stop_del_stg5 ( | |
474 | .d (clk_stop_synced_stg4), .q (clk_stop_synced_stg5), .l1clk (div_clk), | |
475 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg5_unused) | |
476 | ); | |
477 | ||
478 | ||
479 | // assign array_wr_inhibit1 = clk_stop_synced & clk_stop_synced_stg5; | |
480 | ||
481 | cl_u1_nand3_1x clk_stop_and_delayed ( // ECO1.4 - changed cl_u1_nand2_1x | |
482 | .in0 (clk_stop_synced), | |
483 | .in1 (clk_stop_synced_stg5), | |
484 | .in2 (tcu_atpg_mode_n), | |
485 | .out (array_wr_inhibit1_n) | |
486 | ); | |
487 | ||
488 | cl_u1_inv_1x array_wr_inhibit1_inv ( .in(array_wr_inhibit1_n), .out(array_wr_inhibit1) ); | |
489 | ||
490 | ||
491 | // assign array_wr_inhibit2 = (~clk_stop_synced) & wr_inhibit_q2; | |
492 | cl_u1_inv_1x clk_stop_synced_inv ( .in(clk_stop_synced), .out(clk_stop_synced_n) ); | |
493 | ||
494 | // ECO1.1 - removed nand gate from path of tcu_wr_inhibit | |
495 | // and replaced with buffer | |
496 | // | |
497 | // cl_u1_nand2_1x clk_stop_synced_and_wr_inhibit_q2 ( | |
498 | // .in0 (clk_stop_synced_n), | |
499 | // .in1 (tcu_wr_inhibit), // (wr_inhibit_q2), | |
500 | // .out (array_wr_inhibit2_n) | |
501 | // ); | |
502 | // | |
503 | // cl_u1_inv_1x array_wr_inhibit2_inv ( .in(array_wr_inhibit2_n), .out(array_wr_inhibit2) ); | |
504 | cl_u1_buf_1x array_wr_inhibit2_buf ( .in(tcu_wr_inhibit), .out(array_wr_inhibit2) ); | |
505 | ||
506 | ||
507 | // assign array_wr_inhibit = array_wr_inhibit1 | array_wr_inhibit2 | (~cluster_arst_l); | |
508 | ||
509 | cl_u1_inv_1x cluster_arst_inv (.in (cluster_arst_l), .out (cluster_arst)); | |
510 | ||
511 | cl_u1_nor3_1x array_wr_inhibit_nor ( | |
512 | .in0 (array_wr_inhibit1), | |
513 | .in1 (array_wr_inhibit2), | |
514 | .in2 (cluster_arst), | |
515 | .out (array_wr_inhibit_n) | |
516 | ); | |
517 | ||
518 | cl_u1_inv_1x array_wr_inhibit_inv (.in (array_wr_inhibit_n), .out (array_wr_inhibit)); | |
519 | ||
520 | endmodule // n2_clk_clstr_hdr2_cust | |
521 | ||
522 | ||
523 | ||
524 | ||
525 | // ********************************************************** | |
526 | // (fictitous) observe flop module for ATPG purposes | |
527 | // ********************************************************** | |
528 | ||
529 | module n2_clk_clstr_hdr2_obs_flops ( | |
530 | tcu_clk_stop, | |
531 | ccu_div_ph, | |
532 | array_wr_inhibit, | |
533 | l1clk, | |
534 | aclk, | |
535 | bclk, | |
536 | scan_in, | |
537 | scan_out | |
538 | ); | |
539 | ||
540 | input tcu_clk_stop; | |
541 | input ccu_div_ph; | |
542 | input array_wr_inhibit; | |
543 | input l1clk; | |
544 | input aclk; | |
545 | input bclk; | |
546 | input scan_in; | |
547 | output scan_out; | |
548 | ||
549 | wire tcu_clk_stop; | |
550 | wire ccu_div_ph; | |
551 | wire array_wr_inhibit; | |
552 | wire l1clk; | |
553 | wire aclk; | |
554 | wire bclk; | |
555 | wire scan_in; | |
556 | wire scan_out; | |
557 | ||
558 | wire scan_ch1; | |
559 | wire scan_ch2; | |
560 | wire obs_ff1_unused; | |
561 | wire obs_ff2_unused; | |
562 | wire obs_ff3_unused; | |
563 | ||
564 | cl_sc1_msff_1x obs_ff1 ( | |
565 | .d ( tcu_clk_stop ), | |
566 | .l1clk ( l1clk ), | |
567 | .si ( scan_in ), | |
568 | .siclk ( aclk ), | |
569 | .soclk ( bclk ), | |
570 | .q (obs_ff1_unused ), | |
571 | .so ( scan_ch1 ) | |
572 | ); | |
573 | ||
574 | cl_sc1_msff_1x obs_ff2 ( | |
575 | .d ( ccu_div_ph ), | |
576 | .l1clk ( l1clk ), | |
577 | .si ( scan_ch1 ), | |
578 | .siclk ( aclk ), | |
579 | .soclk ( bclk ), | |
580 | .q (obs_ff2_unused ), | |
581 | .so ( scan_ch2 ) | |
582 | ); | |
583 | ||
584 | cl_sc1_msff_1x obs_ff3 ( | |
585 | .d ( array_wr_inhibit ), | |
586 | .l1clk ( l1clk ), | |
587 | .si ( scan_ch2 ), | |
588 | .siclk ( aclk ), | |
589 | .soclk ( bclk ), | |
590 | .q (obs_ff3_unused ), | |
591 | .so ( scan_out ) | |
592 | ); | |
593 | endmodule // n2_clk_clstr_hdr2_obs_flops | |
594 | ||
595 | ||
596 | // ********************************************************** | |
597 | // (fictitous) synchronizer module for ATPG purposes | |
598 | // ********************************************************** | |
599 | ||
600 | module n2_clk_clstr_hdr2_sync ( | |
601 | // div_r, | |
602 | gclk, | |
603 | l1clk, | |
604 | // ccu_slow_cmp_sync_en , | |
605 | // ccu_cmp_slow_sync_en , | |
606 | rst_por_ , | |
607 | rst_wmr_ , | |
608 | scan_in, | |
609 | aclk, | |
610 | bclk, | |
611 | // slow_cmp_sync_en, | |
612 | // cmp_slow_sync_en, | |
613 | por_, | |
614 | wmr_, | |
615 | scan_out | |
616 | ); | |
617 | ||
618 | ||
619 | // input div_r; | |
620 | input gclk; | |
621 | input l1clk; | |
622 | // input ccu_slow_cmp_sync_en ; | |
623 | // input ccu_cmp_slow_sync_en ; | |
624 | input rst_por_ ; | |
625 | input rst_wmr_ ; | |
626 | input scan_in; | |
627 | input aclk; | |
628 | input bclk; | |
629 | ||
630 | // output slow_cmp_sync_en; | |
631 | // output cmp_slow_sync_en; | |
632 | output por_; | |
633 | output wmr_; | |
634 | output scan_out; | |
635 | ||
636 | // wire div_r; | |
637 | // wire div_r_n; | |
638 | wire gclk; | |
639 | // wire gclk_n; // vlint | |
640 | wire l1clk; | |
641 | ||
642 | // wire ccu_slow_cmp_sync_en ; | |
643 | // wire slow_cmp_sync_en; | |
644 | // wire ccu_cmp_slow_sync_en ; | |
645 | // wire cmp_slow_sync_en; | |
646 | wire rst_por_ ; | |
647 | wire por_; | |
648 | ||
649 | wire rst_wmr_ ; | |
650 | wire wmr_; | |
651 | ||
652 | wire scan_in; | |
653 | wire scan_out; | |
654 | wire aclk; | |
655 | wire bclk; | |
656 | ||
657 | wire scan_ch1; | |
658 | ||
659 | ||
660 | // por_ | |
661 | n2_clk_clstr_hdr2_sync_ff por_syncff ( | |
662 | .din ( rst_por_ ), | |
663 | .synced ( por_ ), | |
664 | .clkin ( l1clk ), // .clkin ( gclk ), | |
665 | .sync_clk ( l1clk ), | |
666 | // .sel ( div_r ), | |
667 | .siclk ( aclk ), | |
668 | .soclk ( bclk ), | |
669 | .si ( scan_in ), | |
670 | .so ( scan_ch1 ) | |
671 | ); | |
672 | ||
673 | // wmr_ | |
674 | n2_clk_clstr_hdr2_sync_ff wmr_syncff ( | |
675 | .din ( rst_wmr_ ), | |
676 | .synced ( wmr_ ), | |
677 | .clkin ( l1clk ), // .clkin ( gclk ), | |
678 | .sync_clk ( l1clk ), | |
679 | // .sel ( div_r ), | |
680 | .siclk ( aclk ), | |
681 | .soclk ( bclk ), | |
682 | .si ( scan_ch1 ), | |
683 | .so ( scan_out ) | |
684 | ); | |
685 | ||
686 | endmodule // n2_clk_clstr_hdr2_sync | |
687 | ||
688 | ||
689 | // ********************************************************** | |
690 | // (fictitous) 1-bit synchronizer for ATPG purposes | |
691 | // ********************************************************** | |
692 | ||
693 | module n2_clk_clstr_hdr2_sync_ff ( | |
694 | din, | |
695 | synced, | |
696 | clkin, | |
697 | sync_clk, | |
698 | // sel, | |
699 | siclk, | |
700 | soclk, | |
701 | si, | |
702 | so | |
703 | ); | |
704 | ||
705 | input din; | |
706 | output synced; | |
707 | input clkin; | |
708 | input sync_clk; | |
709 | input siclk; | |
710 | input soclk; | |
711 | input si; | |
712 | output so; | |
713 | // input sel; | |
714 | ||
715 | wire din; | |
716 | wire synced; | |
717 | wire clkin; | |
718 | wire sync_clk; | |
719 | wire siclk; | |
720 | wire soclk; | |
721 | wire si; | |
722 | wire so; | |
723 | // wire sel; | |
724 | ||
725 | wire so_tmp; | |
726 | // wire sel_n; | |
727 | ||
728 | /* | |
729 | cl_u1_inv_1x sel_inv ( .in(sel), .out(sel_n) ); | |
730 | ||
731 | cl_sc1_aomux2_1x sync_mux1 ( | |
732 | .sel0 ( sel_n ), | |
733 | .sel1 ( sel ), | |
734 | .in0 ( din_q1 ), | |
735 | .in1 ( din ), | |
736 | .out ( din_muxed ) | |
737 | ); | |
738 | */ | |
739 | ||
740 | cl_sc1_msff_1x din_stg1 ( | |
741 | .d ( din ), // .d ( din_muxed ), | |
742 | .l1clk ( clkin ), | |
743 | .si ( si ), | |
744 | .siclk ( siclk ), | |
745 | .soclk ( soclk ), | |
746 | .q ( din_q1 ), | |
747 | .so ( so_tmp ) | |
748 | ); | |
749 | ||
750 | cl_sc1_msff_1x din_stg2 ( | |
751 | .d ( din_q1 ), | |
752 | .l1clk ( sync_clk ), | |
753 | .si ( so_tmp ), | |
754 | .siclk ( siclk ), | |
755 | .soclk ( soclk ), | |
756 | .q ( synced ), | |
757 | .so ( so ) | |
758 | ); | |
759 | ||
760 | endmodule // n2_clk_clstr_hdr2_sync_ff | |
761 | ||
762 | ||
763 | module n2_clk_clstr_hdr2_clkgate ( | |
764 | atpg_mode, | |
765 | clken, | |
766 | l2clk, | |
767 | l1clk | |
768 | ); | |
769 | ||
770 | input atpg_mode; | |
771 | input clken; // clken, active high | |
772 | input l2clk; // level 2 clock, from clock grid | |
773 | output l1clk; | |
774 | ||
775 | wire atpg_mode, clken, l2clk, l1clk; | |
776 | ||
777 | wire clken_gated; | |
778 | wire clken_gated_n; | |
779 | wire l1clk_n; | |
780 | wire clken_lat; | |
781 | wire so_unused; | |
782 | ||
783 | cl_sc1_blatch_4x blatch ( | |
784 | .latout(clken_lat), .d(clken), .l1clk (l2clk), | |
785 | .so (so_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0) ); | |
786 | ||
787 | cl_u1_nor2_1x clken_nor ( .in0(clken_lat), .in1(atpg_mode), .out(clken_gated_n) ); | |
788 | cl_u1_inv_1x clken_gated_inv ( .in(clken_gated_n), .out(clken_gated) ); | |
789 | ||
790 | cl_u1_nand2_1x clk_nand ( .in0(clken_gated), .in1(l2clk), .out(l1clk_n) ); | |
791 | cl_u1_inv_1x clk_inv ( .in(l1clk_n), .out(l1clk) ); | |
792 | ||
793 | endmodule // n2_clk_clstr_hdr2_clkgate | |
794 | ||
795 | module n2_clk_clstr_hdr2_l1hdr ( | |
796 | l2clk, | |
797 | se, | |
798 | pce, | |
799 | pce_ov, | |
800 | stop, | |
801 | l1clk | |
802 | ); | |
803 | ||
804 | input l2clk; // level 2 clock, from clock grid | |
805 | input se; // Scan Enable | |
806 | input pce; // Clock enable for local power savings | |
807 | input pce_ov; // TCU sourced clock enable override for testing | |
808 | input stop; // TCU/CCU sourced clock stop for debug | |
809 | output l1clk; | |
810 | ||
811 | reg l1en; | |
812 | ||
813 | always @ (l2clk or stop or pce or pce_ov ) begin // vlint fix - latch model | |
814 | if (!l2clk) | |
815 | l1en = (~stop & ( pce | pce_ov )); // vlint fix - replaced w/blocking | |
816 | end | |
817 | ||
818 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
819 | ||
820 | endmodule // n2_clk_clstr_hdr2_l1hdr | |
821 | ||
822 |