| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_iss_fsm.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_iss_fsm ( |
| 36 | |
| 37 | // Clock and Reset |
| 38 | |
| 39 | clk, |
| 40 | rst_l, |
| 41 | |
| 42 | // HW State Update Access Interface |
| 43 | |
| 44 | int_detected, |
| 45 | int_scheduled, |
| 46 | |
| 47 | // SW CSR State Update Access Interface |
| 48 | |
| 49 | sw_wr, |
| 50 | sw_addr_sel, |
| 51 | sw_wr_data, |
| 52 | |
| 53 | //Mondo State Status Signal |
| 54 | |
| 55 | mondo_state |
| 56 | |
| 57 | ); |
| 58 | |
| 59 | //############################################################################ |
| 60 | // PORT DECLARATIONS |
| 61 | //############################################################################ |
| 62 | |
| 63 | //------------------------------------------------------------------------ |
| 64 | // Clock and Reset Signals |
| 65 | //------------------------------------------------------------------------ |
| 66 | |
| 67 | input clk; |
| 68 | input rst_l; |
| 69 | |
| 70 | |
| 71 | //------------------------------------------------------------------------ |
| 72 | // Hw State Update Access Signals |
| 73 | //------------------------------------------------------------------------ |
| 74 | |
| 75 | input int_detected; |
| 76 | input int_scheduled; |
| 77 | |
| 78 | //------------------------------------------------------------------------ |
| 79 | // SW CSR State Update Access Interface |
| 80 | //------------------------------------------------------------------------ |
| 81 | |
| 82 | input sw_wr; |
| 83 | input sw_addr_sel; |
| 84 | input [1:0] sw_wr_data; |
| 85 | |
| 86 | |
| 87 | |
| 88 | //------------------------------------------------------------------------ |
| 89 | // Mondo State Status Signals |
| 90 | //------------------------------------------------------------------------ |
| 91 | |
| 92 | output [1:0] mondo_state; |
| 93 | |
| 94 | //############################################################################ |
| 95 | // PARAMETERS |
| 96 | //############################################################################ |
| 97 | |
| 98 | parameter IDLE = 2'b00; |
| 99 | parameter RECEIVED = 2'b01; |
| 100 | parameter PENDING = 2'b11; |
| 101 | |
| 102 | |
| 103 | //############################################################################ |
| 104 | // SIGNAL DECLARATIONS |
| 105 | //############################################################################ |
| 106 | |
| 107 | //------------------------ |
| 108 | // Wires |
| 109 | //------------------------ |
| 110 | wire go_sw_idle; // Signal for when CSR to IDLE is done by SW |
| 111 | wire go_sw_received; // Signal for when CSR to RECEIVED is done by SW |
| 112 | wire go_sw_pending; // Signal for when CSR to PENDING is done by SW |
| 113 | |
| 114 | //------------------------- |
| 115 | // Regs that are NOT flops |
| 116 | //------------------------- |
| 117 | |
| 118 | reg [1:0] n_state; |
| 119 | |
| 120 | //------------------------ |
| 121 | // Regs that are flops |
| 122 | //------------------------ |
| 123 | |
| 124 | reg [1:0] state; |
| 125 | |
| 126 | |
| 127 | //############################################################################ |
| 128 | // ZERO IN CHECKERS |
| 129 | //############################################################################ |
| 130 | //--------------------------------------------------------------------- |
| 131 | // State Machine Checkers |
| 132 | //--------------------------------------------------------------------- |
| 133 | //0in state_transition -var state -val IDLE -next RECEIVED PENDING |
| 134 | //0in state_transition -var state -val RECEIVED -next PENDING IDLE |
| 135 | //0in state_transition -var state -val PENDING -next IDLE RECEIVED |
| 136 | |
| 137 | |
| 138 | //############################################################################ |
| 139 | // COMBINATIONAL LOGIC |
| 140 | //############################################################################ |
| 141 | |
| 142 | //------------------------ |
| 143 | // Assign the Output |
| 144 | //------------------------ |
| 145 | |
| 146 | assign mondo_state = state; |
| 147 | |
| 148 | //--------------------------------------------------------------------- |
| 149 | // The signals which cause state transistions for HW and SW |
| 150 | //--------------------------------------------------------------------- |
| 151 | assign go_sw_idle = sw_addr_sel & sw_wr & ~sw_wr_data[1] & ~sw_wr_data[0]; |
| 152 | assign go_sw_received = sw_addr_sel & sw_wr & ~sw_wr_data[1] & sw_wr_data[0]; |
| 153 | assign go_sw_pending = sw_addr_sel & sw_wr & sw_wr_data[1] & sw_wr_data[0]; |
| 154 | |
| 155 | |
| 156 | //############################################################################ |
| 157 | // SEQUENTIAL LOGIC |
| 158 | //############################################################################ |
| 159 | |
| 160 | //----------------------------------------------------------------------- |
| 161 | // Next State Logic, Assign next state to current state |
| 162 | //----------------------------------------------------------------------- |
| 163 | always @ (posedge clk) |
| 164 | if (!rst_l) |
| 165 | state <= IDLE; |
| 166 | else |
| 167 | state <= n_state; |
| 168 | |
| 169 | //----------------------------------------------------------------------- |
| 170 | // FSM Combination Logic |
| 171 | //----------------------------------------------------------------------- |
| 172 | |
| 173 | always @ (state or go_sw_received or go_sw_pending or int_detected or go_sw_idle |
| 174 | or int_scheduled ) |
| 175 | case (state) // synopsys parallel_case |
| 176 | |
| 177 | //******************************************************** |
| 178 | // |
| 179 | // IDLE STATE |
| 180 | // |
| 181 | // - Wait here until |
| 182 | // - HW receives and interrupt (Active Low) |
| 183 | // - or SW PIO directs us to another state |
| 184 | // |
| 185 | // - Software gets priority |
| 186 | // |
| 187 | //******************************************************** |
| 188 | |
| 189 | |
| 190 | IDLE: |
| 191 | begin |
| 192 | |
| 193 | if (go_sw_pending) // Software PIO to PENDING |
| 194 | n_state = PENDING; |
| 195 | else if (go_sw_received | ~int_detected) // Software PIO to RECEIVED or HW detects an int |
| 196 | n_state = RECEIVED; |
| 197 | else // Software PIO to IDLE or nothing happens |
| 198 | n_state = IDLE; |
| 199 | |
| 200 | end |
| 201 | |
| 202 | |
| 203 | //******************************************************** |
| 204 | // |
| 205 | // RECEIVED STATE |
| 206 | // |
| 207 | // - Wait here until |
| 208 | // - HW can process the RECEIVED interrupt |
| 209 | // - or SW PIO directs us to another state |
| 210 | // |
| 211 | // - Software gets priority |
| 212 | // |
| 213 | //******************************************************** |
| 214 | |
| 215 | |
| 216 | RECEIVED: |
| 217 | begin |
| 218 | |
| 219 | if (go_sw_idle) // Software PIO to IDLE |
| 220 | n_state = IDLE; |
| 221 | else if (go_sw_pending | int_scheduled) // Software PIO to PENDING or HW detects an int |
| 222 | n_state = PENDING; |
| 223 | else // Software PIO to RECEIVED or nothing happens |
| 224 | n_state = RECEIVED; |
| 225 | |
| 226 | end |
| 227 | |
| 228 | //******************************************************** |
| 229 | // |
| 230 | // PENDING STATE |
| 231 | // |
| 232 | // - Wait here until |
| 233 | // - SW PIO directs us to another state |
| 234 | // |
| 235 | //******************************************************** |
| 236 | |
| 237 | PENDING: |
| 238 | begin |
| 239 | |
| 240 | if (go_sw_idle) // Software PIO to IDLE |
| 241 | n_state = IDLE; |
| 242 | else if (go_sw_received) // Software PIO to RECEIVED |
| 243 | n_state = RECEIVED; |
| 244 | else // Software PIO to PENDNIG or nothing happens |
| 245 | n_state = PENDING; |
| 246 | |
| 247 | end |
| 248 | |
| 249 | |
| 250 | //******************************************************** |
| 251 | // |
| 252 | // DEFAULT STATE |
| 253 | // |
| 254 | // - Go to IDLE |
| 255 | //******************************************************** |
| 256 | |
| 257 | default: |
| 258 | |
| 259 | begin |
| 260 | n_state = IDLE; //0in < fire -message "Illegal State Reached in module fire_dlc_imu_iss_fsm.v" |
| 261 | |
| 262 | end |
| 263 | |
| 264 | endcase |
| 265 | endmodule |