| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: n2_stb_cm_64x45_cust.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module n2_stb_cm_64x45_cust ( |
| 36 | stb_cam_rw_ptr, |
| 37 | stb_cam_rw_tid, |
| 38 | stb_cam_wptr_vld, |
| 39 | stb_cam_rptr_vld, |
| 40 | stb_camwr_data, |
| 41 | stb_cam_vld, |
| 42 | stb_cam_cm_tid, |
| 43 | stb_cam_line_en, |
| 44 | stb_quad_ld_cam, |
| 45 | stb_rdata_ramc, |
| 46 | stb_ld_partial_raw, |
| 47 | stb_cam_hit_ptr, |
| 48 | stb_cam_hit, |
| 49 | stb_cam_mhit, |
| 50 | l2clk, |
| 51 | scan_in, |
| 52 | tcu_pce_ov, |
| 53 | tcu_aclk, |
| 54 | tcu_bclk, |
| 55 | tcu_scan_en, |
| 56 | tcu_se_scancollar_in, |
| 57 | tcu_se_scancollar_out, |
| 58 | tcu_array_wr_inhibit, |
| 59 | pce, |
| 60 | scan_out); |
| 61 | wire l1clk_in; |
| 62 | wire l1clk_out; |
| 63 | wire l1clk_free; |
| 64 | wire [44:0] stb_rdata; |
| 65 | wire [44:0] stb_rdata_; |
| 66 | wire [44:0] stb_rdata_ramc_; |
| 67 | wire dff_out_mask_scanin; |
| 68 | wire dff_out_mask_scanout; |
| 69 | wire mo_din_scanin; |
| 70 | wire mo_din_scanout; |
| 71 | wire [2:0] cam_rw_tid; |
| 72 | wire [2:0] cam_rw_ptr; |
| 73 | wire rptr_vld; |
| 74 | wire wptr_vld; |
| 75 | wire [7:0] mo_din_q_unused; |
| 76 | wire [7:0] mo_din_q_l_unused; |
| 77 | wire [7:0] mo_din_mq_l_unused; |
| 78 | wire cam_vld_din_scanin; |
| 79 | wire cam_vld_din_scanout; |
| 80 | wire cam_vld; |
| 81 | wire cam_vld_din_q_unused; |
| 82 | wire cam_vld_din_q_l_unused; |
| 83 | wire cam_tid_din_scanin; |
| 84 | wire cam_tid_din_scanout; |
| 85 | wire [2:0] cam_cm_tid; |
| 86 | wire dff_out_addr_scanin; |
| 87 | wire dff_out_addr_scanout; |
| 88 | wire [45:0] camwr_din_scanin; |
| 89 | wire [45:0] camwr_din_scanout; |
| 90 | wire [44:0] camwr_data; |
| 91 | wire cam_ldq; |
| 92 | wire [45:0] camwr_din_q_unused; |
| 93 | wire [45:0] camwr_din_q_l_unused; |
| 94 | |
| 95 | |
| 96 | input [2:0] stb_cam_rw_ptr ; // wr pointer for single port. |
| 97 | input [2:0] stb_cam_rw_tid ; // thread id for rw. |
| 98 | input stb_cam_wptr_vld ; // write pointer vld |
| 99 | input stb_cam_rptr_vld ; // read pointer vld |
| 100 | |
| 101 | input [44:0] stb_camwr_data ; // data for compare/write |
| 102 | input stb_cam_vld ; // cam is required. |
| 103 | input [2:0] stb_cam_cm_tid ; // thread id for cam operation. |
| 104 | input [7:0] stb_cam_line_en; // mask for squashing cam results (unflopped input) |
| 105 | |
| 106 | input stb_quad_ld_cam ; // quad-ld cam. |
| 107 | |
| 108 | |
| 109 | output [44:0] stb_rdata_ramc ; // rd data from CAM RAM. |
| 110 | output stb_ld_partial_raw ; // ld with partial raw. |
| 111 | output [2:0] stb_cam_hit_ptr ; |
| 112 | output stb_cam_hit ; // any hit in stb |
| 113 | output stb_cam_mhit ; // multiple hits in stb |
| 114 | |
| 115 | input l2clk; |
| 116 | input scan_in; |
| 117 | input tcu_pce_ov; |
| 118 | input tcu_aclk; |
| 119 | input tcu_bclk; |
| 120 | input tcu_scan_en; |
| 121 | input tcu_se_scancollar_in; |
| 122 | input tcu_se_scancollar_out; |
| 123 | input tcu_array_wr_inhibit; |
| 124 | input pce; |
| 125 | output scan_out; |
| 126 | |
| 127 | `ifndef FPGA |
| 128 | // synopsys translate_off |
| 129 | `endif |
| 130 | |
| 131 | wire pce_ov = tcu_pce_ov; |
| 132 | wire stop = 1'b0; |
| 133 | wire siclk = tcu_aclk ; |
| 134 | wire soclk = tcu_bclk; |
| 135 | |
| 136 | integer i,l; |
| 137 | |
| 138 | //================================================ |
| 139 | // Clock headers |
| 140 | //================================================ |
| 141 | n2_stb_cm_64x45_cust_l1clkhdr_ctl_macro l1ch_in ( |
| 142 | .l2clk (l2clk), |
| 143 | .l1en (pce), |
| 144 | .se (tcu_se_scancollar_in), |
| 145 | .l1clk (l1clk_in), |
| 146 | .pce_ov(pce_ov), |
| 147 | .stop(stop) |
| 148 | ); |
| 149 | |
| 150 | n2_stb_cm_64x45_cust_l1clkhdr_ctl_macro l1ch_out ( |
| 151 | .l2clk (l2clk), |
| 152 | .l1en (pce), |
| 153 | .se (tcu_se_scancollar_out), |
| 154 | .l1clk (l1clk_out), |
| 155 | .pce_ov(pce_ov), |
| 156 | .stop(stop) |
| 157 | ); |
| 158 | |
| 159 | n2_stb_cm_64x45_cust_l1clkhdr_ctl_macro l1ch_free ( |
| 160 | .l2clk (l2clk), |
| 161 | .l1en (pce), |
| 162 | .se (tcu_scan_en), |
| 163 | .l1clk (l1clk_free), |
| 164 | .pce_ov(pce_ov), |
| 165 | .stop(stop) |
| 166 | ); |
| 167 | |
| 168 | /////////////////////////////////////////////////////////////// |
| 169 | // Input/output flops/latches |
| 170 | /////////////////////////////////////////////////////////////// |
| 171 | |
| 172 | // Output flops are inverted. |
| 173 | n2_stb_cm_64x45_cust_inv_macro__width_45 rdata_in_inv ( |
| 174 | .din (stb_rdata[44:0]), |
| 175 | .dout (stb_rdata_[44:0]) |
| 176 | ); |
| 177 | n2_stb_cm_64x45_cust_inv_macro__width_45 rdata_out_inv ( |
| 178 | .din (stb_rdata_ramc_[44:0]), |
| 179 | .dout (stb_rdata_ramc[44:0]) |
| 180 | ); |
| 181 | |
| 182 | n2_stb_cm_64x45_cust_msff_ctl_macro__width_8 dff_out_mask ( |
| 183 | .scan_in(dff_out_mask_scanin), |
| 184 | .scan_out(dff_out_mask_scanout), |
| 185 | .l1clk (l1clk_out), |
| 186 | .din (stb_rdata_[7:0]), |
| 187 | .dout (stb_rdata_ramc_[7:0]), |
| 188 | .siclk(siclk), |
| 189 | .soclk(soclk) |
| 190 | ); |
| 191 | |
| 192 | n2_stb_cm_64x45_cust_sram_msff_mo_macro__width_8 mo_din ( |
| 193 | .scan_in(mo_din_scanin), |
| 194 | .scan_out(mo_din_scanout), |
| 195 | .l1clk (l1clk_in), |
| 196 | .and_clk(l1clk_free), |
| 197 | .d ({stb_cam_rw_tid[2:0],stb_cam_rw_ptr[2:0],stb_cam_rptr_vld,stb_cam_wptr_vld}), |
| 198 | .mq ({cam_rw_tid[2:0], cam_rw_ptr[2:0], rptr_vld, wptr_vld}), |
| 199 | .q (mo_din_q_unused[7:0]), |
| 200 | .q_l ( mo_din_q_l_unused[7:0]), |
| 201 | .mq_l ( mo_din_mq_l_unused[7:0]), |
| 202 | .siclk(siclk), |
| 203 | .soclk(soclk) |
| 204 | ); |
| 205 | |
| 206 | n2_stb_cm_64x45_cust_scm_msff_lat_macro__width_1 cam_vld_din ( |
| 207 | .scan_in(cam_vld_din_scanin), |
| 208 | .scan_out(cam_vld_din_scanout), |
| 209 | .l1clk (l1clk_in), |
| 210 | .d (stb_cam_vld), |
| 211 | .latout (cam_vld), |
| 212 | .q ( cam_vld_din_q_unused), |
| 213 | .q_l ( cam_vld_din_q_l_unused), |
| 214 | .siclk(siclk), |
| 215 | .soclk(soclk) |
| 216 | ); |
| 217 | |
| 218 | n2_stb_cm_64x45_cust_msff_ctl_macro__width_3 cam_tid_din ( |
| 219 | .scan_in(cam_tid_din_scanin), |
| 220 | .scan_out(cam_tid_din_scanout), |
| 221 | .l1clk (l1clk_in), |
| 222 | .din (stb_cam_cm_tid[2:0]), |
| 223 | .dout (cam_cm_tid[2:0]), |
| 224 | .siclk(siclk), |
| 225 | .soclk(soclk) |
| 226 | ); |
| 227 | |
| 228 | n2_stb_cm_64x45_cust_msff_ctl_macro__width_37 dff_out_addr ( |
| 229 | .scan_in(dff_out_addr_scanin), |
| 230 | .scan_out(dff_out_addr_scanout), |
| 231 | .l1clk (l1clk_out), |
| 232 | .din (stb_rdata_[44:8]), |
| 233 | .dout (stb_rdata_ramc_[44:8]), |
| 234 | .siclk(siclk), |
| 235 | .soclk(soclk) |
| 236 | ); |
| 237 | |
| 238 | n2_stb_cm_64x45_cust_scm_msff_lat_macro__fs_1__width_46 camwr_din ( |
| 239 | .scan_in(camwr_din_scanin[45:0]), |
| 240 | .scan_out(camwr_din_scanout[45:0]), |
| 241 | .l1clk (l1clk_in), |
| 242 | .d ({stb_camwr_data[44:0],stb_quad_ld_cam}), |
| 243 | .latout ({ camwr_data[44:0],cam_ldq}), |
| 244 | .q (camwr_din_q_unused[45:0]), |
| 245 | .q_l (camwr_din_q_l_unused[45:0]), |
| 246 | .siclk(siclk), |
| 247 | .soclk(soclk) |
| 248 | ); |
| 249 | |
| 250 | // 0in bits_on -var {wptr_vld,rptr_vld} -max 1 |
| 251 | // 0in bits_on -var {wptr_vld,cam_vld} -max 1 |
| 252 | |
| 253 | n2_stb_cm_64x45_array cam_array ( |
| 254 | .cam_line_en (stb_cam_line_en[7:0]), |
| 255 | .clk (l1clk_free), |
| 256 | .cam_rw_ptr(cam_rw_ptr[2:0]), |
| 257 | .cam_rw_tid(cam_rw_tid[2:0]), |
| 258 | .wptr_vld(wptr_vld), |
| 259 | .rptr_vld(rptr_vld), |
| 260 | .camwr_data(camwr_data[44:0]), |
| 261 | .cam_vld(cam_vld), |
| 262 | .cam_cm_tid(cam_cm_tid[2:0]), |
| 263 | .cam_ldq(cam_ldq), |
| 264 | .stb_rdata(stb_rdata[44:0]), |
| 265 | .stb_ld_partial_raw(stb_ld_partial_raw), |
| 266 | .stb_cam_hit_ptr(stb_cam_hit_ptr[2:0]), |
| 267 | .stb_cam_hit(stb_cam_hit), |
| 268 | .stb_cam_mhit(stb_cam_mhit), |
| 269 | .tcu_array_wr_inhibit(tcu_array_wr_inhibit), |
| 270 | .siclk(siclk) |
| 271 | ); |
| 272 | |
| 273 | |
| 274 | |
| 275 | supply0 vss; |
| 276 | supply1 vdd; |
| 277 | // fixscan start: |
| 278 | assign dff_out_mask_scanin = scan_in ; |
| 279 | assign mo_din_scanin = dff_out_mask_scanout ; |
| 280 | assign cam_vld_din_scanin = mo_din_scanout ; |
| 281 | assign cam_tid_din_scanin = cam_vld_din_scanout ; |
| 282 | assign dff_out_addr_scanin = cam_tid_din_scanout ; |
| 283 | assign camwr_din_scanin[0] = dff_out_addr_scanout ; |
| 284 | assign camwr_din_scanin[9] = camwr_din_scanout[0] ; |
| 285 | assign camwr_din_scanin[10] = camwr_din_scanout[9] ; |
| 286 | assign camwr_din_scanin[11] = camwr_din_scanout[10] ; |
| 287 | assign camwr_din_scanin[12] = camwr_din_scanout[11] ; |
| 288 | assign camwr_din_scanin[13] = camwr_din_scanout[12] ; |
| 289 | assign camwr_din_scanin[14] = camwr_din_scanout[13] ; |
| 290 | assign camwr_din_scanin[15] = camwr_din_scanout[14] ; |
| 291 | assign camwr_din_scanin[16] = camwr_din_scanout[15] ; |
| 292 | assign camwr_din_scanin[17] = camwr_din_scanout[16] ; |
| 293 | assign camwr_din_scanin[18] = camwr_din_scanout[17] ; |
| 294 | assign camwr_din_scanin[19] = camwr_din_scanout[18] ; |
| 295 | assign camwr_din_scanin[20] = camwr_din_scanout[19] ; |
| 296 | assign camwr_din_scanin[21] = camwr_din_scanout[20] ; |
| 297 | assign camwr_din_scanin[22] = camwr_din_scanout[21] ; |
| 298 | assign camwr_din_scanin[23] = camwr_din_scanout[22] ; |
| 299 | assign camwr_din_scanin[24] = camwr_din_scanout[23] ; |
| 300 | assign camwr_din_scanin[25] = camwr_din_scanout[24] ; |
| 301 | assign camwr_din_scanin[26] = camwr_din_scanout[25] ; |
| 302 | assign camwr_din_scanin[27] = camwr_din_scanout[26] ; |
| 303 | assign camwr_din_scanin[28] = camwr_din_scanout[27] ; |
| 304 | assign camwr_din_scanin[29] = camwr_din_scanout[28] ; |
| 305 | assign camwr_din_scanin[30] = camwr_din_scanout[29] ; |
| 306 | assign camwr_din_scanin[31] = camwr_din_scanout[30] ; |
| 307 | assign camwr_din_scanin[32] = camwr_din_scanout[31] ; |
| 308 | assign camwr_din_scanin[33] = camwr_din_scanout[32] ; |
| 309 | assign camwr_din_scanin[34] = camwr_din_scanout[33] ; |
| 310 | assign camwr_din_scanin[35] = camwr_din_scanout[34] ; |
| 311 | assign camwr_din_scanin[36] = camwr_din_scanout[35] ; |
| 312 | assign camwr_din_scanin[37] = camwr_din_scanout[36] ; |
| 313 | assign camwr_din_scanin[38] = camwr_din_scanout[37] ; |
| 314 | assign camwr_din_scanin[39] = camwr_din_scanout[38] ; |
| 315 | assign camwr_din_scanin[40] = camwr_din_scanout[39] ; |
| 316 | assign camwr_din_scanin[41] = camwr_din_scanout[40] ; |
| 317 | assign camwr_din_scanin[42] = camwr_din_scanout[41] ; |
| 318 | assign camwr_din_scanin[43] = camwr_din_scanout[42] ; |
| 319 | assign camwr_din_scanin[44] = camwr_din_scanout[43] ; |
| 320 | assign camwr_din_scanin[45] = camwr_din_scanout[44] ; |
| 321 | assign camwr_din_scanin[1] = camwr_din_scanout[45] ; |
| 322 | assign camwr_din_scanin[2] = camwr_din_scanout[1] ; |
| 323 | assign camwr_din_scanin[3] = camwr_din_scanout[2] ; |
| 324 | assign camwr_din_scanin[4] = camwr_din_scanout[3] ; |
| 325 | assign camwr_din_scanin[5] = camwr_din_scanout[4] ; |
| 326 | assign camwr_din_scanin[6] = camwr_din_scanout[5] ; |
| 327 | assign camwr_din_scanin[7] = camwr_din_scanout[6] ; |
| 328 | assign camwr_din_scanin[8] = camwr_din_scanout[7] ; |
| 329 | assign scan_out = camwr_din_scanout[8] ; |
| 330 | // fixscan end: |
| 331 | |
| 332 | `ifndef FPGA |
| 333 | // synopsys translate_on |
| 334 | `endif |
| 335 | |
| 336 | endmodule |
| 337 | |
| 338 | |
| 339 | |
| 340 | |
| 341 | |
| 342 | |
| 343 | // any PARAMS parms go into naming of macro |
| 344 | |
| 345 | module n2_stb_cm_64x45_cust_l1clkhdr_ctl_macro ( |
| 346 | l2clk, |
| 347 | l1en, |
| 348 | pce_ov, |
| 349 | stop, |
| 350 | se, |
| 351 | l1clk); |
| 352 | |
| 353 | |
| 354 | input l2clk; |
| 355 | input l1en; |
| 356 | input pce_ov; |
| 357 | input stop; |
| 358 | input se; |
| 359 | output l1clk; |
| 360 | |
| 361 | |
| 362 | |
| 363 | |
| 364 | |
| 365 | cl_sc1_l1hdr_8x c_0 ( |
| 366 | |
| 367 | |
| 368 | .l2clk(l2clk), |
| 369 | .pce(l1en), |
| 370 | .l1clk(l1clk), |
| 371 | .se(se), |
| 372 | .pce_ov(pce_ov), |
| 373 | .stop(stop) |
| 374 | ); |
| 375 | |
| 376 | |
| 377 | |
| 378 | endmodule |
| 379 | |
| 380 | |
| 381 | |
| 382 | |
| 383 | |
| 384 | |
| 385 | |
| 386 | |
| 387 | |
| 388 | // |
| 389 | // invert macro |
| 390 | // |
| 391 | // |
| 392 | |
| 393 | |
| 394 | |
| 395 | |
| 396 | |
| 397 | module n2_stb_cm_64x45_cust_inv_macro__width_45 ( |
| 398 | din, |
| 399 | dout); |
| 400 | input [44:0] din; |
| 401 | output [44:0] dout; |
| 402 | |
| 403 | |
| 404 | |
| 405 | |
| 406 | |
| 407 | |
| 408 | inv #(45) d0_0 ( |
| 409 | .in(din[44:0]), |
| 410 | .out(dout[44:0]) |
| 411 | ); |
| 412 | |
| 413 | |
| 414 | |
| 415 | |
| 416 | |
| 417 | |
| 418 | |
| 419 | |
| 420 | |
| 421 | endmodule |
| 422 | |
| 423 | |
| 424 | |
| 425 | |
| 426 | |
| 427 | |
| 428 | |
| 429 | |
| 430 | |
| 431 | // any PARAMS parms go into naming of macro |
| 432 | |
| 433 | module n2_stb_cm_64x45_cust_msff_ctl_macro__width_8 ( |
| 434 | din, |
| 435 | l1clk, |
| 436 | scan_in, |
| 437 | siclk, |
| 438 | soclk, |
| 439 | dout, |
| 440 | scan_out); |
| 441 | wire [7:0] fdin; |
| 442 | wire [6:0] so; |
| 443 | |
| 444 | input [7:0] din; |
| 445 | input l1clk; |
| 446 | input scan_in; |
| 447 | |
| 448 | |
| 449 | input siclk; |
| 450 | input soclk; |
| 451 | |
| 452 | output [7:0] dout; |
| 453 | output scan_out; |
| 454 | assign fdin[7:0] = din[7:0]; |
| 455 | |
| 456 | |
| 457 | |
| 458 | |
| 459 | |
| 460 | |
| 461 | dff #(8) d0_0 ( |
| 462 | .l1clk(l1clk), |
| 463 | .siclk(siclk), |
| 464 | .soclk(soclk), |
| 465 | .d(fdin[7:0]), |
| 466 | .si({scan_in,so[6:0]}), |
| 467 | .so({so[6:0],scan_out}), |
| 468 | .q(dout[7:0]) |
| 469 | ); |
| 470 | |
| 471 | |
| 472 | |
| 473 | |
| 474 | |
| 475 | |
| 476 | |
| 477 | |
| 478 | |
| 479 | |
| 480 | |
| 481 | |
| 482 | endmodule |
| 483 | |
| 484 | |
| 485 | |
| 486 | |
| 487 | |
| 488 | |
| 489 | |
| 490 | |
| 491 | |
| 492 | // |
| 493 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops |
| 494 | // |
| 495 | // |
| 496 | |
| 497 | |
| 498 | |
| 499 | |
| 500 | |
| 501 | module n2_stb_cm_64x45_cust_sram_msff_mo_macro__width_8 ( |
| 502 | d, |
| 503 | scan_in, |
| 504 | l1clk, |
| 505 | and_clk, |
| 506 | siclk, |
| 507 | soclk, |
| 508 | mq, |
| 509 | mq_l, |
| 510 | scan_out, |
| 511 | q, |
| 512 | q_l); |
| 513 | wire [6:0] so; |
| 514 | |
| 515 | input [7:0] d; |
| 516 | input scan_in; |
| 517 | input l1clk; |
| 518 | input and_clk; |
| 519 | input siclk; |
| 520 | input soclk; |
| 521 | output [7:0] mq; |
| 522 | output [7:0] mq_l; |
| 523 | output scan_out; |
| 524 | output [7:0] q; |
| 525 | output [7:0] q_l; |
| 526 | |
| 527 | |
| 528 | |
| 529 | |
| 530 | |
| 531 | |
| 532 | new_dlata #(8) d0_0 ( |
| 533 | .d(d[7:0]), |
| 534 | .si({scan_in,so[6:0]}), |
| 535 | .so({so[6:0],scan_out}), |
| 536 | .l1clk(l1clk), |
| 537 | .and_clk(and_clk), |
| 538 | .siclk(siclk), |
| 539 | .soclk(soclk), |
| 540 | .q(q[7:0]), |
| 541 | .q_l(q_l[7:0]), |
| 542 | .mq(mq[7:0]), |
| 543 | .mq_l(mq_l[7:0]) |
| 544 | ); |
| 545 | |
| 546 | |
| 547 | |
| 548 | |
| 549 | |
| 550 | |
| 551 | |
| 552 | |
| 553 | |
| 554 | |
| 555 | //place::generic_place($width,$stack,$left); |
| 556 | |
| 557 | endmodule |
| 558 | |
| 559 | |
| 560 | |
| 561 | |
| 562 | |
| 563 | // |
| 564 | // macro for cl_mc1_scm_msff_lat_{4}x flops |
| 565 | // |
| 566 | // |
| 567 | |
| 568 | |
| 569 | |
| 570 | |
| 571 | |
| 572 | module n2_stb_cm_64x45_cust_scm_msff_lat_macro__width_1 ( |
| 573 | d, |
| 574 | scan_in, |
| 575 | l1clk, |
| 576 | siclk, |
| 577 | soclk, |
| 578 | latout, |
| 579 | scan_out, |
| 580 | q, |
| 581 | q_l); |
| 582 | input [0:0] d; |
| 583 | input scan_in; |
| 584 | input l1clk; |
| 585 | input siclk; |
| 586 | input soclk; |
| 587 | output [0:0] latout; |
| 588 | output scan_out; |
| 589 | output [0:0] q; |
| 590 | output [0:0] q_l; |
| 591 | |
| 592 | |
| 593 | |
| 594 | |
| 595 | |
| 596 | |
| 597 | scm_msff_lat #(1) d0_0 ( |
| 598 | .d(d[0:0]), |
| 599 | .si(scan_in), |
| 600 | .so(scan_out), |
| 601 | .l1clk(l1clk), |
| 602 | .siclk(siclk), |
| 603 | .soclk(soclk), |
| 604 | .q(q[0:0]), |
| 605 | .q_l(q_l[0:0]), |
| 606 | .latout(latout[0:0]) |
| 607 | ); |
| 608 | |
| 609 | |
| 610 | |
| 611 | |
| 612 | |
| 613 | |
| 614 | |
| 615 | |
| 616 | |
| 617 | |
| 618 | //place::generic_place($width,$stack,$left); |
| 619 | |
| 620 | endmodule |
| 621 | |
| 622 | |
| 623 | |
| 624 | |
| 625 | |
| 626 | |
| 627 | |
| 628 | |
| 629 | |
| 630 | // any PARAMS parms go into naming of macro |
| 631 | |
| 632 | module n2_stb_cm_64x45_cust_msff_ctl_macro__width_3 ( |
| 633 | din, |
| 634 | l1clk, |
| 635 | scan_in, |
| 636 | siclk, |
| 637 | soclk, |
| 638 | dout, |
| 639 | scan_out); |
| 640 | wire [2:0] fdin; |
| 641 | wire [1:0] so; |
| 642 | |
| 643 | input [2:0] din; |
| 644 | input l1clk; |
| 645 | input scan_in; |
| 646 | |
| 647 | |
| 648 | input siclk; |
| 649 | input soclk; |
| 650 | |
| 651 | output [2:0] dout; |
| 652 | output scan_out; |
| 653 | assign fdin[2:0] = din[2:0]; |
| 654 | |
| 655 | |
| 656 | |
| 657 | |
| 658 | |
| 659 | |
| 660 | dff #(3) d0_0 ( |
| 661 | .l1clk(l1clk), |
| 662 | .siclk(siclk), |
| 663 | .soclk(soclk), |
| 664 | .d(fdin[2:0]), |
| 665 | .si({scan_in,so[1:0]}), |
| 666 | .so({so[1:0],scan_out}), |
| 667 | .q(dout[2:0]) |
| 668 | ); |
| 669 | |
| 670 | |
| 671 | |
| 672 | |
| 673 | |
| 674 | |
| 675 | |
| 676 | |
| 677 | |
| 678 | |
| 679 | |
| 680 | |
| 681 | endmodule |
| 682 | |
| 683 | |
| 684 | |
| 685 | |
| 686 | |
| 687 | |
| 688 | |
| 689 | |
| 690 | |
| 691 | |
| 692 | |
| 693 | |
| 694 | |
| 695 | // any PARAMS parms go into naming of macro |
| 696 | |
| 697 | module n2_stb_cm_64x45_cust_msff_ctl_macro__width_37 ( |
| 698 | din, |
| 699 | l1clk, |
| 700 | scan_in, |
| 701 | siclk, |
| 702 | soclk, |
| 703 | dout, |
| 704 | scan_out); |
| 705 | wire [36:0] fdin; |
| 706 | wire [35:0] so; |
| 707 | |
| 708 | input [36:0] din; |
| 709 | input l1clk; |
| 710 | input scan_in; |
| 711 | |
| 712 | |
| 713 | input siclk; |
| 714 | input soclk; |
| 715 | |
| 716 | output [36:0] dout; |
| 717 | output scan_out; |
| 718 | assign fdin[36:0] = din[36:0]; |
| 719 | |
| 720 | |
| 721 | |
| 722 | |
| 723 | |
| 724 | |
| 725 | dff #(37) d0_0 ( |
| 726 | .l1clk(l1clk), |
| 727 | .siclk(siclk), |
| 728 | .soclk(soclk), |
| 729 | .d(fdin[36:0]), |
| 730 | .si({scan_in,so[35:0]}), |
| 731 | .so({so[35:0],scan_out}), |
| 732 | .q(dout[36:0]) |
| 733 | ); |
| 734 | |
| 735 | |
| 736 | |
| 737 | |
| 738 | |
| 739 | |
| 740 | |
| 741 | |
| 742 | |
| 743 | |
| 744 | |
| 745 | |
| 746 | endmodule |
| 747 | |
| 748 | |
| 749 | |
| 750 | |
| 751 | |
| 752 | |
| 753 | |
| 754 | |
| 755 | |
| 756 | // |
| 757 | // macro for cl_mc1_scm_msff_lat_{4}x flops |
| 758 | // |
| 759 | // |
| 760 | |
| 761 | |
| 762 | |
| 763 | |
| 764 | |
| 765 | module n2_stb_cm_64x45_cust_scm_msff_lat_macro__fs_1__width_46 ( |
| 766 | d, |
| 767 | scan_in, |
| 768 | l1clk, |
| 769 | siclk, |
| 770 | soclk, |
| 771 | latout, |
| 772 | scan_out, |
| 773 | q, |
| 774 | q_l); |
| 775 | input [45:0] d; |
| 776 | input [45:0] scan_in; |
| 777 | input l1clk; |
| 778 | input siclk; |
| 779 | input soclk; |
| 780 | output [45:0] latout; |
| 781 | output [45:0] scan_out; |
| 782 | output [45:0] q; |
| 783 | output [45:0] q_l; |
| 784 | |
| 785 | |
| 786 | |
| 787 | |
| 788 | |
| 789 | |
| 790 | scm_msff_lat #(46) d0_0 ( |
| 791 | .d(d[45:0]), |
| 792 | .si(scan_in[45:0]), |
| 793 | .so(scan_out[45:0]), |
| 794 | .l1clk(l1clk), |
| 795 | .siclk(siclk), |
| 796 | .soclk(soclk), |
| 797 | .q(q[45:0]), |
| 798 | .q_l(q_l[45:0]), |
| 799 | .latout(latout[45:0]) |
| 800 | ); |
| 801 | |
| 802 | |
| 803 | |
| 804 | |
| 805 | |
| 806 | |
| 807 | |
| 808 | |
| 809 | |
| 810 | |
| 811 | //place::generic_place($width,$stack,$left); |
| 812 | |
| 813 | endmodule |
| 814 | |
| 815 | |
| 816 | |
| 817 | |
| 818 | |
| 819 | `ifndef FPGA |
| 820 | module n2_stb_cm_64x45_array ( |
| 821 | cam_rw_ptr, |
| 822 | cam_rw_tid, |
| 823 | wptr_vld, |
| 824 | rptr_vld, |
| 825 | camwr_data, |
| 826 | cam_vld, |
| 827 | cam_cm_tid, |
| 828 | cam_line_en, |
| 829 | cam_ldq, |
| 830 | stb_rdata, |
| 831 | stb_ld_partial_raw, |
| 832 | stb_cam_hit_ptr, |
| 833 | stb_cam_hit, |
| 834 | stb_cam_mhit, |
| 835 | clk, |
| 836 | tcu_array_wr_inhibit, |
| 837 | siclk); |
| 838 | wire [5:0] rw_addr; |
| 839 | wire write_vld; |
| 840 | wire read_vld; |
| 841 | wire [7:0] byte_overlap_mx; |
| 842 | wire [7:0] byte_match_mx; |
| 843 | wire [7:0] ptag_hit_mx; |
| 844 | wire [7:0] cam_hit; |
| 845 | |
| 846 | |
| 847 | input [2:0] cam_rw_ptr ; // wr pointer for single port. |
| 848 | input [2:0] cam_rw_tid ; // thread id for rw. |
| 849 | input wptr_vld ; // write pointer vld |
| 850 | input rptr_vld ; // read pointer vld |
| 851 | |
| 852 | input [44:0] camwr_data ; // data for compare/write |
| 853 | input cam_vld ; // cam is required. |
| 854 | input [2:0] cam_cm_tid ; // thread id for cam operation. |
| 855 | input [7:0] cam_line_en; // mask for squashing cam results (unflopped input) |
| 856 | |
| 857 | input cam_ldq ; // quad-ld cam. |
| 858 | |
| 859 | |
| 860 | output [44:0] stb_rdata; // rd data from CAM RAM. |
| 861 | output stb_ld_partial_raw ; // ld with partial raw. |
| 862 | output [2:0] stb_cam_hit_ptr ; |
| 863 | output stb_cam_hit ; // any hit in stb |
| 864 | output stb_cam_mhit ; // multiple hits in stb |
| 865 | |
| 866 | input clk; |
| 867 | input tcu_array_wr_inhibit; |
| 868 | input siclk; |
| 869 | |
| 870 | integer i,l; |
| 871 | |
| 872 | /////////////////////////////////////////////////////////////// |
| 873 | // The array |
| 874 | /////////////////////////////////////////////////////////////// |
| 875 | |
| 876 | reg [44:0] stb_ramc[63:0]; |
| 877 | reg [44:0] stb_rdata; |
| 878 | |
| 879 | //========================================================================================= |
| 880 | // initialize array |
| 881 | //========================================================================================= |
| 882 | |
| 883 | `ifndef NOINITMEM |
| 884 | initial begin |
| 885 | for (i=0;i<64;i=i+1) begin |
| 886 | stb_ramc[i] = 45'd0; |
| 887 | end |
| 888 | end |
| 889 | `endif |
| 890 | |
| 891 | assign rw_addr[5:0] = {cam_rw_tid[2:0],cam_rw_ptr[2:0]}; |
| 892 | |
| 893 | assign write_vld = wptr_vld & ~tcu_array_wr_inhibit; |
| 894 | assign read_vld = rptr_vld & ~tcu_array_wr_inhibit; |
| 895 | |
| 896 | /////////// |
| 897 | // Write |
| 898 | /////////// |
| 899 | always @ (clk or write_vld or rw_addr or camwr_data or cam_vld) begin |
| 900 | if (clk & write_vld) begin |
| 901 | if (cam_vld) |
| 902 | stb_ramc[rw_addr] <= 45'hx; |
| 903 | else |
| 904 | stb_ramc[rw_addr] <= camwr_data[44:0]; |
| 905 | end |
| 906 | end |
| 907 | |
| 908 | |
| 909 | |
| 910 | |
| 911 | /////////// |
| 912 | // Read |
| 913 | /////////// |
| 914 | |
| 915 | always @(clk or read_vld or rw_addr or write_vld) begin |
| 916 | if (clk) begin |
| 917 | if (write_vld | ~read_vld) |
| 918 | stb_rdata[44:0] <= 45'hx; |
| 919 | else |
| 920 | stb_rdata[44:0] <= stb_ramc[rw_addr]; |
| 921 | end |
| 922 | end |
| 923 | |
| 924 | //========================================================================================= |
| 925 | // CAM contents |
| 926 | //========================================================================================= |
| 927 | |
| 928 | // - Generate full/partial raw for incoming load. |
| 929 | // - Output signals need to be qualified with per entry |
| 930 | // vlds before causing any subsequent event, the read of |
| 931 | // the DATA RAM specifically. |
| 932 | |
| 933 | // Mapping of cam/write data |
| 934 | // |
| 935 | // | 39-3=37b(pa) | 8b(bytemask) | <- use |
| 936 | // | 44:8 | 7:0 | <- input port |
| 937 | |
| 938 | reg [44:0] ramc_entry; |
| 939 | reg [36:0] cam_tag; |
| 940 | reg [7:0] cam_bmask; |
| 941 | reg [63:0] ptag_hit; |
| 942 | reg [63:0] byte_match; |
| 943 | reg [63:0] byte_overlap; |
| 944 | |
| 945 | // ptag_hit indicates a match at the dword (or qword for quad loads) boundary |
| 946 | // byte_match indciates match at the byte level within the dword |
| 947 | // byte_overlap checks that all bytes in incoming bmask has a corresponding mask bit |
| 948 | // set in the cam entry. This differentiates between full and partial raw. |
| 949 | |
| 950 | always @(posedge clk) begin |
| 951 | for (l=0;l<64;l=l+1) begin |
| 952 | ramc_entry[44:0] = stb_ramc[l] ; |
| 953 | cam_tag[36:0] = ramc_entry[44:8] ; |
| 954 | cam_bmask[7:0] = ramc_entry[7:0] ; |
| 955 | ptag_hit[l] <= (cam_tag[36:1] == camwr_data[44:9]) & (((cam_tag[0] == camwr_data[8]) & ~cam_ldq) | cam_ldq) & cam_vld; |
| 956 | byte_match[l] <= |(cam_bmask[7:0] & camwr_data[7:0]) & cam_vld; |
| 957 | byte_overlap[l] <= |(~cam_bmask[7:0] & camwr_data[7:0]) & cam_vld ; |
| 958 | end |
| 959 | end |
| 960 | |
| 961 | // CAM values will be indeterminate while scanning |
| 962 | |
| 963 | always @(posedge siclk) begin |
| 964 | ptag_hit[63:0] <= 64'hx; |
| 965 | byte_match[63:0] <= 64'hx; |
| 966 | byte_overlap[63:0] <= 64'hx; |
| 967 | end |
| 968 | |
| 969 | |
| 970 | // Mux the raw signals down to 8b quantities. Line enable comes mid-way thru cycle. |
| 971 | |
| 972 | assign byte_overlap_mx[7:0] = |
| 973 | ({8{(cam_cm_tid[2:0] == 3'b000)}} & byte_overlap[7:0] ) | |
| 974 | ({8{(cam_cm_tid[2:0] == 3'b001)}} & byte_overlap[15:8] ) | |
| 975 | ({8{(cam_cm_tid[2:0] == 3'b010)}} & byte_overlap[23:16]) | |
| 976 | ({8{(cam_cm_tid[2:0] == 3'b011)}} & byte_overlap[31:24]) | |
| 977 | ({8{(cam_cm_tid[2:0] == 3'b100)}} & byte_overlap[39:32]) | |
| 978 | ({8{(cam_cm_tid[2:0] == 3'b101)}} & byte_overlap[47:40]) | |
| 979 | ({8{(cam_cm_tid[2:0] == 3'b110)}} & byte_overlap[55:48]) | |
| 980 | ({8{(cam_cm_tid[2:0] == 3'b111)}} & byte_overlap[63:56]) ; |
| 981 | |
| 982 | assign byte_match_mx[7:0] = |
| 983 | ({8{(cam_cm_tid[2:0] == 3'b000)}} & byte_match[7:0] ) | |
| 984 | ({8{(cam_cm_tid[2:0] == 3'b001)}} & byte_match[15:8] ) | |
| 985 | ({8{(cam_cm_tid[2:0] == 3'b010)}} & byte_match[23:16]) | |
| 986 | ({8{(cam_cm_tid[2:0] == 3'b011)}} & byte_match[31:24]) | |
| 987 | ({8{(cam_cm_tid[2:0] == 3'b100)}} & byte_match[39:32]) | |
| 988 | ({8{(cam_cm_tid[2:0] == 3'b101)}} & byte_match[47:40]) | |
| 989 | ({8{(cam_cm_tid[2:0] == 3'b110)}} & byte_match[55:48]) | |
| 990 | ({8{(cam_cm_tid[2:0] == 3'b111)}} & byte_match[63:56]) ; |
| 991 | |
| 992 | assign ptag_hit_mx[7:0] = |
| 993 | ({8{(cam_cm_tid[2:0] == 3'b000)}} & ptag_hit[7:0] ) | |
| 994 | ({8{(cam_cm_tid[2:0] == 3'b001)}} & ptag_hit[15:8] ) | |
| 995 | ({8{(cam_cm_tid[2:0] == 3'b010)}} & ptag_hit[23:16]) | |
| 996 | ({8{(cam_cm_tid[2:0] == 3'b011)}} & ptag_hit[31:24]) | |
| 997 | ({8{(cam_cm_tid[2:0] == 3'b100)}} & ptag_hit[39:32]) | |
| 998 | ({8{(cam_cm_tid[2:0] == 3'b101)}} & ptag_hit[47:40]) | |
| 999 | ({8{(cam_cm_tid[2:0] == 3'b110)}} & ptag_hit[55:48]) | |
| 1000 | ({8{(cam_cm_tid[2:0] == 3'b111)}} & ptag_hit[63:56]) ; |
| 1001 | |
| 1002 | assign stb_ld_partial_raw = |
| 1003 | |(ptag_hit_mx[7:0] & byte_match_mx[7:0] & byte_overlap_mx[7:0] & cam_line_en[7:0]) ; |
| 1004 | |
| 1005 | assign cam_hit[7:0] = |
| 1006 | ptag_hit_mx[7:0] & byte_match_mx[7:0] & cam_line_en[7:0] ; |
| 1007 | assign stb_cam_hit = |(cam_hit[7:0]); |
| 1008 | |
| 1009 | // The stb data is meant to be read for single hit full raw case. It may actually be read |
| 1010 | // for full raw, partial raw or multiple hit case but the read output will be ignored for |
| 1011 | // partial and multiple hit case. Multiple hits will not cause a hazard as the ptr is first |
| 1012 | // encoded and then decoded to form the wdline for the stb-data |
| 1013 | // Use cam_hit result to void false hits. |
| 1014 | assign stb_cam_hit_ptr[0] = cam_hit[1] | cam_hit[3] | cam_hit[5] | cam_hit[7] ; |
| 1015 | assign stb_cam_hit_ptr[1] = cam_hit[2] | cam_hit[3] | cam_hit[6] | cam_hit[7] ; |
| 1016 | assign stb_cam_hit_ptr[2] = cam_hit[4] | cam_hit[5] | cam_hit[6] | cam_hit[7] ; |
| 1017 | |
| 1018 | //Generating multiple hits |
| 1019 | assign stb_cam_mhit = (cam_hit[0] & cam_hit[1]) | (cam_hit[2] & cam_hit[3]) | |
| 1020 | (cam_hit[4] & cam_hit[5]) | (cam_hit[6] & cam_hit[7]) | |
| 1021 | ((cam_hit[0] | cam_hit[1]) & (cam_hit[2] | cam_hit[3])) | |
| 1022 | ((cam_hit[4] | cam_hit[5]) & (cam_hit[6] | cam_hit[7])) | |
| 1023 | ((|cam_hit[3:0]) & (|cam_hit[7:4])); |
| 1024 | |
| 1025 | supply0 vss; |
| 1026 | supply1 vdd; |
| 1027 | endmodule |
| 1028 | `endif |
| 1029 | |
| 1030 | |
| 1031 | |
| 1032 | `ifdef FPGA |
| 1033 | |
| 1034 | module n2_stb_cm_64x45_array(cam_rw_ptr, cam_rw_tid, wptr_vld, rptr_vld, |
| 1035 | camwr_data, cam_vld, cam_cm_tid, cam_line_en, cam_ldq, stb_rdata, |
| 1036 | stb_ld_partial_raw, stb_cam_hit_ptr, stb_cam_hit, stb_cam_mhit, clk, |
| 1037 | tcu_array_wr_inhibit, siclk); |
| 1038 | |
| 1039 | input [2:0] cam_rw_ptr; |
| 1040 | input [2:0] cam_rw_tid; |
| 1041 | input wptr_vld; |
| 1042 | input rptr_vld; |
| 1043 | input [44:0] camwr_data; |
| 1044 | input cam_vld; |
| 1045 | input [2:0] cam_cm_tid; |
| 1046 | input [7:0] cam_line_en; |
| 1047 | input cam_ldq; |
| 1048 | output [44:0] stb_rdata; |
| 1049 | output stb_ld_partial_raw; |
| 1050 | output [2:0] stb_cam_hit_ptr; |
| 1051 | output stb_cam_hit; |
| 1052 | output stb_cam_mhit; |
| 1053 | input clk; |
| 1054 | input tcu_array_wr_inhibit; |
| 1055 | input siclk; |
| 1056 | |
| 1057 | wire [5:0] rw_addr; |
| 1058 | wire write_vld; |
| 1059 | wire read_vld; |
| 1060 | wire [7:0] byte_overlap_mx; |
| 1061 | wire [7:0] byte_match_mx; |
| 1062 | wire [7:0] ptag_hit_mx; |
| 1063 | wire [7:0] cam_hit; |
| 1064 | integer i; |
| 1065 | integer l; |
| 1066 | |
| 1067 | reg [44:0] stb_ramc[63:0]; |
| 1068 | reg [44:0] stb_rdata; |
| 1069 | reg [44:0] ramc_entry; |
| 1070 | reg [36:0] cam_tag; |
| 1071 | reg [7:0] cam_bmask; |
| 1072 | reg [63:0] ptag_hit; |
| 1073 | reg [63:0] byte_match; |
| 1074 | reg [63:0] byte_overlap; |
| 1075 | supply0 vss; |
| 1076 | supply1 vdd; |
| 1077 | |
| 1078 | assign rw_addr[5:0] = {cam_rw_tid[2:0], cam_rw_ptr[2:0]}; |
| 1079 | assign write_vld = (wptr_vld & (~tcu_array_wr_inhibit)); |
| 1080 | assign read_vld = (rptr_vld & (~tcu_array_wr_inhibit)); |
| 1081 | assign byte_overlap_mx[7:0] = (((((((({8 {(cam_cm_tid[2:0] == 3'b0)}} & |
| 1082 | byte_overlap[7:0]) | ({8 {(cam_cm_tid[2:0] == 3'b1)}} & |
| 1083 | byte_overlap[15:8])) | ({8 {(cam_cm_tid[2:0] == 3'd2)}} & |
| 1084 | byte_overlap[23:16])) | ({8 {(cam_cm_tid[2:0] == 3'd3)}} & |
| 1085 | byte_overlap[31:24])) | ({8 {(cam_cm_tid[2:0] == 3'd4)}} & |
| 1086 | byte_overlap[39:32])) | ({8 {(cam_cm_tid[2:0] == 3'd5)}} & |
| 1087 | byte_overlap[47:40])) | ({8 {(cam_cm_tid[2:0] == 3'd6)}} & |
| 1088 | byte_overlap[55:48])) | ({8 {(cam_cm_tid[2:0] == 3'd7)}} & |
| 1089 | byte_overlap[63:56])); |
| 1090 | assign byte_match_mx[7:0] = (((((((({8 {(cam_cm_tid[2:0] == 3'b0)}} & |
| 1091 | byte_match[7:0]) | ({8 {(cam_cm_tid[2:0] == 3'b1)}} & |
| 1092 | byte_match[15:8])) | ({8 {(cam_cm_tid[2:0] == 3'd2)}} & |
| 1093 | byte_match[23:16])) | ({8 {(cam_cm_tid[2:0] == 3'd3)}} & |
| 1094 | byte_match[31:24])) | ({8 {(cam_cm_tid[2:0] == 3'd4)}} & |
| 1095 | byte_match[39:32])) | ({8 {(cam_cm_tid[2:0] == 3'd5)}} & |
| 1096 | byte_match[47:40])) | ({8 {(cam_cm_tid[2:0] == 3'd6)}} & |
| 1097 | byte_match[55:48])) | ({8 {(cam_cm_tid[2:0] == 3'd7)}} & |
| 1098 | byte_match[63:56])); |
| 1099 | assign ptag_hit_mx[7:0] = (((((((({8 {(cam_cm_tid[2:0] == 3'b0)}} & |
| 1100 | ptag_hit[7:0]) | ({8 {(cam_cm_tid[2:0] == 3'b1)}} & |
| 1101 | ptag_hit[15:8])) | ({8 {(cam_cm_tid[2:0] == 3'd2)}} & |
| 1102 | ptag_hit[23:16])) | ({8 {(cam_cm_tid[2:0] == 3'd3)}} & |
| 1103 | ptag_hit[31:24])) | ({8 {(cam_cm_tid[2:0] == 3'd4)}} & |
| 1104 | ptag_hit[39:32])) | ({8 {(cam_cm_tid[2:0] == 3'd5)}} & |
| 1105 | ptag_hit[47:40])) | ({8 {(cam_cm_tid[2:0] == 3'd6)}} & |
| 1106 | ptag_hit[55:48])) | ({8 {(cam_cm_tid[2:0] == 3'd7)}} & |
| 1107 | ptag_hit[63:56])); |
| 1108 | assign stb_ld_partial_raw = (|(((ptag_hit_mx[7:0] & byte_match_mx[7:0]) |
| 1109 | & byte_overlap_mx[7:0]) & cam_line_en[7:0])); |
| 1110 | assign cam_hit[7:0] = ((ptag_hit_mx[7:0] & byte_match_mx[7:0]) & |
| 1111 | cam_line_en[7:0]); |
| 1112 | assign stb_cam_hit = (|cam_hit[7:0]); |
| 1113 | assign stb_cam_hit_ptr[0] = (((cam_hit[1] | cam_hit[3]) | cam_hit[5]) | |
| 1114 | cam_hit[7]); |
| 1115 | assign stb_cam_hit_ptr[1] = (((cam_hit[2] | cam_hit[3]) | cam_hit[6]) | |
| 1116 | cam_hit[7]); |
| 1117 | assign stb_cam_hit_ptr[2] = (((cam_hit[4] | cam_hit[5]) | cam_hit[6]) | |
| 1118 | cam_hit[7]); |
| 1119 | assign stb_cam_mhit = (((((((cam_hit[0] & cam_hit[1]) | (cam_hit[2] & |
| 1120 | cam_hit[3])) | (cam_hit[4] & cam_hit[5])) | (cam_hit[6] & |
| 1121 | cam_hit[7])) | ((cam_hit[0] | cam_hit[1]) & (cam_hit[2] | |
| 1122 | cam_hit[3]))) | ((cam_hit[4] | cam_hit[5]) & (cam_hit[6] | |
| 1123 | cam_hit[7]))) | ((|cam_hit[3:0]) & (|cam_hit[7:4]))); |
| 1124 | |
| 1125 | initial begin |
| 1126 | for (i = 0; (i < 64); i = (i + 1)) begin |
| 1127 | stb_ramc[i] = 45'b0; |
| 1128 | end |
| 1129 | end |
| 1130 | always @(clk or write_vld or rw_addr or camwr_data or cam_vld) begin |
| 1131 | if (clk & write_vld) begin |
| 1132 | if (cam_vld) begin |
| 1133 | stb_ramc[rw_addr] <= 45'hxxxxxxxxxxxx; |
| 1134 | end |
| 1135 | else begin |
| 1136 | stb_ramc[rw_addr] <= camwr_data[44:0]; |
| 1137 | end |
| 1138 | end |
| 1139 | end |
| 1140 | always @(clk or read_vld or rw_addr or write_vld) begin |
| 1141 | if (clk) begin |
| 1142 | if (write_vld | (~read_vld)) begin |
| 1143 | stb_rdata[44:0] <= 45'hxxxxxxxxxxxx; |
| 1144 | end |
| 1145 | else begin |
| 1146 | stb_rdata[44:0] <= stb_ramc[rw_addr]; |
| 1147 | end |
| 1148 | end |
| 1149 | end |
| 1150 | always @(posedge clk) begin |
| 1151 | for (l = 0; (l < 64); l = (l + 1)) begin |
| 1152 | ramc_entry[44:0] = stb_ramc[l]; |
| 1153 | cam_tag[36:0] = ramc_entry[44:8]; |
| 1154 | cam_bmask[7:0] = ramc_entry[7:0]; |
| 1155 | ptag_hit[l] <= (((cam_tag[36:1] == camwr_data[44:9]) & (((cam_tag[0] |
| 1156 | == camwr_data[8]) & (~cam_ldq)) | cam_ldq)) & cam_vld); |
| 1157 | byte_match[l] <= ((|(cam_bmask[7:0] & camwr_data[7:0])) & cam_vld); |
| 1158 | byte_overlap[l] <= ((|((~cam_bmask[7:0]) & camwr_data[7:0])) & |
| 1159 | cam_vld); |
| 1160 | end |
| 1161 | end |
| 1162 | endmodule |
| 1163 | |
| 1164 | `endif // `ifdef FPGA |
| 1165 | |