| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: n2_tlb_tl_128x59_cust.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module n2_tlb_tl_128x59_cust ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | pce, |
| 40 | tcu_aclk, |
| 41 | tcu_bclk, |
| 42 | tcu_se_scancollar_in, |
| 43 | tcu_se_scancollar_out, |
| 44 | tcu_array_wr_inhibit, |
| 45 | tcu_scan_en, |
| 46 | disable_clear_ubit, |
| 47 | scan_out, |
| 48 | tlb_bypass, |
| 49 | tlb_wr_vld, |
| 50 | tlb_rd_vld, |
| 51 | tlb_cam_vld, |
| 52 | tlb_rw_index, |
| 53 | tlb_rw_index_vld, |
| 54 | tlb_demap, |
| 55 | tlb_demap_context, |
| 56 | tlb_demap_all, |
| 57 | tlb_demap_real, |
| 58 | tte_tag, |
| 59 | tte_ubit, |
| 60 | tte_page_size_mask, |
| 61 | tte_data, |
| 62 | tlb_va, |
| 63 | cache_ptag_w0, |
| 64 | cache_ptag_w1, |
| 65 | cache_ptag_w2, |
| 66 | cache_ptag_w3, |
| 67 | cache_set_vld, |
| 68 | cache_way_hit, |
| 69 | cache_hit, |
| 70 | tlb_cam_hit, |
| 71 | tlb_cam_mhit, |
| 72 | tlb_context0_hit, |
| 73 | tlb_pgnum_crit, |
| 74 | tlb_pgnum, |
| 75 | tlb_tte_data, |
| 76 | tlb_tte_tag, |
| 77 | tlb_tte_u_bit, |
| 78 | tlb_tte_data_parity) ; |
| 79 | wire pce_ov; |
| 80 | wire stop; |
| 81 | wire siclk; |
| 82 | wire soclk; |
| 83 | wire se; |
| 84 | wire l1clk_in; |
| 85 | wire l1clk_free; |
| 86 | wire [73:0] cam_ctl_lat_scanin; |
| 87 | wire [73:0] cam_ctl_lat_scanout; |
| 88 | wire [65:0] tte_tag_1; |
| 89 | wire tte_ubit_1; |
| 90 | wire tlb_wr_1_in_unused; |
| 91 | wire tlb_rd_1_unused; |
| 92 | wire tlb_cam_1_in; |
| 93 | wire demap_1_in; |
| 94 | wire demap_context_1; |
| 95 | wire demap_all_1; |
| 96 | wire demap_real_1; |
| 97 | wire [73:0] lat_l_unused; |
| 98 | wire [65:0] tte_tag_1_dout; |
| 99 | wire tte_ubit_1_unused; |
| 100 | wire tlb_wr_1_in_dout; |
| 101 | wire tlb_rd_1_in_dout; |
| 102 | wire tlb_cam_1_in_dout; |
| 103 | wire demap_1_in_unused; |
| 104 | wire demap_context_1_unused; |
| 105 | wire demap_all_1_unused; |
| 106 | wire demap_real_1_unused; |
| 107 | wire [73:0] dout_l_unused; |
| 108 | wire demap_page_1_unused; |
| 109 | wire wr_inhibit_; |
| 110 | wire tlb_wr_1_dout; |
| 111 | wire tlb_rd_1_dout; |
| 112 | wire tlb_cam_1; |
| 113 | wire tlb_cam_1_dout; |
| 114 | wire demap_1; |
| 115 | wire [2:0] page_size_mask_reg_scanin; |
| 116 | wire [2:0] page_size_mask_reg_scanout; |
| 117 | wire [2:0] tte_page_size_mask_1; |
| 118 | wire disable_clear_ubit_reg_scanin; |
| 119 | wire disable_clear_ubit_reg_scanout; |
| 120 | wire disable_clear_ubit_1_in; |
| 121 | wire disable_clear_ubit_1; |
| 122 | wire tlb_bypass_reg_scanin; |
| 123 | wire tlb_bypass_reg_scanout; |
| 124 | wire tlb_bypass_1; |
| 125 | wire [1:0] vaddr_reg_scanin; |
| 126 | wire [1:0] vaddr_reg_scanout; |
| 127 | wire [12:11] va_1; |
| 128 | wire [37:0] tte_data_reg_scanin; |
| 129 | wire [37:0] tte_data_reg_scanout; |
| 130 | wire [37:0] tte_data_1; |
| 131 | wire [6:0] tlb_replacement_index; |
| 132 | wire [6:0] rw_index_0; |
| 133 | wire [6:0] rw_index_reg_scanin; |
| 134 | wire [6:0] rw_index_reg_scanout; |
| 135 | wire [6:0] rw_index_1; |
| 136 | wire rw_index_vld_reg_scanin; |
| 137 | wire rw_index_vld_reg_scanout; |
| 138 | wire rw_index_vld_unused; |
| 139 | wire [39:11] pa_1; |
| 140 | wire tlb_cam_hit_1; |
| 141 | wire l1clk_out; |
| 142 | wire [2:0] tlb_cam_hit_reg_scanin; |
| 143 | wire [2:0] tlb_cam_hit_reg_scanout; |
| 144 | wire multiple_match; |
| 145 | wire context0_hit; |
| 146 | wire tlb_cam_mhit_b; |
| 147 | wire [39:13] pa_1_b; |
| 148 | wire [26:0] pa_reg_scanin; |
| 149 | wire [26:0] pa_reg_scanout; |
| 150 | wire [39:13] pa_2_b; |
| 151 | wire [39:13] pa_2; |
| 152 | wire [37:0] tte_data_out_reg_scanin; |
| 153 | wire [37:0] tte_data_out_reg_scanout; |
| 154 | wire [37:0] rd_tte_data; |
| 155 | wire [65:0] rd_tte_tag; |
| 156 | wire [65:0] rd_tte_tag_b; |
| 157 | wire [65:0] tte_tag_out_reg_scanin; |
| 158 | wire [65:0] tte_tag_out_reg_scanout; |
| 159 | wire [65:0] tlb_tte_tag_b; |
| 160 | wire rd_tte_u_bit; |
| 161 | wire rd_tte_u_bit_b; |
| 162 | wire tte_u_bit_out_reg_scanin; |
| 163 | wire tte_u_bit_out_reg_scanout; |
| 164 | wire tlb_tte_u_bit_b; |
| 165 | wire [3:0] cache_way_hit_in; |
| 166 | wire [3:0] cache_way_hit_in_b; |
| 167 | wire [3:0] cache_way_hit_reg_scanin; |
| 168 | wire [3:0] cache_way_hit_reg_scanout; |
| 169 | wire [3:0] cache_way_hit_b; |
| 170 | wire data_parity_0; |
| 171 | wire [3:0] mm_debug_reg_scanin; |
| 172 | wire [3:0] mm_debug_reg_scanout; |
| 173 | wire [3:0] mm_debug; |
| 174 | wire tag_read_mux_control; |
| 175 | |
| 176 | |
| 177 | |
| 178 | |
| 179 | input l2clk; |
| 180 | input scan_in; |
| 181 | input tcu_pce_ov; |
| 182 | input pce; |
| 183 | input tcu_aclk; |
| 184 | input tcu_bclk; |
| 185 | input tcu_se_scancollar_in; |
| 186 | input tcu_se_scancollar_out; |
| 187 | input tcu_array_wr_inhibit; |
| 188 | input tcu_scan_en; |
| 189 | input disable_clear_ubit; |
| 190 | output scan_out; |
| 191 | |
| 192 | input tlb_bypass; // DO NOT CHANGE THIS NAME - IT'S USED BY THE BENCH |
| 193 | input tlb_wr_vld; |
| 194 | input tlb_rd_vld; |
| 195 | input tlb_cam_vld; // DO NOT CHANGE THIS NAME - IT'S USED BY THE BENCH |
| 196 | input [6:0] tlb_rw_index; |
| 197 | input tlb_rw_index_vld; |
| 198 | input tlb_demap; |
| 199 | input tlb_demap_context; |
| 200 | input tlb_demap_all; |
| 201 | input tlb_demap_real; |
| 202 | |
| 203 | input [65:0] tte_tag; |
| 204 | input tte_ubit; |
| 205 | input [2:0] tte_page_size_mask; |
| 206 | input [37:0] tte_data; |
| 207 | input [12:11] tlb_va; // Incoming VA |
| 208 | |
| 209 | // Cache tag compare |
| 210 | input [39:11] cache_ptag_w0; |
| 211 | input [39:11] cache_ptag_w1; |
| 212 | input [39:11] cache_ptag_w2; |
| 213 | input [39:11] cache_ptag_w3; |
| 214 | // |
| 215 | // |
| 216 | // |
| 217 | // |
| 218 | input [3:0] cache_set_vld; |
| 219 | |
| 220 | output [3:0] cache_way_hit; |
| 221 | output cache_hit; |
| 222 | output tlb_cam_hit; |
| 223 | output tlb_cam_mhit; |
| 224 | output tlb_context0_hit; |
| 225 | output [39:13] tlb_pgnum_crit; // PA unflopped |
| 226 | output [39:13] tlb_pgnum; // PA flopped |
| 227 | output [37:0] tlb_tte_data; |
| 228 | output [65:0] tlb_tte_tag; |
| 229 | output tlb_tte_u_bit; |
| 230 | output tlb_tte_data_parity; |
| 231 | |
| 232 | `ifndef FPGA |
| 233 | // synopsys translate_off |
| 234 | `endif |
| 235 | |
| 236 | assign pce_ov = tcu_pce_ov; |
| 237 | assign stop = 1'b0; |
| 238 | assign siclk = tcu_aclk ; |
| 239 | assign soclk = tcu_bclk; |
| 240 | assign se = tcu_scan_en; |
| 241 | |
| 242 | |
| 243 | // 0in bits_on -var {tlb_wr_vld,tlb_rd_vld,tlb_cam_vld,tlb_demap} -max 1 |
| 244 | // 0in bits_on -var {tlb_demap_context,tlb_demap_all,tlb_demap_real} -max 1 |
| 245 | // 0in bits_on -var {tlb_cam_vld,tlb_bypass} -max 1 |
| 246 | // 0in assert -var (~(tlb_demap_context & ~tlb_demap)) -message "Cannot asert tlb_demap_context without tlb_demap" |
| 247 | // 0in assert -var (~(tlb_demap_all & ~tlb_demap)) -message "Cannot asert tlb_demap_all without tlb_demap" |
| 248 | // 0in assert -var (~(tlb_demap_real & ~tlb_demap)) -message "Cannot asert tlb_demap_real without tlb_demap" |
| 249 | // 0in known_driven -var tlb_cam_hit |
| 250 | |
| 251 | |
| 252 | /////////////////////////////////////////////////////////////// |
| 253 | // Input flops |
| 254 | /////////////////////////////////////////////////////////////// |
| 255 | |
| 256 | n2_tlb_tl_128x59_cust_l1clkhdr_ctl_macro in_clken ( |
| 257 | .l2clk(l2clk), |
| 258 | .l1en(pce), |
| 259 | .se(tcu_se_scancollar_in), |
| 260 | .l1clk(l1clk_in), |
| 261 | .pce_ov(pce_ov), |
| 262 | .stop(stop) |
| 263 | ); |
| 264 | |
| 265 | n2_tlb_tl_128x59_cust_l1clkhdr_ctl_macro free_clken ( |
| 266 | .l2clk(l2clk), |
| 267 | .l1en(pce), |
| 268 | .se(se), |
| 269 | .l1clk(l1clk_free), |
| 270 | .pce_ov(pce_ov), |
| 271 | .stop(stop) |
| 272 | ); |
| 273 | |
| 274 | // Put all the CAM controls and data in one latch to avoid races |
| 275 | // Doesn't really matter any more... also this gets split up in |
| 276 | // gate level model |
| 277 | n2_tlb_tl_128x59_cust_sram_msff_mo_macro__fs_1__width_74 cam_ctl_lat ( |
| 278 | .scan_in(cam_ctl_lat_scanin[73:0]), |
| 279 | .scan_out(cam_ctl_lat_scanout[73:0]), |
| 280 | .l1clk (l1clk_in), |
| 281 | .and_clk(l1clk_free), |
| 282 | // 73:8 7 6 |
| 283 | .d ({tte_tag [65:0],tte_ubit ,tlb_wr_vld , |
| 284 | // 5 4 3 2 |
| 285 | tlb_rd_vld,tlb_cam_vld ,tlb_demap ,tlb_demap_context, |
| 286 | // 1 0 |
| 287 | tlb_demap_all,tlb_demap_real}), |
| 288 | .mq ({tte_tag_1[65:0],tte_ubit_1,tlb_wr_1_in_unused, |
| 289 | tlb_rd_1_unused ,tlb_cam_1_in,demap_1_in,demap_context_1 , |
| 290 | demap_all_1 ,demap_real_1 }), |
| 291 | .mq_l (lat_l_unused[73:0]), |
| 292 | // NOTE: Some signals on dout port ARE used by bench (dtlb_wr.v)! |
| 293 | .q ({tte_tag_1_dout[65:0],tte_ubit_1_unused,tlb_wr_1_in_dout, |
| 294 | tlb_rd_1_in_dout,tlb_cam_1_in_dout,demap_1_in_unused,demap_context_1_unused , |
| 295 | demap_all_1_unused ,demap_real_1_unused }), |
| 296 | .q_l (dout_l_unused[73:0]), |
| 297 | .siclk(siclk), |
| 298 | .soclk(soclk) |
| 299 | ); |
| 300 | |
| 301 | // This is strictly for DV |
| 302 | assign demap_page_1_unused = |
| 303 | demap_1_in_unused & ~demap_context_1_unused & ~demap_all_1_unused & |
| 304 | ~demap_real_1_unused; |
| 305 | |
| 306 | n2_tlb_tl_128x59_cust_inv_macro__width_1 wr_inhibit_b_inv ( |
| 307 | .din(tcu_array_wr_inhibit), |
| 308 | .dout(wr_inhibit_) |
| 309 | ); |
| 310 | |
| 311 | n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 tlb_wr_dout_and ( |
| 312 | .din0(tlb_wr_1_in_dout), |
| 313 | .din1(wr_inhibit_), |
| 314 | .dout(tlb_wr_1_dout) |
| 315 | ); |
| 316 | |
| 317 | n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 tlb_rd_dout_and ( |
| 318 | .din0(tlb_rd_1_in_dout), |
| 319 | .din1(wr_inhibit_), |
| 320 | .dout(tlb_rd_1_dout) |
| 321 | ); |
| 322 | |
| 323 | n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 tlb_cam_and ( |
| 324 | .din0(tlb_cam_1_in), |
| 325 | .din1(wr_inhibit_), |
| 326 | .dout(tlb_cam_1) |
| 327 | ); |
| 328 | |
| 329 | n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 tlb_cam_dout_and ( |
| 330 | .din0(tlb_cam_1_in_dout), |
| 331 | .din1(wr_inhibit_), |
| 332 | .dout(tlb_cam_1_dout) |
| 333 | ); |
| 334 | |
| 335 | n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 demap_and ( |
| 336 | .din0(demap_1_in), |
| 337 | .din1(wr_inhibit_), |
| 338 | .dout(demap_1) |
| 339 | ); |
| 340 | |
| 341 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_3 page_size_mask_reg ( |
| 342 | .scan_in(page_size_mask_reg_scanin[2:0]), |
| 343 | .scan_out(page_size_mask_reg_scanout[2:0]), |
| 344 | .l1clk(l1clk_in), |
| 345 | .din(tte_page_size_mask[2:0]), |
| 346 | .dout(tte_page_size_mask_1[2:0]), |
| 347 | .siclk(siclk), |
| 348 | .soclk(soclk) |
| 349 | ); |
| 350 | |
| 351 | n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 disable_clear_ubit_reg ( |
| 352 | .scan_in(disable_clear_ubit_reg_scanin), |
| 353 | .scan_out(disable_clear_ubit_reg_scanout), |
| 354 | .l1clk(l1clk_in), |
| 355 | .din(disable_clear_ubit), |
| 356 | .dout(disable_clear_ubit_1_in), |
| 357 | .siclk(siclk), |
| 358 | .soclk(soclk) |
| 359 | ); |
| 360 | |
| 361 | n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 disable_clear_ubit_and ( |
| 362 | .din0(disable_clear_ubit_1_in), |
| 363 | .din1(wr_inhibit_), |
| 364 | .dout(disable_clear_ubit_1) |
| 365 | ); |
| 366 | |
| 367 | n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 tlb_bypass_reg ( |
| 368 | .scan_in(tlb_bypass_reg_scanin), |
| 369 | .scan_out(tlb_bypass_reg_scanout), |
| 370 | .l1clk(l1clk_in), |
| 371 | .din(tlb_bypass), |
| 372 | .dout(tlb_bypass_1), |
| 373 | .siclk(siclk), |
| 374 | .soclk(soclk) |
| 375 | ); |
| 376 | |
| 377 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_2 vaddr_reg ( |
| 378 | .scan_in(vaddr_reg_scanin[1:0]), |
| 379 | .scan_out(vaddr_reg_scanout[1:0]), |
| 380 | .l1clk(l1clk_in), |
| 381 | .din(tlb_va[12:11]), |
| 382 | .dout(va_1[12:11]), |
| 383 | .siclk(siclk), |
| 384 | .soclk(soclk) |
| 385 | ); |
| 386 | |
| 387 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_38 tte_data_reg ( |
| 388 | .scan_in(tte_data_reg_scanin[37:0]), |
| 389 | .scan_out(tte_data_reg_scanout[37:0]), |
| 390 | .l1clk(l1clk_in), |
| 391 | .din(tte_data[37:0]), |
| 392 | .dout(tte_data_1[37:0]), |
| 393 | .siclk(siclk), |
| 394 | .soclk(soclk) |
| 395 | ); |
| 396 | |
| 397 | |
| 398 | ///////////////////////////////////////////////////////////////////// |
| 399 | // Write index muxing |
| 400 | ////////////////////////////////////////////////////////////////////// |
| 401 | |
| 402 | n2_tlb_tl_128x59_cust_mux_macro__mux_aope__ports_2__width_7 rw_index_mux ( |
| 403 | .din0 (tlb_rw_index[6:0]), |
| 404 | .din1 (tlb_replacement_index[6:0]), |
| 405 | .sel0 (tlb_rw_index_vld), |
| 406 | .dout (rw_index_0[6:0]) |
| 407 | ); |
| 408 | |
| 409 | // The output of this flop is used by the bench (dtlb_wr.vpal) |
| 410 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_7 rw_index_reg ( |
| 411 | .scan_in(rw_index_reg_scanin[6:0]), |
| 412 | .scan_out(rw_index_reg_scanout[6:0]), |
| 413 | .l1clk(l1clk_in), |
| 414 | .din(rw_index_0[6:0]), |
| 415 | .dout(rw_index_1[6:0]), |
| 416 | .siclk(siclk), |
| 417 | .soclk(soclk) |
| 418 | ); |
| 419 | |
| 420 | // This flop is here to mirror the circuit; it has no functional purpose; |
| 421 | // Just want it here for 'debug' even though this signal |
| 422 | // is flopped outside the circuit |
| 423 | n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 rw_index_vld_reg ( |
| 424 | .scan_in(rw_index_vld_reg_scanin), |
| 425 | .scan_out(rw_index_vld_reg_scanout), |
| 426 | .l1clk(l1clk_in), |
| 427 | .din(tlb_rw_index_vld), |
| 428 | .dout(rw_index_vld_unused), |
| 429 | .siclk(siclk), |
| 430 | .soclk(soclk) |
| 431 | ); |
| 432 | |
| 433 | |
| 434 | ///////////////////////////////////////////////////////////////////// |
| 435 | // Array behavioral |
| 436 | ////////////////////////////////////////////////////////////////////// |
| 437 | |
| 438 | n2_tlb_tl_128x59_array array ( |
| 439 | // Inputs |
| 440 | .l1clk (l1clk_free), |
| 441 | .tlb_bypass (tlb_bypass_1), |
| 442 | .tlb_wr_flopped (tlb_wr_1_dout), |
| 443 | .tlb_rd_flopped (tlb_rd_1_dout), |
| 444 | .rw_index (rw_index_1[6:0]), |
| 445 | .tlb_cam (tlb_cam_1), |
| 446 | .tlb_cam_flopped(tlb_cam_1_dout), |
| 447 | .disable_clear_ubit(disable_clear_ubit_1), |
| 448 | .demap (demap_1), |
| 449 | .demap_context (demap_context_1), |
| 450 | .demap_all (demap_all_1), |
| 451 | .demap_real (demap_real_1), |
| 452 | .tte_tag (tte_tag_1[65:0]), |
| 453 | .tte_tag_flopped(tte_tag_1_dout[65:0]), |
| 454 | .tte_ubit (tte_ubit_1), |
| 455 | .tte_page_size_mask(tte_page_size_mask_1[2:0]), |
| 456 | .tte_data (tte_data_1[37:0]), |
| 457 | .va (va_1[12:11]), |
| 458 | // Outputs |
| 459 | .pa (pa_1[39:11]), |
| 460 | .tlb_cam_hit (tlb_cam_hit_1), |
| 461 | .tag_read_mux_control(tag_read_mux_control), |
| 462 | .context0_hit(context0_hit), |
| 463 | .multiple_match(multiple_match), |
| 464 | .rd_tte_data(rd_tte_data[37:0]), |
| 465 | .rd_tte_tag(rd_tte_tag[65:0]), |
| 466 | .rd_tte_u_bit(rd_tte_u_bit), |
| 467 | .tlb_replacement_index(tlb_replacement_index[6:0]) |
| 468 | ); |
| 469 | |
| 470 | // Unflopped output |
| 471 | assign tlb_pgnum_crit[39:13] = pa_1[39:13]; |
| 472 | |
| 473 | ////////////////////////////////////////////////// |
| 474 | // Flop the output data |
| 475 | ////////////////////////////////////////////////// |
| 476 | |
| 477 | n2_tlb_tl_128x59_cust_l1clkhdr_ctl_macro out_clken ( |
| 478 | .l2clk(l2clk), |
| 479 | .l1en(pce), |
| 480 | .se(tcu_se_scancollar_out), |
| 481 | .l1clk(l1clk_out), |
| 482 | .pce_ov(pce_ov), |
| 483 | .stop(stop) |
| 484 | ); |
| 485 | |
| 486 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_3 tlb_cam_hit_reg ( |
| 487 | .scan_in(tlb_cam_hit_reg_scanin[2:0]), |
| 488 | .scan_out(tlb_cam_hit_reg_scanout[2:0]), |
| 489 | .l1clk(l1clk_out), |
| 490 | .din({tlb_cam_hit_1,multiple_match,context0_hit}), |
| 491 | .dout({tlb_cam_hit,tlb_cam_mhit,tlb_context0_hit}), |
| 492 | .siclk(siclk), |
| 493 | .soclk(soclk) |
| 494 | ); |
| 495 | |
| 496 | n2_tlb_tl_128x59_cust_inv_macro__width_1 tlb_cam_mhit_b_inv ( |
| 497 | .din(tlb_cam_mhit), |
| 498 | .dout(tlb_cam_mhit_b) |
| 499 | ); |
| 500 | |
| 501 | n2_tlb_tl_128x59_cust_inv_macro__width_27 pa_1_b_inv ( |
| 502 | .din(pa_1[39:13]), |
| 503 | .dout(pa_1_b[39:13]) |
| 504 | ); |
| 505 | |
| 506 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_27 pa_reg ( |
| 507 | .scan_in(pa_reg_scanin[26:0]), |
| 508 | .scan_out(pa_reg_scanout[26:0]), |
| 509 | .l1clk(l1clk_out), |
| 510 | .din(pa_1_b[39:13]), |
| 511 | .dout(pa_2_b[39:13]), |
| 512 | .siclk(siclk), |
| 513 | .soclk(soclk) |
| 514 | ); |
| 515 | |
| 516 | n2_tlb_tl_128x59_cust_inv_macro__width_27 pa_2_inv ( |
| 517 | .din(pa_2_b[39:13]), |
| 518 | .dout(pa_2[39:13]) |
| 519 | ); |
| 520 | |
| 521 | assign tlb_pgnum[39:13] = pa_2[39:13]; |
| 522 | |
| 523 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_38 tte_data_out_reg ( |
| 524 | .scan_in(tte_data_out_reg_scanin[37:0]), |
| 525 | .scan_out(tte_data_out_reg_scanout[37:0]), |
| 526 | .l1clk(l1clk_out), |
| 527 | .din(rd_tte_data[37:0]), |
| 528 | .dout(tlb_tte_data[37:0]), |
| 529 | .siclk(siclk), |
| 530 | .soclk(soclk) |
| 531 | ); |
| 532 | |
| 533 | n2_tlb_tl_128x59_cust_inv_macro__stack_66c__width_66 rd_tte_tag_b_inv ( |
| 534 | .din(rd_tte_tag[65:0]), |
| 535 | .dout(rd_tte_tag_b[65:0]) |
| 536 | ); |
| 537 | |
| 538 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_66 tte_tag_out_reg ( |
| 539 | .scan_in(tte_tag_out_reg_scanin[65:0]), |
| 540 | .scan_out(tte_tag_out_reg_scanout[65:0]), |
| 541 | .l1clk(l1clk_out), |
| 542 | .din(rd_tte_tag_b[65:0]), |
| 543 | .dout(tlb_tte_tag_b[65:0]), |
| 544 | .siclk(siclk), |
| 545 | .soclk(soclk) |
| 546 | ); |
| 547 | |
| 548 | n2_tlb_tl_128x59_cust_inv_macro__stack_66c__width_66 tlb_tte_tag_inv ( |
| 549 | .din(tlb_tte_tag_b[65:0]), |
| 550 | .dout(tlb_tte_tag[65:0]) |
| 551 | ); |
| 552 | |
| 553 | n2_tlb_tl_128x59_cust_inv_macro__width_1 rd_tte_u_bit_b_inv ( |
| 554 | .din(rd_tte_u_bit), |
| 555 | .dout(rd_tte_u_bit_b) |
| 556 | ); |
| 557 | |
| 558 | n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 tte_u_bit_out_reg ( |
| 559 | .scan_in(tte_u_bit_out_reg_scanin), |
| 560 | .scan_out(tte_u_bit_out_reg_scanout), |
| 561 | .l1clk(l1clk_out), |
| 562 | .din(rd_tte_u_bit_b), |
| 563 | .dout(tlb_tte_u_bit_b), |
| 564 | .siclk(siclk), |
| 565 | .soclk(soclk) |
| 566 | ); |
| 567 | |
| 568 | n2_tlb_tl_128x59_cust_inv_macro__width_1 tlb_tte_u_bit_inv ( |
| 569 | .din(tlb_tte_u_bit_b), |
| 570 | .dout(tlb_tte_u_bit) |
| 571 | ); |
| 572 | |
| 573 | /////////////////////////////////////////////////////////////// |
| 574 | // Tag compare logic |
| 575 | /////////////////////////////////////////////////////////////// |
| 576 | |
| 577 | n2_tlb_tl_128x59_cust_cmp_macro__width_32 way0_cmp ( |
| 578 | .din0 ({cache_ptag_w0[39:11],cache_set_vld[0],1'b0 , 1'b0}), |
| 579 | .din1 ({pa_1[39:11], 1'b1 ,1'b0 , 1'b0}), |
| 580 | .dout (cache_way_hit_in[0]) |
| 581 | ); |
| 582 | n2_tlb_tl_128x59_cust_cmp_macro__width_32 way1_cmp ( |
| 583 | .din0 ({cache_ptag_w1[39:11],cache_set_vld[1],1'b0 , 1'b0}), |
| 584 | .din1 ({pa_1[39:11], 1'b1 ,1'b0 , 1'b0}), |
| 585 | .dout (cache_way_hit_in[1]) |
| 586 | ); |
| 587 | n2_tlb_tl_128x59_cust_cmp_macro__width_32 way2_cmp ( |
| 588 | .din0 ({cache_ptag_w2[39:11],cache_set_vld[2],1'b0 , 1'b0}), |
| 589 | .din1 ({pa_1[39:11], 1'b1 ,1'b0 , 1'b0}), |
| 590 | .dout (cache_way_hit_in[2]) |
| 591 | ); |
| 592 | n2_tlb_tl_128x59_cust_cmp_macro__width_32 way3_cmp ( |
| 593 | .din0 ({cache_ptag_w3[39:11],cache_set_vld[3],1'b0 , 1'b0}), |
| 594 | .din1 ({pa_1[39:11], 1'b1 ,1'b0 , 1'b0}), |
| 595 | .dout (cache_way_hit_in[3]) |
| 596 | ); |
| 597 | // |
| 598 | // |
| 599 | // |
| 600 | // |
| 601 | // |
| 602 | // |
| 603 | // |
| 604 | // |
| 605 | // |
| 606 | // |
| 607 | // |
| 608 | // |
| 609 | // |
| 610 | // |
| 611 | // |
| 612 | // |
| 613 | // |
| 614 | // |
| 615 | // |
| 616 | // |
| 617 | |
| 618 | n2_tlb_tl_128x59_cust_inv_macro__width_4 cache_way_hit_in_b_inv ( |
| 619 | .din(cache_way_hit_in[3:0]), |
| 620 | .dout(cache_way_hit_in_b[3:0]) |
| 621 | ); |
| 622 | |
| 623 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_4 cache_way_hit_reg ( |
| 624 | .scan_in(cache_way_hit_reg_scanin[3:0]), |
| 625 | .scan_out(cache_way_hit_reg_scanout[3:0]), |
| 626 | .l1clk(l1clk_out), |
| 627 | .din(cache_way_hit_in_b[3:0]), |
| 628 | .dout(cache_way_hit_b[3:0]), |
| 629 | .siclk(siclk), |
| 630 | .soclk(soclk) |
| 631 | ); |
| 632 | |
| 633 | n2_tlb_tl_128x59_cust_inv_macro__width_4 cache_way_hit_inv ( |
| 634 | .din(cache_way_hit_b[3:0]), |
| 635 | .dout(cache_way_hit[3:0]) |
| 636 | ); |
| 637 | |
| 638 | n2_tlb_tl_128x59_cust_mux_macro__mux_aonpe__ports_4__width_1 cache_hit_or ( |
| 639 | .din0 (cache_way_hit[0]), |
| 640 | .din1 (cache_way_hit[1]), |
| 641 | .din2 (cache_way_hit[2]), |
| 642 | .din3 (cache_way_hit[3]), |
| 643 | // |
| 644 | // |
| 645 | // |
| 646 | // |
| 647 | .sel0 (tlb_cam_mhit_b), |
| 648 | .sel1 (tlb_cam_mhit_b), |
| 649 | .sel2 (tlb_cam_mhit_b), |
| 650 | .sel3 (tlb_cam_mhit_b), |
| 651 | // |
| 652 | // |
| 653 | // |
| 654 | // |
| 655 | .dout (cache_hit) |
| 656 | ); |
| 657 | |
| 658 | /////////////////////////////////////////////////////////////// |
| 659 | // Parity checks for tag and data |
| 660 | /////////////////////////////////////////////////////////////// |
| 661 | |
| 662 | n2_tlb_tl_128x59_cust_prty_macro__width_32 dprty0 ( |
| 663 | .din (tlb_tte_data[31:0]), |
| 664 | .dout (data_parity_0) |
| 665 | ); |
| 666 | n2_tlb_tl_128x59_cust_prty_macro__width_8 dprty1 ( |
| 667 | .din ({tlb_tte_data[36:32],data_parity_0,2'b0}), |
| 668 | .dout (tlb_tte_data_parity) |
| 669 | ); |
| 670 | |
| 671 | |
| 672 | |
| 673 | // Flops for circuit use |
| 674 | |
| 675 | n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_4 mm_debug_reg ( |
| 676 | .scan_in(mm_debug_reg_scanin[3:0]), |
| 677 | .scan_out(mm_debug_reg_scanout[3:0]), |
| 678 | .l1clk(l1clk_in), |
| 679 | .din(mm_debug[3:0]), |
| 680 | .dout(mm_debug[3:0]), |
| 681 | .siclk(siclk), |
| 682 | .soclk(soclk) |
| 683 | ); |
| 684 | |
| 685 | assign tag_read_mux_control = mm_debug[3]; |
| 686 | |
| 687 | |
| 688 | |
| 689 | supply0 vss; // <- port for ground |
| 690 | supply1 vdd; // <- port for power |
| 691 | // Fullscan hookups begin |
| 692 | assign tte_data_reg_scanin [0] = scan_in ; |
| 693 | assign tte_data_reg_scanin [37:1] = tte_data_reg_scanout [36:0]; |
| 694 | |
| 695 | assign vaddr_reg_scanin [0] = tte_data_reg_scanout [37]; |
| 696 | assign vaddr_reg_scanin [1] = vaddr_reg_scanout [0]; |
| 697 | |
| 698 | assign rw_index_reg_scanin [5] = vaddr_reg_scanout [1]; |
| 699 | assign rw_index_reg_scanin [4] = rw_index_reg_scanout [5]; |
| 700 | assign rw_index_reg_scanin [3] = rw_index_reg_scanout [4]; |
| 701 | assign rw_index_reg_scanin [0] = rw_index_reg_scanout [3]; |
| 702 | assign rw_index_reg_scanin [1] = rw_index_reg_scanout [0]; |
| 703 | assign rw_index_reg_scanin [2] = rw_index_reg_scanout [1]; |
| 704 | assign rw_index_reg_scanin [6] = rw_index_reg_scanout [2]; |
| 705 | |
| 706 | assign rw_index_vld_reg_scanin = rw_index_reg_scanout [6]; |
| 707 | |
| 708 | assign cam_ctl_lat_scanin [6] = rw_index_vld_reg_scanout ; |
| 709 | assign cam_ctl_lat_scanin [5] = cam_ctl_lat_scanout [6]; |
| 710 | assign cam_ctl_lat_scanin [58] = cam_ctl_lat_scanout [5]; |
| 711 | assign cam_ctl_lat_scanin [60:59] = cam_ctl_lat_scanout [59:58]; |
| 712 | assign cam_ctl_lat_scanin [37] = cam_ctl_lat_scanout [60]; |
| 713 | assign cam_ctl_lat_scanin [56:38] = cam_ctl_lat_scanout [55:37]; |
| 714 | |
| 715 | assign page_size_mask_reg_scanin [0] = cam_ctl_lat_scanout [56]; |
| 716 | |
| 717 | assign cam_ctl_lat_scanin [21] = page_size_mask_reg_scanout [0]; |
| 718 | assign cam_ctl_lat_scanin [26:22] = cam_ctl_lat_scanout [25:21]; |
| 719 | |
| 720 | assign page_size_mask_reg_scanin [1] = cam_ctl_lat_scanout [26]; |
| 721 | |
| 722 | assign cam_ctl_lat_scanin [27] = page_size_mask_reg_scanout [1]; |
| 723 | assign cam_ctl_lat_scanin [29:28] = cam_ctl_lat_scanout [28:27]; |
| 724 | assign cam_ctl_lat_scanin [31] = cam_ctl_lat_scanout [29]; |
| 725 | assign cam_ctl_lat_scanin [33:32] = cam_ctl_lat_scanout [32:31]; |
| 726 | |
| 727 | assign page_size_mask_reg_scanin [2] = cam_ctl_lat_scanout [33]; |
| 728 | |
| 729 | assign cam_ctl_lat_scanin [34] = page_size_mask_reg_scanout [2]; |
| 730 | assign cam_ctl_lat_scanin [36:35] = cam_ctl_lat_scanout [35:34]; |
| 731 | assign cam_ctl_lat_scanin [57] = cam_ctl_lat_scanout [36]; |
| 732 | assign cam_ctl_lat_scanin [3] = cam_ctl_lat_scanout [57]; |
| 733 | assign cam_ctl_lat_scanin [4] = cam_ctl_lat_scanout [3]; |
| 734 | assign cam_ctl_lat_scanin [61] = cam_ctl_lat_scanout [4]; |
| 735 | assign cam_ctl_lat_scanin [73:62] = cam_ctl_lat_scanout [72:61]; |
| 736 | assign cam_ctl_lat_scanin [8] = cam_ctl_lat_scanout [73]; |
| 737 | assign cam_ctl_lat_scanin [20:9] = cam_ctl_lat_scanout [19:8]; |
| 738 | |
| 739 | assign mm_debug_reg_scanin [3] = cam_ctl_lat_scanout [20]; |
| 740 | assign mm_debug_reg_scanin [2:0] = mm_debug_reg_scanout [3:1]; |
| 741 | |
| 742 | assign cam_ctl_lat_scanin [7] = mm_debug_reg_scanout [0]; |
| 743 | |
| 744 | assign disable_clear_ubit_reg_scanin = cam_ctl_lat_scanout [7]; |
| 745 | |
| 746 | assign cam_ctl_lat_scanin [30] = disable_clear_ubit_reg_scanout ; |
| 747 | assign cam_ctl_lat_scanin [0] = cam_ctl_lat_scanout [30]; |
| 748 | assign cam_ctl_lat_scanin [2] = cam_ctl_lat_scanout [0]; |
| 749 | assign cam_ctl_lat_scanin [1] = cam_ctl_lat_scanout [2]; |
| 750 | |
| 751 | assign tlb_bypass_reg_scanin = cam_ctl_lat_scanout [1]; |
| 752 | |
| 753 | assign tlb_cam_hit_reg_scanin [2] = tlb_bypass_reg_scanout ; |
| 754 | assign tlb_cam_hit_reg_scanin [0] = tlb_cam_hit_reg_scanout [2]; |
| 755 | |
| 756 | assign tte_tag_out_reg_scanin [22] = tlb_cam_hit_reg_scanout [0]; |
| 757 | |
| 758 | assign tte_u_bit_out_reg_scanin = tte_tag_out_reg_scanout [22]; |
| 759 | |
| 760 | assign tte_tag_out_reg_scanin [12] = tte_u_bit_out_reg_scanout ; |
| 761 | assign tte_tag_out_reg_scanin [11:0] = tte_tag_out_reg_scanout [12:1]; |
| 762 | assign tte_tag_out_reg_scanin [65] = tte_tag_out_reg_scanout [0]; |
| 763 | assign tte_tag_out_reg_scanin [64:53] = tte_tag_out_reg_scanout [65:54]; |
| 764 | assign tte_tag_out_reg_scanin [49] = tte_tag_out_reg_scanout [53]; |
| 765 | assign tte_tag_out_reg_scanin [28] = tte_tag_out_reg_scanout [49]; |
| 766 | assign tte_tag_out_reg_scanin [27:23] = tte_tag_out_reg_scanout [28:24]; |
| 767 | assign tte_tag_out_reg_scanin [21] = tte_tag_out_reg_scanout [23]; |
| 768 | assign tte_tag_out_reg_scanin [20:13] = tte_tag_out_reg_scanout [21:14]; |
| 769 | assign tte_tag_out_reg_scanin [48] = tte_tag_out_reg_scanout [13]; |
| 770 | assign tte_tag_out_reg_scanin [47:29] = tte_tag_out_reg_scanout [48:30]; |
| 771 | assign tte_tag_out_reg_scanin [52] = tte_tag_out_reg_scanout [29]; |
| 772 | assign tte_tag_out_reg_scanin [51:50] = tte_tag_out_reg_scanout [52:51]; |
| 773 | |
| 774 | assign tte_data_out_reg_scanin [0] = tte_tag_out_reg_scanout [50]; |
| 775 | assign tte_data_out_reg_scanin [37:1] = tte_data_out_reg_scanout [36:0]; |
| 776 | |
| 777 | assign cache_way_hit_reg_scanin [0] = tte_data_out_reg_scanout [37]; |
| 778 | assign cache_way_hit_reg_scanin [3:1] = cache_way_hit_reg_scanout [2:0]; |
| 779 | |
| 780 | assign pa_reg_scanin [0] = cache_way_hit_reg_scanout [3]; |
| 781 | assign pa_reg_scanin [26:1] = pa_reg_scanout [25:0]; |
| 782 | |
| 783 | assign tlb_cam_hit_reg_scanin [1] = pa_reg_scanout [26]; |
| 784 | |
| 785 | assign scan_out = tlb_cam_hit_reg_scanout [1]; |
| 786 | // Fullscan hookups end |
| 787 | |
| 788 | `ifndef FPGA |
| 789 | // synopsys translate_on |
| 790 | `endif |
| 791 | |
| 792 | endmodule |
| 793 | |
| 794 | |
| 795 | |
| 796 | |
| 797 | |
| 798 | |
| 799 | // any PARAMS parms go into naming of macro |
| 800 | |
| 801 | module n2_tlb_tl_128x59_cust_l1clkhdr_ctl_macro ( |
| 802 | l2clk, |
| 803 | l1en, |
| 804 | pce_ov, |
| 805 | stop, |
| 806 | se, |
| 807 | l1clk); |
| 808 | |
| 809 | |
| 810 | input l2clk; |
| 811 | input l1en; |
| 812 | input pce_ov; |
| 813 | input stop; |
| 814 | input se; |
| 815 | output l1clk; |
| 816 | |
| 817 | |
| 818 | |
| 819 | |
| 820 | |
| 821 | cl_sc1_l1hdr_8x c_0 ( |
| 822 | |
| 823 | |
| 824 | .l2clk(l2clk), |
| 825 | .pce(l1en), |
| 826 | .l1clk(l1clk), |
| 827 | .se(se), |
| 828 | .pce_ov(pce_ov), |
| 829 | .stop(stop) |
| 830 | ); |
| 831 | |
| 832 | |
| 833 | |
| 834 | endmodule |
| 835 | |
| 836 | |
| 837 | |
| 838 | |
| 839 | |
| 840 | |
| 841 | |
| 842 | |
| 843 | |
| 844 | // |
| 845 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops |
| 846 | // |
| 847 | // |
| 848 | |
| 849 | |
| 850 | |
| 851 | |
| 852 | |
| 853 | module n2_tlb_tl_128x59_cust_sram_msff_mo_macro__fs_1__width_74 ( |
| 854 | d, |
| 855 | scan_in, |
| 856 | l1clk, |
| 857 | and_clk, |
| 858 | siclk, |
| 859 | soclk, |
| 860 | mq, |
| 861 | mq_l, |
| 862 | scan_out, |
| 863 | q, |
| 864 | q_l); |
| 865 | input [73:0] d; |
| 866 | input [73:0] scan_in; |
| 867 | input l1clk; |
| 868 | input and_clk; |
| 869 | input siclk; |
| 870 | input soclk; |
| 871 | output [73:0] mq; |
| 872 | output [73:0] mq_l; |
| 873 | output [73:0] scan_out; |
| 874 | output [73:0] q; |
| 875 | output [73:0] q_l; |
| 876 | |
| 877 | |
| 878 | |
| 879 | |
| 880 | |
| 881 | |
| 882 | new_dlata #(74) d0_0 ( |
| 883 | .d(d[73:0]), |
| 884 | .si(scan_in[73:0]), |
| 885 | .so(scan_out[73:0]), |
| 886 | .l1clk(l1clk), |
| 887 | .and_clk(and_clk), |
| 888 | .siclk(siclk), |
| 889 | .soclk(soclk), |
| 890 | .q(q[73:0]), |
| 891 | .q_l(q_l[73:0]), |
| 892 | .mq(mq[73:0]), |
| 893 | .mq_l(mq_l[73:0]) |
| 894 | ); |
| 895 | |
| 896 | |
| 897 | |
| 898 | |
| 899 | |
| 900 | |
| 901 | |
| 902 | |
| 903 | |
| 904 | |
| 905 | //place::generic_place($width,$stack,$left); |
| 906 | |
| 907 | endmodule |
| 908 | |
| 909 | |
| 910 | |
| 911 | |
| 912 | |
| 913 | // |
| 914 | // invert macro |
| 915 | // |
| 916 | // |
| 917 | |
| 918 | |
| 919 | |
| 920 | |
| 921 | |
| 922 | module n2_tlb_tl_128x59_cust_inv_macro__width_1 ( |
| 923 | din, |
| 924 | dout); |
| 925 | input [0:0] din; |
| 926 | output [0:0] dout; |
| 927 | |
| 928 | |
| 929 | |
| 930 | |
| 931 | |
| 932 | |
| 933 | inv #(1) d0_0 ( |
| 934 | .in(din[0:0]), |
| 935 | .out(dout[0:0]) |
| 936 | ); |
| 937 | |
| 938 | |
| 939 | |
| 940 | |
| 941 | |
| 942 | |
| 943 | |
| 944 | |
| 945 | |
| 946 | endmodule |
| 947 | |
| 948 | |
| 949 | |
| 950 | |
| 951 | |
| 952 | // |
| 953 | // and macro for ports = 2,3,4 |
| 954 | // |
| 955 | // |
| 956 | |
| 957 | |
| 958 | |
| 959 | |
| 960 | |
| 961 | module n2_tlb_tl_128x59_cust_and_macro__ports_2__width_1 ( |
| 962 | din0, |
| 963 | din1, |
| 964 | dout); |
| 965 | input [0:0] din0; |
| 966 | input [0:0] din1; |
| 967 | output [0:0] dout; |
| 968 | |
| 969 | |
| 970 | |
| 971 | |
| 972 | |
| 973 | |
| 974 | and2 #(1) d0_0 ( |
| 975 | .in0(din0[0:0]), |
| 976 | .in1(din1[0:0]), |
| 977 | .out(dout[0:0]) |
| 978 | ); |
| 979 | |
| 980 | |
| 981 | |
| 982 | |
| 983 | |
| 984 | |
| 985 | |
| 986 | |
| 987 | |
| 988 | endmodule |
| 989 | |
| 990 | |
| 991 | |
| 992 | |
| 993 | |
| 994 | |
| 995 | |
| 996 | |
| 997 | |
| 998 | // any PARAMS parms go into naming of macro |
| 999 | |
| 1000 | module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_3 ( |
| 1001 | din, |
| 1002 | l1clk, |
| 1003 | scan_in, |
| 1004 | siclk, |
| 1005 | soclk, |
| 1006 | dout, |
| 1007 | scan_out); |
| 1008 | wire [2:0] fdin; |
| 1009 | |
| 1010 | input [2:0] din; |
| 1011 | input l1clk; |
| 1012 | input [2:0] scan_in; |
| 1013 | |
| 1014 | |
| 1015 | input siclk; |
| 1016 | input soclk; |
| 1017 | |
| 1018 | output [2:0] dout; |
| 1019 | output [2:0] scan_out; |
| 1020 | assign fdin[2:0] = din[2:0]; |
| 1021 | |
| 1022 | |
| 1023 | |
| 1024 | |
| 1025 | |
| 1026 | |
| 1027 | dff #(3) d0_0 ( |
| 1028 | .l1clk(l1clk), |
| 1029 | .siclk(siclk), |
| 1030 | .soclk(soclk), |
| 1031 | .d(fdin[2:0]), |
| 1032 | .si(scan_in[2:0]), |
| 1033 | .so(scan_out[2:0]), |
| 1034 | .q(dout[2:0]) |
| 1035 | ); |
| 1036 | |
| 1037 | |
| 1038 | |
| 1039 | |
| 1040 | |
| 1041 | |
| 1042 | |
| 1043 | |
| 1044 | |
| 1045 | |
| 1046 | |
| 1047 | |
| 1048 | endmodule |
| 1049 | |
| 1050 | |
| 1051 | |
| 1052 | |
| 1053 | |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 | |
| 1058 | |
| 1059 | |
| 1060 | |
| 1061 | |
| 1062 | // any PARAMS parms go into naming of macro |
| 1063 | |
| 1064 | module n2_tlb_tl_128x59_cust_msff_ctl_macro__width_1 ( |
| 1065 | din, |
| 1066 | l1clk, |
| 1067 | scan_in, |
| 1068 | siclk, |
| 1069 | soclk, |
| 1070 | dout, |
| 1071 | scan_out); |
| 1072 | wire [0:0] fdin; |
| 1073 | |
| 1074 | input [0:0] din; |
| 1075 | input l1clk; |
| 1076 | input scan_in; |
| 1077 | |
| 1078 | |
| 1079 | input siclk; |
| 1080 | input soclk; |
| 1081 | |
| 1082 | output [0:0] dout; |
| 1083 | output scan_out; |
| 1084 | assign fdin[0:0] = din[0:0]; |
| 1085 | |
| 1086 | |
| 1087 | |
| 1088 | |
| 1089 | |
| 1090 | |
| 1091 | dff #(1) d0_0 ( |
| 1092 | .l1clk(l1clk), |
| 1093 | .siclk(siclk), |
| 1094 | .soclk(soclk), |
| 1095 | .d(fdin[0:0]), |
| 1096 | .si(scan_in), |
| 1097 | .so(scan_out), |
| 1098 | .q(dout[0:0]) |
| 1099 | ); |
| 1100 | |
| 1101 | |
| 1102 | |
| 1103 | |
| 1104 | |
| 1105 | |
| 1106 | |
| 1107 | |
| 1108 | |
| 1109 | |
| 1110 | |
| 1111 | |
| 1112 | endmodule |
| 1113 | |
| 1114 | |
| 1115 | |
| 1116 | |
| 1117 | |
| 1118 | |
| 1119 | |
| 1120 | |
| 1121 | |
| 1122 | |
| 1123 | |
| 1124 | |
| 1125 | |
| 1126 | // any PARAMS parms go into naming of macro |
| 1127 | |
| 1128 | module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_2 ( |
| 1129 | din, |
| 1130 | l1clk, |
| 1131 | scan_in, |
| 1132 | siclk, |
| 1133 | soclk, |
| 1134 | dout, |
| 1135 | scan_out); |
| 1136 | wire [1:0] fdin; |
| 1137 | |
| 1138 | input [1:0] din; |
| 1139 | input l1clk; |
| 1140 | input [1:0] scan_in; |
| 1141 | |
| 1142 | |
| 1143 | input siclk; |
| 1144 | input soclk; |
| 1145 | |
| 1146 | output [1:0] dout; |
| 1147 | output [1:0] scan_out; |
| 1148 | assign fdin[1:0] = din[1:0]; |
| 1149 | |
| 1150 | |
| 1151 | |
| 1152 | |
| 1153 | |
| 1154 | |
| 1155 | dff #(2) d0_0 ( |
| 1156 | .l1clk(l1clk), |
| 1157 | .siclk(siclk), |
| 1158 | .soclk(soclk), |
| 1159 | .d(fdin[1:0]), |
| 1160 | .si(scan_in[1:0]), |
| 1161 | .so(scan_out[1:0]), |
| 1162 | .q(dout[1:0]) |
| 1163 | ); |
| 1164 | |
| 1165 | |
| 1166 | |
| 1167 | |
| 1168 | |
| 1169 | |
| 1170 | |
| 1171 | |
| 1172 | |
| 1173 | |
| 1174 | |
| 1175 | |
| 1176 | endmodule |
| 1177 | |
| 1178 | |
| 1179 | |
| 1180 | |
| 1181 | |
| 1182 | |
| 1183 | |
| 1184 | |
| 1185 | |
| 1186 | |
| 1187 | |
| 1188 | |
| 1189 | |
| 1190 | // any PARAMS parms go into naming of macro |
| 1191 | |
| 1192 | module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_38 ( |
| 1193 | din, |
| 1194 | l1clk, |
| 1195 | scan_in, |
| 1196 | siclk, |
| 1197 | soclk, |
| 1198 | dout, |
| 1199 | scan_out); |
| 1200 | wire [37:0] fdin; |
| 1201 | |
| 1202 | input [37:0] din; |
| 1203 | input l1clk; |
| 1204 | input [37:0] scan_in; |
| 1205 | |
| 1206 | |
| 1207 | input siclk; |
| 1208 | input soclk; |
| 1209 | |
| 1210 | output [37:0] dout; |
| 1211 | output [37:0] scan_out; |
| 1212 | assign fdin[37:0] = din[37:0]; |
| 1213 | |
| 1214 | |
| 1215 | |
| 1216 | |
| 1217 | |
| 1218 | |
| 1219 | dff #(38) d0_0 ( |
| 1220 | .l1clk(l1clk), |
| 1221 | .siclk(siclk), |
| 1222 | .soclk(soclk), |
| 1223 | .d(fdin[37:0]), |
| 1224 | .si(scan_in[37:0]), |
| 1225 | .so(scan_out[37:0]), |
| 1226 | .q(dout[37:0]) |
| 1227 | ); |
| 1228 | |
| 1229 | |
| 1230 | |
| 1231 | |
| 1232 | |
| 1233 | |
| 1234 | |
| 1235 | |
| 1236 | |
| 1237 | |
| 1238 | |
| 1239 | |
| 1240 | endmodule |
| 1241 | |
| 1242 | |
| 1243 | |
| 1244 | |
| 1245 | |
| 1246 | |
| 1247 | |
| 1248 | |
| 1249 | |
| 1250 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1251 | // also for pass-gate with decoder |
| 1252 | |
| 1253 | |
| 1254 | |
| 1255 | |
| 1256 | |
| 1257 | // any PARAMS parms go into naming of macro |
| 1258 | |
| 1259 | module n2_tlb_tl_128x59_cust_mux_macro__mux_aope__ports_2__width_7 ( |
| 1260 | din0, |
| 1261 | din1, |
| 1262 | sel0, |
| 1263 | dout); |
| 1264 | wire psel0; |
| 1265 | wire psel1; |
| 1266 | |
| 1267 | input [6:0] din0; |
| 1268 | input [6:0] din1; |
| 1269 | input sel0; |
| 1270 | output [6:0] dout; |
| 1271 | |
| 1272 | |
| 1273 | |
| 1274 | |
| 1275 | |
| 1276 | cl_dp1_penc2_8x c0_0 ( |
| 1277 | .sel0(sel0), |
| 1278 | .psel0(psel0), |
| 1279 | .psel1(psel1) |
| 1280 | ); |
| 1281 | |
| 1282 | mux2s #(7) d0_0 ( |
| 1283 | .sel0(psel0), |
| 1284 | .sel1(psel1), |
| 1285 | .in0(din0[6:0]), |
| 1286 | .in1(din1[6:0]), |
| 1287 | .dout(dout[6:0]) |
| 1288 | ); |
| 1289 | |
| 1290 | |
| 1291 | |
| 1292 | |
| 1293 | |
| 1294 | |
| 1295 | |
| 1296 | |
| 1297 | |
| 1298 | |
| 1299 | |
| 1300 | |
| 1301 | |
| 1302 | endmodule |
| 1303 | |
| 1304 | |
| 1305 | |
| 1306 | |
| 1307 | |
| 1308 | |
| 1309 | // any PARAMS parms go into naming of macro |
| 1310 | |
| 1311 | module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_7 ( |
| 1312 | din, |
| 1313 | l1clk, |
| 1314 | scan_in, |
| 1315 | siclk, |
| 1316 | soclk, |
| 1317 | dout, |
| 1318 | scan_out); |
| 1319 | wire [6:0] fdin; |
| 1320 | |
| 1321 | input [6:0] din; |
| 1322 | input l1clk; |
| 1323 | input [6:0] scan_in; |
| 1324 | |
| 1325 | |
| 1326 | input siclk; |
| 1327 | input soclk; |
| 1328 | |
| 1329 | output [6:0] dout; |
| 1330 | output [6:0] scan_out; |
| 1331 | assign fdin[6:0] = din[6:0]; |
| 1332 | |
| 1333 | |
| 1334 | |
| 1335 | |
| 1336 | |
| 1337 | |
| 1338 | dff #(7) d0_0 ( |
| 1339 | .l1clk(l1clk), |
| 1340 | .siclk(siclk), |
| 1341 | .soclk(soclk), |
| 1342 | .d(fdin[6:0]), |
| 1343 | .si(scan_in[6:0]), |
| 1344 | .so(scan_out[6:0]), |
| 1345 | .q(dout[6:0]) |
| 1346 | ); |
| 1347 | |
| 1348 | |
| 1349 | |
| 1350 | |
| 1351 | |
| 1352 | |
| 1353 | |
| 1354 | |
| 1355 | |
| 1356 | |
| 1357 | |
| 1358 | |
| 1359 | endmodule |
| 1360 | |
| 1361 | |
| 1362 | |
| 1363 | |
| 1364 | |
| 1365 | |
| 1366 | |
| 1367 | |
| 1368 | |
| 1369 | module n2_tlb_tl_128x59_array ( |
| 1370 | l1clk, |
| 1371 | disable_clear_ubit, |
| 1372 | tlb_bypass, |
| 1373 | tlb_wr_flopped, |
| 1374 | tlb_rd_flopped, |
| 1375 | rw_index, |
| 1376 | tlb_cam, |
| 1377 | tlb_cam_flopped, |
| 1378 | demap, |
| 1379 | demap_context, |
| 1380 | demap_all, |
| 1381 | demap_real, |
| 1382 | tte_tag, |
| 1383 | tte_tag_flopped, |
| 1384 | tte_ubit, |
| 1385 | tte_page_size_mask, |
| 1386 | tte_data, |
| 1387 | va, |
| 1388 | tag_read_mux_control, |
| 1389 | pa, |
| 1390 | tlb_cam_hit, |
| 1391 | context0_hit, |
| 1392 | multiple_match, |
| 1393 | rd_tte_data, |
| 1394 | rd_tte_tag, |
| 1395 | rd_tte_u_bit, |
| 1396 | tlb_replacement_index) ; |
| 1397 | wire [127:0] ram_wwl; |
| 1398 | wire [127:0] ram_rwl; |
| 1399 | wire [127:0] valid; |
| 1400 | wire force_data_to_x; |
| 1401 | wire [127:0] used; |
| 1402 | |
| 1403 | |
| 1404 | `define ENTRIES 128 |
| 1405 | `define INDEX 6 |
| 1406 | |
| 1407 | input l1clk; |
| 1408 | input disable_clear_ubit; |
| 1409 | |
| 1410 | input tlb_bypass; |
| 1411 | input tlb_wr_flopped; |
| 1412 | input tlb_rd_flopped; |
| 1413 | input [`INDEX:0] rw_index; |
| 1414 | input tlb_cam; |
| 1415 | input tlb_cam_flopped; |
| 1416 | input demap; |
| 1417 | input demap_context; |
| 1418 | input demap_all; |
| 1419 | input demap_real; |
| 1420 | |
| 1421 | input [65:0] tte_tag; |
| 1422 | input [65:0] tte_tag_flopped; |
| 1423 | input tte_ubit; |
| 1424 | input [2:0] tte_page_size_mask; |
| 1425 | input [37:0] tte_data; |
| 1426 | input [12:11] va; // Incoming VA |
| 1427 | |
| 1428 | input tag_read_mux_control; |
| 1429 | |
| 1430 | output [39:11] pa; |
| 1431 | output tlb_cam_hit; |
| 1432 | output context0_hit; |
| 1433 | output multiple_match; |
| 1434 | output [37:0] rd_tte_data; |
| 1435 | output [65:0] rd_tte_tag; |
| 1436 | output rd_tte_u_bit; |
| 1437 | output [`INDEX:0] tlb_replacement_index; |
| 1438 | |
| 1439 | |
| 1440 | |
| 1441 | |
| 1442 | |
| 1443 | `define VA_39 40 |
| 1444 | `define VA_28 29 |
| 1445 | `define VA_27 28 |
| 1446 | `define VA_22 23 |
| 1447 | `define VA_21 21 |
| 1448 | `define VA_16 16 |
| 1449 | `define VA_15 15 |
| 1450 | `define VA_13 13 |
| 1451 | |
| 1452 | |
| 1453 | |
| 1454 | |
| 1455 | n2_tlb_tl_128x59_cam cam( |
| 1456 | .l1clk(l1clk), |
| 1457 | .tlb_bypass(tlb_bypass), |
| 1458 | .tlb_wr_flopped(tlb_wr_flopped), |
| 1459 | .tlb_rd_flopped(tlb_rd_flopped), |
| 1460 | .rw_index(rw_index[6:0]), |
| 1461 | .tlb_cam(tlb_cam), |
| 1462 | .tlb_cam_flopped(tlb_cam_flopped), |
| 1463 | .demap(demap), |
| 1464 | .demap_context(demap_context), |
| 1465 | .demap_all(demap_all), |
| 1466 | .demap_real(demap_real), |
| 1467 | .tte_tag(tte_tag[65:0]), |
| 1468 | .tte_tag_flopped(tte_tag_flopped[65:0]), |
| 1469 | .tte_page_size_mask(tte_page_size_mask[2:0]), |
| 1470 | .tag_read_mux_control(tag_read_mux_control), |
| 1471 | .tlb_cam_hit(tlb_cam_hit), |
| 1472 | .context0_hit(context0_hit), |
| 1473 | .rd_tte_tag(rd_tte_tag[65:0]), |
| 1474 | .ram_wwl(ram_wwl[127:0]), |
| 1475 | .ram_rwl(ram_rwl[127:0]), |
| 1476 | .valid(valid[127:0])); |
| 1477 | |
| 1478 | n2_tlb_tl_128x59_ram ram( |
| 1479 | .va ({tte_tag_flopped[`VA_39:`VA_28], |
| 1480 | tte_tag_flopped[`VA_27:`VA_22], |
| 1481 | tte_tag_flopped[`VA_21:`VA_16], |
| 1482 | tte_tag_flopped[`VA_15:`VA_13], |
| 1483 | va[12:11]}), |
| 1484 | .l1clk(l1clk), |
| 1485 | .tlb_bypass(tlb_bypass), |
| 1486 | .tlb_cam_flopped(tlb_cam_flopped), |
| 1487 | .ram_wwl(ram_wwl[127:0]), |
| 1488 | .ram_rwl(ram_rwl[127:0]), |
| 1489 | .tte_data(tte_data[37:0]), |
| 1490 | .force_data_to_x(force_data_to_x), |
| 1491 | .pa(pa[39:11]), |
| 1492 | .rd_tte_data(rd_tte_data[37:0]) |
| 1493 | ); |
| 1494 | |
| 1495 | n2_tlb_tl_128x59_multihit multihit ( |
| 1496 | .tlb_cam_mhit (multiple_match ), |
| 1497 | .ram_rwl(ram_rwl[127:0]), |
| 1498 | .tlb_bypass(tlb_bypass), |
| 1499 | .force_data_to_x(force_data_to_x) |
| 1500 | ); |
| 1501 | |
| 1502 | n2_tlb_tl_128x59_ubit ubit( |
| 1503 | .l1clk(l1clk), |
| 1504 | .disable_clear_ubit(disable_clear_ubit), |
| 1505 | .tlb_bypass(tlb_bypass), |
| 1506 | .ram_rwl(ram_rwl[127:0]), |
| 1507 | .ram_wwl(ram_wwl[127:0]), |
| 1508 | .tte_ubit(tte_ubit), |
| 1509 | .tlb_wr_flopped(tlb_wr_flopped), |
| 1510 | .tlb_rd_flopped(tlb_rd_flopped), |
| 1511 | .tlb_cam_flopped(tlb_cam_flopped), |
| 1512 | .used(used[127:0]), |
| 1513 | .rd_tte_u_bit(rd_tte_u_bit)); |
| 1514 | |
| 1515 | n2_tlb_tl_128x59_repl_index repl_index( |
| 1516 | .l1clk(l1clk), |
| 1517 | .used(used[127:0]), |
| 1518 | .valid(valid[127:0]), |
| 1519 | .tlb_replacement_index(tlb_replacement_index[6:0])); |
| 1520 | |
| 1521 | |
| 1522 | supply0 vss; // <- port for ground |
| 1523 | supply1 vdd; // <- port for power |
| 1524 | endmodule |
| 1525 | |
| 1526 | |
| 1527 | |
| 1528 | `ifndef FPGA |
| 1529 | module n2_tlb_tl_128x59_cam ( |
| 1530 | l1clk, |
| 1531 | tlb_bypass, |
| 1532 | tlb_wr_flopped, |
| 1533 | tlb_rd_flopped, |
| 1534 | rw_index, |
| 1535 | tlb_cam, |
| 1536 | tlb_cam_flopped, |
| 1537 | demap, |
| 1538 | demap_context, |
| 1539 | demap_all, |
| 1540 | demap_real, |
| 1541 | tte_tag, |
| 1542 | tte_tag_flopped, |
| 1543 | tte_page_size_mask, |
| 1544 | tag_read_mux_control, |
| 1545 | tlb_cam_hit, |
| 1546 | context0_hit, |
| 1547 | rd_tte_tag, |
| 1548 | ram_wwl, |
| 1549 | ram_rwl, |
| 1550 | valid) ; |
| 1551 | wire [6:0] rw_index_to_decode; |
| 1552 | wire [127:0] decoded_index; |
| 1553 | |
| 1554 | |
| 1555 | `define ENTRIES 128 |
| 1556 | `define INDEX 6 |
| 1557 | |
| 1558 | |
| 1559 | |
| 1560 | input l1clk; |
| 1561 | |
| 1562 | input tlb_bypass; |
| 1563 | input tlb_wr_flopped; |
| 1564 | input tlb_rd_flopped; |
| 1565 | input [`INDEX:0] rw_index; |
| 1566 | input tlb_cam; |
| 1567 | input tlb_cam_flopped; |
| 1568 | input demap; |
| 1569 | input demap_context; |
| 1570 | input demap_all; |
| 1571 | input demap_real; |
| 1572 | |
| 1573 | input [65:0] tte_tag; |
| 1574 | input [65:0] tte_tag_flopped; |
| 1575 | input [2:0] tte_page_size_mask; |
| 1576 | |
| 1577 | input tag_read_mux_control; |
| 1578 | |
| 1579 | |
| 1580 | |
| 1581 | output tlb_cam_hit; |
| 1582 | output context0_hit; |
| 1583 | output [65:0] rd_tte_tag; |
| 1584 | output [`ENTRIES-1:0] ram_wwl; |
| 1585 | output [`ENTRIES-1:0] ram_rwl; |
| 1586 | output [`ENTRIES-1:0] valid; |
| 1587 | |
| 1588 | |
| 1589 | |
| 1590 | `define CNTX1_HI 65 |
| 1591 | `define CNTX1_LO 53 |
| 1592 | `define PID_HI 52 |
| 1593 | `define PID_LO 50 |
| 1594 | `define REAL_BIT 49 |
| 1595 | `define VA_47 48 |
| 1596 | `define VA_28 29 |
| 1597 | `define VA_27 28 |
| 1598 | `define VA_22 23 |
| 1599 | `define TTE_VALID 22 |
| 1600 | `define VA_21 21 |
| 1601 | `define VA_16 16 |
| 1602 | `define VA_15 15 |
| 1603 | `define VA_13 13 |
| 1604 | `define CNTX0_HI 12 |
| 1605 | `define CNTX0_LO 0 |
| 1606 | |
| 1607 | |
| 1608 | |
| 1609 | //---------------------------------------------------------------------- |
| 1610 | // Declarations |
| 1611 | //---------------------------------------------------------------------- |
| 1612 | |
| 1613 | // local signals |
| 1614 | |
| 1615 | reg [12:0] context_a [`ENTRIES-1:0]; // Contexts a and b are |
| 1616 | reg [12:0] context_a_ [`ENTRIES-1:0]; // to be equal at all times |
| 1617 | reg [12:0] context_b [`ENTRIES-1:0]; // This is NOT context 0 and 1 |
| 1618 | reg [12:0] context_b_ [`ENTRIES-1:0]; // This is NOT primary/secondary |
| 1619 | reg r_bit [`ENTRIES-1:0]; |
| 1620 | reg r_bit_ [`ENTRIES-1:0]; |
| 1621 | reg [47:28] va_47_28 [`ENTRIES-1:0]; |
| 1622 | reg [47:28] va_47_28_ [`ENTRIES-1:0]; |
| 1623 | reg [27:22] va_27_22 [`ENTRIES-1:0]; |
| 1624 | reg [27:22] va_27_22_ [`ENTRIES-1:0]; |
| 1625 | reg [21:16] va_21_16 [`ENTRIES-1:0]; |
| 1626 | reg [21:16] va_21_16_ [`ENTRIES-1:0]; |
| 1627 | reg [15:13] va_15_13 [`ENTRIES-1:0]; |
| 1628 | reg [15:13] va_15_13_ [`ENTRIES-1:0]; |
| 1629 | reg [2:0] pid [`ENTRIES-1:0]; |
| 1630 | reg [2:0] pid_ [`ENTRIES-1:0]; |
| 1631 | reg [`ENTRIES-1:0] valid; |
| 1632 | reg [`ENTRIES-1:0] match_for_sat; |
| 1633 | reg tlb_cam_hit; |
| 1634 | reg context0_hit; |
| 1635 | |
| 1636 | integer n; |
| 1637 | reg [31:0] n_reg; |
| 1638 | |
| 1639 | reg [`ENTRIES-1:0] va_47_28_match ; |
| 1640 | reg [`ENTRIES-1:0] va_27_22_match ; |
| 1641 | reg [`ENTRIES-1:0] va_21_16_match ; |
| 1642 | reg [`ENTRIES-1:0] va_15_13_match ; |
| 1643 | reg [`ENTRIES-1:0] pid_match ; |
| 1644 | reg [`ENTRIES-1:0] real_match ; |
| 1645 | reg [`ENTRIES-1:0] context0_match ; |
| 1646 | reg [`ENTRIES-1:0] context1_match ; |
| 1647 | reg [`ENTRIES-1:0] context_match ; |
| 1648 | reg [`ENTRIES-1:0] match ; |
| 1649 | reg [`ENTRIES-1:0] ram_wl ; |
| 1650 | reg [65:0] rd_tte_tag; |
| 1651 | reg [12:0] a_xnor_tag; |
| 1652 | reg [12:0] b_xnor_tag; |
| 1653 | |
| 1654 | reg demap_posedge_l1clk; |
| 1655 | |
| 1656 | |
| 1657 | |
| 1658 | `ifndef NOINITMEM |
| 1659 | /////////////////////////////////////// |
| 1660 | // Initialize the arrays. // |
| 1661 | /////////////////////////////////////// |
| 1662 | initial begin |
| 1663 | for (n = 0; n < `ENTRIES; n = n+1) begin |
| 1664 | context_a [n] = {13 {1'b0}}; |
| 1665 | context_a_ [n] = {13 {1'b1}}; |
| 1666 | context_b [n] = {13 {1'b0}}; |
| 1667 | context_b_ [n] = {13 {1'b1}}; |
| 1668 | r_bit [n] = { 1 {1'b0}}; |
| 1669 | r_bit_ [n] = { 1 {1'b1}}; |
| 1670 | va_47_28 [n] = {20 {1'b0}}; |
| 1671 | va_47_28_ [n] = {20 {1'b1}}; |
| 1672 | va_27_22 [n] = { 6 {1'b0}}; |
| 1673 | va_27_22_ [n] = { 6 {1'b1}}; |
| 1674 | va_21_16 [n] = { 6 {1'b0}}; |
| 1675 | va_21_16_ [n] = { 6 {1'b1}}; |
| 1676 | va_15_13 [n] = { 3 {1'b0}}; |
| 1677 | va_15_13_ [n] = { 3 {1'b1}}; |
| 1678 | pid [n] = { 3 {1'b0}}; |
| 1679 | pid_ [n] = { 3 {1'b1}}; |
| 1680 | valid [n] = { 1 {1'b0}}; |
| 1681 | end // for (n = 0; n < `ENTRIES; n = n+1) |
| 1682 | end |
| 1683 | `endif |
| 1684 | |
| 1685 | |
| 1686 | |
| 1687 | /////////////////////////////////////////////////////////////// |
| 1688 | // CAM, read |
| 1689 | /////////////////////////////////////////////////////////////// |
| 1690 | always @(posedge l1clk) begin |
| 1691 | |
| 1692 | demap_posedge_l1clk = demap; |
| 1693 | |
| 1694 | match[`ENTRIES-1:0] = {`ENTRIES {1'b0}}; |
| 1695 | |
| 1696 | if (tlb_cam | demap) begin |
| 1697 | for (n = 0; n < `ENTRIES; n = n + 1) begin |
| 1698 | // Have to represent dual match line architecture... |
| 1699 | // LSB 2 bits of context must both match AND MSB 11 bits must not mismatch |
| 1700 | a_xnor_tag[12:0] = (context_a [n] & tte_tag[`CNTX1_HI:`CNTX1_LO]) | |
| 1701 | (context_a_ [n] & ~tte_tag[`CNTX1_HI:`CNTX1_LO]) ; |
| 1702 | b_xnor_tag[12:0] = (context_b [n] & tte_tag[`CNTX0_HI:`CNTX0_LO]) | |
| 1703 | (context_b_ [n] & ~tte_tag[`CNTX0_HI:`CNTX0_LO]) ; |
| 1704 | context1_match[n] = demap_all | demap_real | |
| 1705 | (& a_xnor_tag[1:0]) & |
| 1706 | (~(| {context_a [n] & ~tte_tag[`CNTX1_HI:`CNTX1_LO] & 13'h1ffc, |
| 1707 | context_a_ [n] & tte_tag[`CNTX1_HI:`CNTX1_LO] & 13'h1ffc})); |
| 1708 | context0_match[n] = demap_all | demap_real | |
| 1709 | (& b_xnor_tag[1:0]) & |
| 1710 | (~(| {context_b [n] & ~tte_tag[`CNTX0_HI:`CNTX0_LO] & 13'h1ffc, |
| 1711 | context_b_ [n] & tte_tag[`CNTX0_HI:`CNTX0_LO] & 13'h1ffc})); |
| 1712 | pid_match[n] = (~(| {pid [n] & ~tte_tag[`PID_HI :`PID_LO ], |
| 1713 | pid_ [n] & tte_tag[`PID_HI :`PID_LO ]})); |
| 1714 | real_match[n] = demap_all | |
| 1715 | (~(| {r_bit [n] & ~tte_tag[`REAL_BIT ], |
| 1716 | r_bit_ [n] & tte_tag[`REAL_BIT ]})); |
| 1717 | va_47_28_match[n] = demap_all | demap_real | demap_context | |
| 1718 | (~(| {va_47_28 [n] & ~tte_tag[`VA_47 :`VA_28 ], |
| 1719 | va_47_28_ [n] & tte_tag[`VA_47 :`VA_28 ]})); |
| 1720 | va_27_22_match[n] = demap_all | demap_real | demap_context | |
| 1721 | (~(| {va_27_22 [n] & ~tte_tag[`VA_27 :`VA_22 ], |
| 1722 | va_27_22_ [n] & tte_tag[`VA_27 :`VA_22 ]})); |
| 1723 | va_21_16_match[n] = demap_all | demap_real | demap_context | |
| 1724 | (~(| {va_21_16 [n] & ~tte_tag[`VA_21 :`VA_16 ], |
| 1725 | va_21_16_ [n] & tte_tag[`VA_21 :`VA_16 ]})); |
| 1726 | va_15_13_match[n] = demap_all | demap_real | demap_context | |
| 1727 | (~(| {va_15_13 [n] & ~tte_tag[`VA_15 :`VA_13 ], |
| 1728 | va_15_13_ [n] & tte_tag[`VA_15 :`VA_13 ]})); |
| 1729 | |
| 1730 | context_match[n] = context0_match[n] | context1_match[n]; |
| 1731 | |
| 1732 | match[n] = va_47_28_match[n] & va_27_22_match[n] & va_21_16_match[n] & |
| 1733 | va_15_13_match[n] & pid_match[n] & real_match[n] & context_match[n] & |
| 1734 | valid[n]; |
| 1735 | |
| 1736 | end // for (n = 0; n < `ENTRIES; n = n + 1) |
| 1737 | |
| 1738 | |
| 1739 | end // if (tlb_cam | demap) |
| 1740 | |
| 1741 | |
| 1742 | |
| 1743 | ram_wl[`ENTRIES-1:0] <= match[`ENTRIES-1:0]; |
| 1744 | |
| 1745 | end // always @ (posedge l1clk) |
| 1746 | |
| 1747 | |
| 1748 | |
| 1749 | /////////////////////////////////////////////////////////////// |
| 1750 | // Demap, Write, Read |
| 1751 | /////////////////////////////////////////////////////////////// |
| 1752 | always @(negedge l1clk) begin |
| 1753 | |
| 1754 | // Demap |
| 1755 | if (demap) begin |
| 1756 | for (n = 0; n < `ENTRIES; n = n + 1) begin |
| 1757 | if (match[n]) begin |
| 1758 | valid[n] <= 1'b0; |
| 1759 | end |
| 1760 | end |
| 1761 | end // if (demap) |
| 1762 | |
| 1763 | // Write |
| 1764 | if (tlb_wr_flopped) begin |
| 1765 | |
| 1766 | for (n = 0; n < `ENTRIES; n = n + 1) begin |
| 1767 | if (ram_wwl[n]) begin |
| 1768 | context_a [n] <=( tte_tag_flopped[`CNTX1_HI:`CNTX1_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}}; |
| 1769 | context_a_ [n] <=(~tte_tag_flopped[`CNTX1_HI:`CNTX1_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}}; |
| 1770 | pid [n] <= tte_tag_flopped[`PID_HI :`PID_LO ]; |
| 1771 | pid_ [n] <= ~tte_tag_flopped[`PID_HI :`PID_LO ]; |
| 1772 | r_bit [n] <= tte_tag_flopped[`REAL_BIT ]; |
| 1773 | r_bit_ [n] <= ~tte_tag_flopped[`REAL_BIT ]; |
| 1774 | va_47_28 [n] <= tte_tag_flopped[`VA_47 :`VA_28 ]; |
| 1775 | va_47_28_ [n] <= ~tte_tag_flopped[`VA_47 :`VA_28 ]; |
| 1776 | va_27_22 [n] <= tte_tag_flopped[`VA_27 :`VA_22 ] & { 6 {~tte_page_size_mask[2]}}; |
| 1777 | va_27_22_ [n] <= ~tte_tag_flopped[`VA_27 :`VA_22 ] & { 6 {~tte_page_size_mask[2]}}; |
| 1778 | va_21_16 [n] <= tte_tag_flopped[`VA_21 :`VA_16 ] & { 6 {~tte_page_size_mask[1]}}; |
| 1779 | va_21_16_ [n] <= ~tte_tag_flopped[`VA_21 :`VA_16 ] & { 6 {~tte_page_size_mask[1]}}; |
| 1780 | va_15_13 [n] <= tte_tag_flopped[`VA_15 :`VA_13 ] & { 3 {~tte_page_size_mask[0]}}; |
| 1781 | va_15_13_ [n] <= ~tte_tag_flopped[`VA_15 :`VA_13 ] & { 3 {~tte_page_size_mask[0]}}; |
| 1782 | context_b [n] <=( tte_tag_flopped[`CNTX0_HI:`CNTX0_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}}; |
| 1783 | context_b_ [n] <=(~tte_tag_flopped[`CNTX0_HI:`CNTX0_LO] & {13 {~tte_tag_flopped[`REAL_BIT]}}) | {11'h00, {2 {tte_tag_flopped[`REAL_BIT]}}}; |
| 1784 | valid [n] <= tte_tag_flopped[`TTE_VALID ]; |
| 1785 | |
| 1786 | |
| 1787 | |
| 1788 | |
| 1789 | end // if (ram_wwl[n]) |
| 1790 | end // for (n = 0; n < `ENTRIES; n = n + 1) |
| 1791 | |
| 1792 | end // if (tlb_wr_flopped) |
| 1793 | |
| 1794 | // Read |
| 1795 | if (tlb_rd_flopped) begin |
| 1796 | if (tag_read_mux_control) begin |
| 1797 | rd_tte_tag[`CNTX1_HI:`CNTX1_LO] <= context_a_ [rw_index[`INDEX:0]]; |
| 1798 | rd_tte_tag[`PID_HI :`PID_LO ] <= pid_ [rw_index[`INDEX:0]]; |
| 1799 | rd_tte_tag[`REAL_BIT ] <= r_bit_ [rw_index[`INDEX:0]]; |
| 1800 | rd_tte_tag[`VA_47 :`VA_28 ] <= va_47_28_ [rw_index[`INDEX:0]]; |
| 1801 | rd_tte_tag[`VA_27 :`VA_22 ] <= va_27_22_ [rw_index[`INDEX:0]]; |
| 1802 | rd_tte_tag[`VA_21 :`VA_16 ] <= va_21_16_ [rw_index[`INDEX:0]]; |
| 1803 | rd_tte_tag[`VA_15 :`VA_13 ] <= va_15_13_ [rw_index[`INDEX:0]]; |
| 1804 | rd_tte_tag[`CNTX0_HI:`CNTX0_LO] <= context_b_ [rw_index[`INDEX:0]]; |
| 1805 | end // if (tag_read_mux_control) |
| 1806 | else begin |
| 1807 | rd_tte_tag[`CNTX1_HI:`CNTX1_LO] <= context_a [rw_index[`INDEX:0]]; |
| 1808 | rd_tte_tag[`PID_HI :`PID_LO ] <= pid [rw_index[`INDEX:0]]; |
| 1809 | rd_tte_tag[`REAL_BIT ] <= r_bit [rw_index[`INDEX:0]]; |
| 1810 | rd_tte_tag[`VA_47 :`VA_28 ] <= va_47_28 [rw_index[`INDEX:0]]; |
| 1811 | rd_tte_tag[`VA_27 :`VA_22 ] <= va_27_22 [rw_index[`INDEX:0]]; |
| 1812 | rd_tte_tag[`VA_21 :`VA_16 ] <= va_21_16 [rw_index[`INDEX:0]]; |
| 1813 | rd_tte_tag[`VA_15 :`VA_13 ] <= va_15_13 [rw_index[`INDEX:0]]; |
| 1814 | rd_tte_tag[`CNTX0_HI:`CNTX0_LO] <= context_b [rw_index[`INDEX:0]]; |
| 1815 | end // else: !if(tag_read_mux_control) |
| 1816 | rd_tte_tag[`TTE_VALID ] <= valid [rw_index[`INDEX:0]]; |
| 1817 | end // if (tlb_rd |
| 1818 | else begin |
| 1819 | rd_tte_tag[65:0] <= {66 {1'b0}} ; |
| 1820 | end // else: !if(tlb_rd) |
| 1821 | |
| 1822 | end // always @ (negedge l1clk) |
| 1823 | |
| 1824 | |
| 1825 | |
| 1826 | /////////////////////////////////////////////////////////////// |
| 1827 | // Output assignments |
| 1828 | /////////////////////////////////////////////////////////////// |
| 1829 | // Have to hold them to next clock edge |
| 1830 | |
| 1831 | // Read and write address decode |
| 1832 | assign rw_index_to_decode[6:0] = |
| 1833 | // {1'b0, |
| 1834 | {rw_index[6], |
| 1835 | rw_index[5:0]}; |
| 1836 | |
| 1837 | assign decoded_index[127:0] = |
| 1838 | {(rw_index_to_decode[6:0] == 7'h7f), |
| 1839 | (rw_index_to_decode[6:0] == 7'h7e), |
| 1840 | (rw_index_to_decode[6:0] == 7'h7d), |
| 1841 | (rw_index_to_decode[6:0] == 7'h7c), |
| 1842 | (rw_index_to_decode[6:0] == 7'h7b), |
| 1843 | (rw_index_to_decode[6:0] == 7'h7a), |
| 1844 | (rw_index_to_decode[6:0] == 7'h79), |
| 1845 | (rw_index_to_decode[6:0] == 7'h78), |
| 1846 | (rw_index_to_decode[6:0] == 7'h77), |
| 1847 | (rw_index_to_decode[6:0] == 7'h76), |
| 1848 | (rw_index_to_decode[6:0] == 7'h75), |
| 1849 | (rw_index_to_decode[6:0] == 7'h74), |
| 1850 | (rw_index_to_decode[6:0] == 7'h73), |
| 1851 | (rw_index_to_decode[6:0] == 7'h72), |
| 1852 | (rw_index_to_decode[6:0] == 7'h71), |
| 1853 | (rw_index_to_decode[6:0] == 7'h70), |
| 1854 | (rw_index_to_decode[6:0] == 7'h6f), |
| 1855 | (rw_index_to_decode[6:0] == 7'h6e), |
| 1856 | (rw_index_to_decode[6:0] == 7'h6d), |
| 1857 | (rw_index_to_decode[6:0] == 7'h6c), |
| 1858 | (rw_index_to_decode[6:0] == 7'h6b), |
| 1859 | (rw_index_to_decode[6:0] == 7'h6a), |
| 1860 | (rw_index_to_decode[6:0] == 7'h69), |
| 1861 | (rw_index_to_decode[6:0] == 7'h68), |
| 1862 | (rw_index_to_decode[6:0] == 7'h67), |
| 1863 | (rw_index_to_decode[6:0] == 7'h66), |
| 1864 | (rw_index_to_decode[6:0] == 7'h65), |
| 1865 | (rw_index_to_decode[6:0] == 7'h64), |
| 1866 | (rw_index_to_decode[6:0] == 7'h63), |
| 1867 | (rw_index_to_decode[6:0] == 7'h62), |
| 1868 | (rw_index_to_decode[6:0] == 7'h61), |
| 1869 | (rw_index_to_decode[6:0] == 7'h60), |
| 1870 | (rw_index_to_decode[6:0] == 7'h5f), |
| 1871 | (rw_index_to_decode[6:0] == 7'h5e), |
| 1872 | (rw_index_to_decode[6:0] == 7'h5d), |
| 1873 | (rw_index_to_decode[6:0] == 7'h5c), |
| 1874 | (rw_index_to_decode[6:0] == 7'h5b), |
| 1875 | (rw_index_to_decode[6:0] == 7'h5a), |
| 1876 | (rw_index_to_decode[6:0] == 7'h59), |
| 1877 | (rw_index_to_decode[6:0] == 7'h58), |
| 1878 | (rw_index_to_decode[6:0] == 7'h57), |
| 1879 | (rw_index_to_decode[6:0] == 7'h56), |
| 1880 | (rw_index_to_decode[6:0] == 7'h55), |
| 1881 | (rw_index_to_decode[6:0] == 7'h54), |
| 1882 | (rw_index_to_decode[6:0] == 7'h53), |
| 1883 | (rw_index_to_decode[6:0] == 7'h52), |
| 1884 | (rw_index_to_decode[6:0] == 7'h51), |
| 1885 | (rw_index_to_decode[6:0] == 7'h50), |
| 1886 | (rw_index_to_decode[6:0] == 7'h4f), |
| 1887 | (rw_index_to_decode[6:0] == 7'h4e), |
| 1888 | (rw_index_to_decode[6:0] == 7'h4d), |
| 1889 | (rw_index_to_decode[6:0] == 7'h4c), |
| 1890 | (rw_index_to_decode[6:0] == 7'h4b), |
| 1891 | (rw_index_to_decode[6:0] == 7'h4a), |
| 1892 | (rw_index_to_decode[6:0] == 7'h49), |
| 1893 | (rw_index_to_decode[6:0] == 7'h48), |
| 1894 | (rw_index_to_decode[6:0] == 7'h47), |
| 1895 | (rw_index_to_decode[6:0] == 7'h46), |
| 1896 | (rw_index_to_decode[6:0] == 7'h45), |
| 1897 | (rw_index_to_decode[6:0] == 7'h44), |
| 1898 | (rw_index_to_decode[6:0] == 7'h43), |
| 1899 | (rw_index_to_decode[6:0] == 7'h42), |
| 1900 | (rw_index_to_decode[6:0] == 7'h41), |
| 1901 | (rw_index_to_decode[6:0] == 7'h40), |
| 1902 | (rw_index_to_decode[6:0] == 7'h3f), |
| 1903 | (rw_index_to_decode[6:0] == 7'h3e), |
| 1904 | (rw_index_to_decode[6:0] == 7'h3d), |
| 1905 | (rw_index_to_decode[6:0] == 7'h3c), |
| 1906 | (rw_index_to_decode[6:0] == 7'h3b), |
| 1907 | (rw_index_to_decode[6:0] == 7'h3a), |
| 1908 | (rw_index_to_decode[6:0] == 7'h39), |
| 1909 | (rw_index_to_decode[6:0] == 7'h38), |
| 1910 | (rw_index_to_decode[6:0] == 7'h37), |
| 1911 | (rw_index_to_decode[6:0] == 7'h36), |
| 1912 | (rw_index_to_decode[6:0] == 7'h35), |
| 1913 | (rw_index_to_decode[6:0] == 7'h34), |
| 1914 | (rw_index_to_decode[6:0] == 7'h33), |
| 1915 | (rw_index_to_decode[6:0] == 7'h32), |
| 1916 | (rw_index_to_decode[6:0] == 7'h31), |
| 1917 | (rw_index_to_decode[6:0] == 7'h30), |
| 1918 | (rw_index_to_decode[6:0] == 7'h2f), |
| 1919 | (rw_index_to_decode[6:0] == 7'h2e), |
| 1920 | (rw_index_to_decode[6:0] == 7'h2d), |
| 1921 | (rw_index_to_decode[6:0] == 7'h2c), |
| 1922 | (rw_index_to_decode[6:0] == 7'h2b), |
| 1923 | (rw_index_to_decode[6:0] == 7'h2a), |
| 1924 | (rw_index_to_decode[6:0] == 7'h29), |
| 1925 | (rw_index_to_decode[6:0] == 7'h28), |
| 1926 | (rw_index_to_decode[6:0] == 7'h27), |
| 1927 | (rw_index_to_decode[6:0] == 7'h26), |
| 1928 | (rw_index_to_decode[6:0] == 7'h25), |
| 1929 | (rw_index_to_decode[6:0] == 7'h24), |
| 1930 | (rw_index_to_decode[6:0] == 7'h23), |
| 1931 | (rw_index_to_decode[6:0] == 7'h22), |
| 1932 | (rw_index_to_decode[6:0] == 7'h21), |
| 1933 | (rw_index_to_decode[6:0] == 7'h20), |
| 1934 | (rw_index_to_decode[6:0] == 7'h1f), |
| 1935 | (rw_index_to_decode[6:0] == 7'h1e), |
| 1936 | (rw_index_to_decode[6:0] == 7'h1d), |
| 1937 | (rw_index_to_decode[6:0] == 7'h1c), |
| 1938 | (rw_index_to_decode[6:0] == 7'h1b), |
| 1939 | (rw_index_to_decode[6:0] == 7'h1a), |
| 1940 | (rw_index_to_decode[6:0] == 7'h19), |
| 1941 | (rw_index_to_decode[6:0] == 7'h18), |
| 1942 | (rw_index_to_decode[6:0] == 7'h17), |
| 1943 | (rw_index_to_decode[6:0] == 7'h16), |
| 1944 | (rw_index_to_decode[6:0] == 7'h15), |
| 1945 | (rw_index_to_decode[6:0] == 7'h14), |
| 1946 | (rw_index_to_decode[6:0] == 7'h13), |
| 1947 | (rw_index_to_decode[6:0] == 7'h12), |
| 1948 | (rw_index_to_decode[6:0] == 7'h11), |
| 1949 | (rw_index_to_decode[6:0] == 7'h10), |
| 1950 | (rw_index_to_decode[6:0] == 7'h0f), |
| 1951 | (rw_index_to_decode[6:0] == 7'h0e), |
| 1952 | (rw_index_to_decode[6:0] == 7'h0d), |
| 1953 | (rw_index_to_decode[6:0] == 7'h0c), |
| 1954 | (rw_index_to_decode[6:0] == 7'h0b), |
| 1955 | (rw_index_to_decode[6:0] == 7'h0a), |
| 1956 | (rw_index_to_decode[6:0] == 7'h09), |
| 1957 | (rw_index_to_decode[6:0] == 7'h08), |
| 1958 | (rw_index_to_decode[6:0] == 7'h07), |
| 1959 | (rw_index_to_decode[6:0] == 7'h06), |
| 1960 | (rw_index_to_decode[6:0] == 7'h05), |
| 1961 | (rw_index_to_decode[6:0] == 7'h04), |
| 1962 | (rw_index_to_decode[6:0] == 7'h03), |
| 1963 | (rw_index_to_decode[6:0] == 7'h02), |
| 1964 | (rw_index_to_decode[6:0] == 7'h01), |
| 1965 | (rw_index_to_decode[6:0] == 7'h00)}; |
| 1966 | |
| 1967 | //assign decoded_index_unused[127:64] = decoded_index[127:64]; |
| 1968 | |
| 1969 | always @(negedge l1clk) begin |
| 1970 | match_for_sat[`ENTRIES-1:0] <= match[`ENTRIES-1:0]; // For MMU SAT |
| 1971 | tlb_cam_hit <= (| match[`ENTRIES-1:0]) | tlb_bypass | ~tlb_cam; |
| 1972 | context0_hit <= (|(match[`ENTRIES-1:0] & context0_match[`ENTRIES-1:0])) & ~demap_posedge_l1clk; |
| 1973 | end // always @ (negedge l1clk) |
| 1974 | |
| 1975 | assign ram_wwl[`ENTRIES-1:0] = |
| 1976 | decoded_index[`ENTRIES-1:0] & {`ENTRIES {tlb_wr_flopped}}; |
| 1977 | |
| 1978 | assign ram_rwl[`ENTRIES-1:0] = |
| 1979 | (decoded_index[`ENTRIES-1:0] & {`ENTRIES {tlb_rd_flopped }}) | |
| 1980 | (ram_wl [`ENTRIES-1:0] & {`ENTRIES {tlb_cam_flopped}}); |
| 1981 | |
| 1982 | |
| 1983 | |
| 1984 | |
| 1985 | |
| 1986 | supply0 vss; // <- port for ground |
| 1987 | supply1 vdd; // <- port for power |
| 1988 | endmodule |
| 1989 | `endif // `ifndef FPGA |
| 1990 | |
| 1991 | `ifdef FPGA |
| 1992 | module n2_tlb_tl_128x59_cam(l1clk, tlb_bypass, tlb_wr_flopped, tlb_rd_flopped, |
| 1993 | rw_index, tlb_cam, tlb_cam_flopped, demap, demap_context, demap_all, |
| 1994 | demap_real, tte_tag, tte_tag_flopped, tte_page_size_mask, |
| 1995 | tag_read_mux_control, tlb_cam_hit, context0_hit, rd_tte_tag, ram_wwl, |
| 1996 | ram_rwl, valid); |
| 1997 | |
| 1998 | input l1clk; |
| 1999 | input tlb_bypass; |
| 2000 | input tlb_wr_flopped; |
| 2001 | input tlb_rd_flopped; |
| 2002 | input [6:0] rw_index; |
| 2003 | input tlb_cam; |
| 2004 | input tlb_cam_flopped; |
| 2005 | input demap; |
| 2006 | input demap_context; |
| 2007 | input demap_all; |
| 2008 | input demap_real; |
| 2009 | input [65:0] tte_tag; |
| 2010 | input [65:0] tte_tag_flopped; |
| 2011 | input [2:0] tte_page_size_mask; |
| 2012 | input tag_read_mux_control; |
| 2013 | output tlb_cam_hit; |
| 2014 | output context0_hit; |
| 2015 | output [65:0] rd_tte_tag; |
| 2016 | output [(128 - 1):0] ram_wwl; |
| 2017 | output [(128 - 1):0] ram_rwl; |
| 2018 | output [(128 - 1):0] valid; |
| 2019 | |
| 2020 | wire [6:0] rw_index_to_decode; |
| 2021 | wire [127:0] decoded_index; |
| 2022 | |
| 2023 | reg [12:0] context_a[(128 - 1):0]; |
| 2024 | reg [12:0] context_a_[(128 - 1):0]; |
| 2025 | reg [12:0] context_b[(128 - 1):0]; |
| 2026 | reg [12:0] context_b_[(128 - 1):0]; |
| 2027 | reg r_bit[(128 - 1):0]; |
| 2028 | reg r_bit_[(128 - 1):0]; |
| 2029 | reg [47:28] va_47_28[(128 - 1):0]; |
| 2030 | reg [47:28] va_47_28_[(128 - 1):0]; |
| 2031 | reg [27:22] va_27_22[(128 - 1):0]; |
| 2032 | reg [27:22] va_27_22_[(128 - 1):0]; |
| 2033 | reg [21:16] va_21_16[(128 - 1):0]; |
| 2034 | reg [21:16] va_21_16_[(128 - 1):0]; |
| 2035 | reg [15:13] va_15_13[(128 - 1):0]; |
| 2036 | reg [15:13] va_15_13_[(128 - 1):0]; |
| 2037 | reg [2:0] pid[(128 - 1):0]; |
| 2038 | reg [2:0] pid_[(128 - 1):0]; |
| 2039 | reg [(128 - 1):0] match_for_sat; |
| 2040 | reg tlb_cam_hit; |
| 2041 | reg context0_hit; |
| 2042 | integer n; |
| 2043 | reg [31:0] n_reg; |
| 2044 | reg [(128 - 1):0] va_47_28_match; |
| 2045 | reg [(128 - 1):0] va_27_22_match; |
| 2046 | reg [(128 - 1):0] va_21_16_match; |
| 2047 | reg [(128 - 1):0] va_15_13_match; |
| 2048 | reg [(128 - 1):0] pid_match; |
| 2049 | reg [(128 - 1):0] real_match; |
| 2050 | reg [(128 - 1):0] context0_match; |
| 2051 | reg [(128 - 1):0] context1_match; |
| 2052 | reg [(128 - 1):0] context_match; |
| 2053 | reg [(128 - 1):0] match; |
| 2054 | reg [(128 - 1):0] ram_wl; |
| 2055 | reg [65:0] rd_tte_tag; |
| 2056 | reg [(128 - 1):0] valid; |
| 2057 | reg [12:0] a_xnor_tag; |
| 2058 | reg [12:0] b_xnor_tag; |
| 2059 | reg demap_posedge_l1clk; |
| 2060 | supply0 vss; |
| 2061 | supply1 vdd; |
| 2062 | |
| 2063 | assign rw_index_to_decode[6:0] = {rw_index[6], rw_index[5:0]}; |
| 2064 | assign decoded_index[127:0] = {(rw_index_to_decode[6:0] == 7'b1111111), |
| 2065 | (rw_index_to_decode[6:0] == 7'h7e), (rw_index_to_decode[6:0] == |
| 2066 | 7'h7d), (rw_index_to_decode[6:0] == 7'h7c), |
| 2067 | (rw_index_to_decode[6:0] == 7'h7b), (rw_index_to_decode[6:0] == |
| 2068 | 7'h7a), (rw_index_to_decode[6:0] == 7'h79), |
| 2069 | (rw_index_to_decode[6:0] == 7'h78), (rw_index_to_decode[6:0] == |
| 2070 | 7'h77), (rw_index_to_decode[6:0] == 7'h76), |
| 2071 | (rw_index_to_decode[6:0] == 7'h75), (rw_index_to_decode[6:0] == |
| 2072 | 7'h74), (rw_index_to_decode[6:0] == 7'h73), |
| 2073 | (rw_index_to_decode[6:0] == 7'h72), (rw_index_to_decode[6:0] == |
| 2074 | 7'h71), (rw_index_to_decode[6:0] == 7'h70), |
| 2075 | (rw_index_to_decode[6:0] == 7'h6f), (rw_index_to_decode[6:0] == |
| 2076 | 7'h6e), (rw_index_to_decode[6:0] == 7'h6d), |
| 2077 | (rw_index_to_decode[6:0] == 7'h6c), (rw_index_to_decode[6:0] == |
| 2078 | 7'h6b), (rw_index_to_decode[6:0] == 7'h6a), |
| 2079 | (rw_index_to_decode[6:0] == 7'h69), (rw_index_to_decode[6:0] == |
| 2080 | 7'h68), (rw_index_to_decode[6:0] == 7'h67), |
| 2081 | (rw_index_to_decode[6:0] == 7'h66), (rw_index_to_decode[6:0] == |
| 2082 | 7'h65), (rw_index_to_decode[6:0] == 7'h64), |
| 2083 | (rw_index_to_decode[6:0] == 7'h63), (rw_index_to_decode[6:0] == |
| 2084 | 7'h62), (rw_index_to_decode[6:0] == 7'h61), |
| 2085 | (rw_index_to_decode[6:0] == 7'h60), (rw_index_to_decode[6:0] == |
| 2086 | 7'h5f), (rw_index_to_decode[6:0] == 7'h5e), |
| 2087 | (rw_index_to_decode[6:0] == 7'h5d), (rw_index_to_decode[6:0] == |
| 2088 | 7'h5c), (rw_index_to_decode[6:0] == 7'h5b), |
| 2089 | (rw_index_to_decode[6:0] == 7'h5a), (rw_index_to_decode[6:0] == |
| 2090 | 7'h59), (rw_index_to_decode[6:0] == 7'h58), |
| 2091 | (rw_index_to_decode[6:0] == 7'h57), (rw_index_to_decode[6:0] == |
| 2092 | 7'h56), (rw_index_to_decode[6:0] == 7'h55), |
| 2093 | (rw_index_to_decode[6:0] == 7'h54), (rw_index_to_decode[6:0] == |
| 2094 | 7'h53), (rw_index_to_decode[6:0] == 7'h52), |
| 2095 | (rw_index_to_decode[6:0] == 7'h51), (rw_index_to_decode[6:0] == |
| 2096 | 7'h50), (rw_index_to_decode[6:0] == 7'h4f), |
| 2097 | (rw_index_to_decode[6:0] == 7'h4e), (rw_index_to_decode[6:0] == |
| 2098 | 7'h4d), (rw_index_to_decode[6:0] == 7'h4c), |
| 2099 | (rw_index_to_decode[6:0] == 7'h4b), (rw_index_to_decode[6:0] == |
| 2100 | 7'h4a), (rw_index_to_decode[6:0] == 7'h49), |
| 2101 | (rw_index_to_decode[6:0] == 7'h48), (rw_index_to_decode[6:0] == |
| 2102 | 7'h47), (rw_index_to_decode[6:0] == 7'h46), |
| 2103 | (rw_index_to_decode[6:0] == 7'h45), (rw_index_to_decode[6:0] == |
| 2104 | 7'h44), (rw_index_to_decode[6:0] == 7'h43), |
| 2105 | (rw_index_to_decode[6:0] == 7'h42), (rw_index_to_decode[6:0] == |
| 2106 | 7'h41), (rw_index_to_decode[6:0] == 7'h40), |
| 2107 | (rw_index_to_decode[6:0] == 7'b0111111), |
| 2108 | (rw_index_to_decode[6:0] == 7'h3e), (rw_index_to_decode[6:0] == |
| 2109 | 7'h3d), (rw_index_to_decode[6:0] == 7'h3c), |
| 2110 | (rw_index_to_decode[6:0] == 7'h3b), (rw_index_to_decode[6:0] == |
| 2111 | 7'h3a), (rw_index_to_decode[6:0] == 7'h39), |
| 2112 | (rw_index_to_decode[6:0] == 7'h38), (rw_index_to_decode[6:0] == |
| 2113 | 7'h37), (rw_index_to_decode[6:0] == 7'h36), |
| 2114 | (rw_index_to_decode[6:0] == 7'h35), (rw_index_to_decode[6:0] == |
| 2115 | 7'h34), (rw_index_to_decode[6:0] == 7'h33), |
| 2116 | (rw_index_to_decode[6:0] == 7'h32), (rw_index_to_decode[6:0] == |
| 2117 | 7'h31), (rw_index_to_decode[6:0] == 7'h30), |
| 2118 | (rw_index_to_decode[6:0] == 7'h2f), (rw_index_to_decode[6:0] == |
| 2119 | 7'h2e), (rw_index_to_decode[6:0] == 7'h2d), |
| 2120 | (rw_index_to_decode[6:0] == 7'h2c), (rw_index_to_decode[6:0] == |
| 2121 | 7'h2b), (rw_index_to_decode[6:0] == 7'h2a), |
| 2122 | (rw_index_to_decode[6:0] == 7'h29), (rw_index_to_decode[6:0] == |
| 2123 | 7'h28), (rw_index_to_decode[6:0] == 7'h27), |
| 2124 | (rw_index_to_decode[6:0] == 7'h26), (rw_index_to_decode[6:0] == |
| 2125 | 7'h25), (rw_index_to_decode[6:0] == 7'h24), |
| 2126 | (rw_index_to_decode[6:0] == 7'h23), (rw_index_to_decode[6:0] == |
| 2127 | 7'h22), (rw_index_to_decode[6:0] == 7'h21), |
| 2128 | (rw_index_to_decode[6:0] == 7'h20), (rw_index_to_decode[6:0] == |
| 2129 | 7'h1f), (rw_index_to_decode[6:0] == 7'h1e), |
| 2130 | (rw_index_to_decode[6:0] == 7'h1d), (rw_index_to_decode[6:0] == |
| 2131 | 7'h1c), (rw_index_to_decode[6:0] == 7'h1b), |
| 2132 | (rw_index_to_decode[6:0] == 7'h1a), (rw_index_to_decode[6:0] == |
| 2133 | 7'h19), (rw_index_to_decode[6:0] == 7'h18), |
| 2134 | (rw_index_to_decode[6:0] == 7'h17), (rw_index_to_decode[6:0] == |
| 2135 | 7'h16), (rw_index_to_decode[6:0] == 7'h15), |
| 2136 | (rw_index_to_decode[6:0] == 7'h14), (rw_index_to_decode[6:0] == |
| 2137 | 7'h13), (rw_index_to_decode[6:0] == 7'h12), |
| 2138 | (rw_index_to_decode[6:0] == 7'h11), (rw_index_to_decode[6:0] == |
| 2139 | 7'h10), (rw_index_to_decode[6:0] == 7'h0f), |
| 2140 | (rw_index_to_decode[6:0] == 7'h0e), (rw_index_to_decode[6:0] == |
| 2141 | 7'h0d), (rw_index_to_decode[6:0] == 7'h0c), |
| 2142 | (rw_index_to_decode[6:0] == 7'h0b), (rw_index_to_decode[6:0] == |
| 2143 | 7'h0a), (rw_index_to_decode[6:0] == 7'h09), |
| 2144 | (rw_index_to_decode[6:0] == 7'h08), (rw_index_to_decode[6:0] == |
| 2145 | 7'h07), (rw_index_to_decode[6:0] == 7'h06), |
| 2146 | (rw_index_to_decode[6:0] == 7'h05), (rw_index_to_decode[6:0] == |
| 2147 | 7'h04), (rw_index_to_decode[6:0] == 7'h03), |
| 2148 | (rw_index_to_decode[6:0] == 7'b0000010), |
| 2149 | (rw_index_to_decode[6:0] == 7'b1), (rw_index_to_decode[6:0] == |
| 2150 | 7'b0)}; |
| 2151 | assign ram_wwl[(128 - 1):0] = (decoded_index[(128 - 1):0] & {128 { |
| 2152 | tlb_wr_flopped}}); |
| 2153 | assign ram_rwl[(128 - 1):0] = ((decoded_index[(128 - 1):0] & {128 { |
| 2154 | tlb_rd_flopped}}) | (ram_wl[(128 - 1):0] & {128 {tlb_cam_flopped |
| 2155 | }})); |
| 2156 | |
| 2157 | initial begin |
| 2158 | for (n = 0; (n < 128); n = (n + 1)) begin |
| 2159 | context_a[n] = {13 {1'b0}}; |
| 2160 | context_a_[n] = {13 {1'b1}}; |
| 2161 | context_b[n] = {13 {1'b0}}; |
| 2162 | context_b_[n] = {13 {1'b1}}; |
| 2163 | r_bit[n] = {1 {1'b0}}; |
| 2164 | r_bit_[n] = {1 {1'b1}}; |
| 2165 | va_47_28[n] = {20 {1'b0}}; |
| 2166 | va_47_28_[n] = {20 {1'b1}}; |
| 2167 | va_27_22[n] = {6 {1'b0}}; |
| 2168 | va_27_22_[n] = {6 {1'b1}}; |
| 2169 | va_21_16[n] = {6 {1'b0}}; |
| 2170 | va_21_16_[n] = {6 {1'b1}}; |
| 2171 | va_15_13[n] = {3 {1'b0}}; |
| 2172 | va_15_13_[n] = {3 {1'b1}}; |
| 2173 | pid[n] = {3 {1'b0}}; |
| 2174 | pid_[n] = {3 {1'b1}}; |
| 2175 | valid[n] = {1 {1'b0}}; |
| 2176 | end |
| 2177 | end |
| 2178 | always @(posedge l1clk) begin |
| 2179 | demap_posedge_l1clk = demap; |
| 2180 | match[(128 - 1):0] = {128 {1'b0}}; |
| 2181 | if (tlb_cam | demap) begin |
| 2182 | for (n = 0; (n < 128); n = (n + 1)) begin |
| 2183 | a_xnor_tag[12:0] = ((context_a[n] & tte_tag[65:53]) | ( |
| 2184 | context_a_[n] & (~tte_tag[65:53]))); |
| 2185 | b_xnor_tag[12:0] = ((context_b[n] & tte_tag[12:0]) | ( |
| 2186 | context_b_[n] & (~tte_tag[12:0]))); |
| 2187 | context1_match[n] = ((demap_all | demap_real) | ((&a_xnor_tag[1:0] |
| 2188 | ) & (~(|{((context_a[n] & (~tte_tag[65:53])) & 13'h1ffc), |
| 2189 | ((context_a_[n] & tte_tag[65:53]) & 13'h1ffc)})))); |
| 2190 | context0_match[n] = ((demap_all | demap_real) | ((&b_xnor_tag[1:0] |
| 2191 | ) & (~(|{((context_b[n] & (~tte_tag[12:0])) & 13'h1ffc), |
| 2192 | ((context_b_[n] & tte_tag[12:0]) & 13'h1ffc)})))); |
| 2193 | pid_match[n] = (~(|{(pid[n] & (~tte_tag[52:50])), (pid_[n] & |
| 2194 | tte_tag[52:50])})); |
| 2195 | real_match[n] = (demap_all | (~(|{(r_bit[n] & (~tte_tag[49])), |
| 2196 | (r_bit_[n] & tte_tag[49])}))); |
| 2197 | va_47_28_match[n] = (((demap_all | demap_real) | demap_context) | |
| 2198 | (~(|{(va_47_28[n] & (~tte_tag[48:29])), (va_47_28_[n] & |
| 2199 | tte_tag[48:29])}))); |
| 2200 | va_27_22_match[n] = (((demap_all | demap_real) | demap_context) | |
| 2201 | (~(|{(va_27_22[n] & (~tte_tag[28:23])), (va_27_22_[n] & |
| 2202 | tte_tag[28:23])}))); |
| 2203 | va_21_16_match[n] = (((demap_all | demap_real) | demap_context) | |
| 2204 | (~(|{(va_21_16[n] & (~tte_tag[21:16])), (va_21_16_[n] & |
| 2205 | tte_tag[21:16])}))); |
| 2206 | va_15_13_match[n] = (((demap_all | demap_real) | demap_context) | |
| 2207 | (~(|{(va_15_13[n] & (~tte_tag[15:13])), (va_15_13_[n] & |
| 2208 | tte_tag[15:13])}))); |
| 2209 | context_match[n] = (context0_match[n] | context1_match[n]); |
| 2210 | match[n] = (((((((va_47_28_match[n] & va_27_22_match[n]) & |
| 2211 | va_21_16_match[n]) & va_15_13_match[n]) & pid_match[n]) & |
| 2212 | real_match[n]) & context_match[n]) & valid[n]); |
| 2213 | end |
| 2214 | end |
| 2215 | ram_wl[(128 - 1):0] <= match[(128 - 1):0]; |
| 2216 | end |
| 2217 | always @(negedge l1clk) begin |
| 2218 | if (demap) begin |
| 2219 | for (n = 0; (n < 128); n = (n + 1)) begin |
| 2220 | if (match[n]) begin |
| 2221 | valid[n] <= 1'b0; |
| 2222 | end |
| 2223 | end |
| 2224 | end |
| 2225 | if (tlb_wr_flopped) begin |
| 2226 | for (n = 0; (n < 128); n = (n + 1)) begin |
| 2227 | if (ram_wwl[n]) begin |
| 2228 | context_a[n] <= ((tte_tag_flopped[65:53] & {13 { |
| 2229 | (~tte_tag_flopped[49])}}) | {11'b0, {2 |
| 2230 | {tte_tag_flopped[49]}}}); |
| 2231 | context_a_[n] <= (((~tte_tag_flopped[65:53]) & {13 { |
| 2232 | (~tte_tag_flopped[49])}}) | {11'b0, {2 |
| 2233 | {tte_tag_flopped[49]}}}); |
| 2234 | pid[n] <= tte_tag_flopped[52:50]; |
| 2235 | pid_[n] <= (~tte_tag_flopped[52:50]); |
| 2236 | r_bit[n] <= tte_tag_flopped[49]; |
| 2237 | r_bit_[n] <= (~tte_tag_flopped[49]); |
| 2238 | va_47_28[n] <= tte_tag_flopped[48:29]; |
| 2239 | va_47_28_[n] <= (~tte_tag_flopped[48:29]); |
| 2240 | va_27_22[n] <= (tte_tag_flopped[28:23] & {6 { |
| 2241 | (~tte_page_size_mask[2])}}); |
| 2242 | va_27_22_[n] <= ((~tte_tag_flopped[28:23]) & {6 { |
| 2243 | (~tte_page_size_mask[2])}}); |
| 2244 | va_21_16[n] <= (tte_tag_flopped[21:16] & {6 { |
| 2245 | (~tte_page_size_mask[1])}}); |
| 2246 | va_21_16_[n] <= ((~tte_tag_flopped[21:16]) & {6 { |
| 2247 | (~tte_page_size_mask[1])}}); |
| 2248 | va_15_13[n] <= (tte_tag_flopped[15:13] & {3 { |
| 2249 | (~tte_page_size_mask[0])}}); |
| 2250 | va_15_13_[n] <= ((~tte_tag_flopped[15:13]) & {3 { |
| 2251 | (~tte_page_size_mask[0])}}); |
| 2252 | context_b[n] <= ((tte_tag_flopped[12:0] & {13 { |
| 2253 | (~tte_tag_flopped[49])}}) | {11'b0, {2 |
| 2254 | {tte_tag_flopped[49]}}}); |
| 2255 | context_b_[n] <= (((~tte_tag_flopped[12:0]) & {13 { |
| 2256 | (~tte_tag_flopped[49])}}) | {11'b0, {2 |
| 2257 | {tte_tag_flopped[49]}}}); |
| 2258 | valid[n] <= tte_tag_flopped[22]; |
| 2259 | end |
| 2260 | end |
| 2261 | end |
| 2262 | if (tlb_rd_flopped) begin |
| 2263 | if (tag_read_mux_control) begin |
| 2264 | rd_tte_tag[65:53] <= context_a_[rw_index[6:0]]; |
| 2265 | rd_tte_tag[52:50] <= pid_[rw_index[6:0]]; |
| 2266 | rd_tte_tag[49] <= r_bit_[rw_index[6:0]]; |
| 2267 | rd_tte_tag[48:29] <= va_47_28_[rw_index[6:0]]; |
| 2268 | rd_tte_tag[28:23] <= va_27_22_[rw_index[6:0]]; |
| 2269 | rd_tte_tag[21:16] <= va_21_16_[rw_index[6:0]]; |
| 2270 | rd_tte_tag[15:13] <= va_15_13_[rw_index[6:0]]; |
| 2271 | rd_tte_tag[12:0] <= context_b_[rw_index[6:0]]; |
| 2272 | end |
| 2273 | else |
| 2274 | begin |
| 2275 | rd_tte_tag[65:53] <= context_a[rw_index[6:0]]; |
| 2276 | rd_tte_tag[52:50] <= pid[rw_index[6:0]]; |
| 2277 | rd_tte_tag[49] <= r_bit[rw_index[6:0]]; |
| 2278 | rd_tte_tag[48:29] <= va_47_28[rw_index[6:0]]; |
| 2279 | rd_tte_tag[28:23] <= va_27_22[rw_index[6:0]]; |
| 2280 | rd_tte_tag[21:16] <= va_21_16[rw_index[6:0]]; |
| 2281 | rd_tte_tag[15:13] <= va_15_13[rw_index[6:0]]; |
| 2282 | rd_tte_tag[12:0] <= context_b[rw_index[6:0]]; |
| 2283 | end |
| 2284 | rd_tte_tag[22] <= valid[rw_index[6:0]]; |
| 2285 | end |
| 2286 | else |
| 2287 | begin |
| 2288 | rd_tte_tag[65:0] <= {66 {1'b0}}; |
| 2289 | end |
| 2290 | end |
| 2291 | always @(negedge l1clk) begin |
| 2292 | match_for_sat[(128 - 1):0] <= match[(128 - 1):0]; |
| 2293 | tlb_cam_hit <= (((|match[(128 - 1):0]) | tlb_bypass) | (~tlb_cam)); |
| 2294 | context0_hit <= ((|(match[(128 - 1):0] & context0_match[(128 - 1):0])) |
| 2295 | & (~demap_posedge_l1clk)); |
| 2296 | end |
| 2297 | endmodule |
| 2298 | |
| 2299 | `endif |
| 2300 | |
| 2301 | |
| 2302 | `ifndef FPGA |
| 2303 | module n2_tlb_tl_128x59_ram ( |
| 2304 | l1clk, |
| 2305 | tlb_bypass, |
| 2306 | tlb_cam_flopped, |
| 2307 | ram_wwl, |
| 2308 | ram_rwl, |
| 2309 | tte_data, |
| 2310 | va, |
| 2311 | force_data_to_x, |
| 2312 | pa, |
| 2313 | rd_tte_data) ; |
| 2314 | wire [6:0] encoded_rwl; |
| 2315 | wire any_wwl; |
| 2316 | wire any_rwl; |
| 2317 | wire [39:13] tte_pa; |
| 2318 | |
| 2319 | |
| 2320 | `define ENTRIES 128 |
| 2321 | `define INDEX 6 |
| 2322 | |
| 2323 | |
| 2324 | |
| 2325 | input l1clk; |
| 2326 | |
| 2327 | input tlb_bypass; |
| 2328 | input tlb_cam_flopped; |
| 2329 | input [`ENTRIES-1:0] ram_wwl; |
| 2330 | input [`ENTRIES-1:0] ram_rwl; |
| 2331 | |
| 2332 | input [37:0] tte_data; |
| 2333 | input [39:11] va; // Incoming VA |
| 2334 | input force_data_to_x; |
| 2335 | |
| 2336 | |
| 2337 | |
| 2338 | output [39:11] pa; |
| 2339 | output [37:0] rd_tte_data; |
| 2340 | |
| 2341 | |
| 2342 | |
| 2343 | `define DATA_PARITY 36 |
| 2344 | `define DATA_PA_39_28_HI 35 |
| 2345 | `define DATA_PA_39_28_LO 24 |
| 2346 | `define DATA_PA_27_22_HI 23 |
| 2347 | `define DATA_PA_27_22_LO 18 |
| 2348 | `define DATA_VA_27_22_V 17 |
| 2349 | `define DATA_PA_21_16_HI 16 |
| 2350 | `define DATA_PA_21_16_LO 11 |
| 2351 | `define DATA_VA_21_16_V 10 |
| 2352 | `define DATA_PA_15_13_HI 9 |
| 2353 | `define DATA_PA_15_13_LO 7 |
| 2354 | `define DATA_VA_15_13_V 6 |
| 2355 | `define DATA_NFO 5 |
| 2356 | `define DATA_IE 4 |
| 2357 | `define DATA_CP 3 |
| 2358 | `define DATA_X 2 |
| 2359 | `define DATA_P 1 |
| 2360 | `define DATA_W 0 |
| 2361 | |
| 2362 | // Converted to structural to eliminate races |
| 2363 | assign encoded_rwl[`INDEX:0] = |
| 2364 | {| {ram_rwl[127:64] }, |
| 2365 | | {ram_rwl[127:96] , ram_rwl[63:32]}, |
| 2366 | | {ram_rwl[127:112], ram_rwl[95:80], ram_rwl[63:48], ram_rwl[31:16]}, |
| 2367 | | {ram_rwl[127:120], ram_rwl[111:104], |
| 2368 | ram_rwl[95:88], ram_rwl[79:72], ram_rwl[63:56], ram_rwl[47:40], |
| 2369 | ram_rwl[31:24], ram_rwl[15:8]}, |
| 2370 | | {ram_rwl[127:124], ram_rwl[119:116], ram_rwl[111:108], ram_rwl[103:100], |
| 2371 | ram_rwl[95:92], ram_rwl[87:84], ram_rwl[79:76], ram_rwl[71:68], |
| 2372 | ram_rwl[63:60], ram_rwl[55:52], ram_rwl[47:44], ram_rwl[39:36], |
| 2373 | ram_rwl[31:28], ram_rwl[23:20], ram_rwl[15:12], ram_rwl[7:4]}, |
| 2374 | | {ram_rwl[127:126], ram_rwl[123:122], ram_rwl[119:118], ram_rwl[115:114], |
| 2375 | ram_rwl[111:110], ram_rwl[107:106], ram_rwl[103:102], ram_rwl[99:98], |
| 2376 | ram_rwl[95:94], ram_rwl[91:90], ram_rwl[87:86], ram_rwl[83:82], |
| 2377 | ram_rwl[79:78], ram_rwl[75:74], ram_rwl[71:70], ram_rwl[67:66], |
| 2378 | ram_rwl[63:62], ram_rwl[59:58], ram_rwl[55:54], ram_rwl[51:50], |
| 2379 | ram_rwl[47:46], ram_rwl[43:42], ram_rwl[39:38], ram_rwl[35:34], |
| 2380 | ram_rwl[31:30], ram_rwl[27:26], ram_rwl[23:22], ram_rwl[19:18], |
| 2381 | ram_rwl[15:14], ram_rwl[11:10], ram_rwl[7:6], ram_rwl[3:2]}, |
| 2382 | | {ram_rwl[127], ram_rwl[125], ram_rwl[123], ram_rwl[121], |
| 2383 | ram_rwl[119], ram_rwl[117], ram_rwl[115], ram_rwl[113], ram_rwl[111], |
| 2384 | ram_rwl[109], ram_rwl[107], ram_rwl[105], ram_rwl[103], ram_rwl[101], |
| 2385 | ram_rwl[99], ram_rwl[97], ram_rwl[95], ram_rwl[93], ram_rwl[91], |
| 2386 | ram_rwl[89], ram_rwl[87], ram_rwl[85], ram_rwl[83], ram_rwl[81], |
| 2387 | ram_rwl[79], ram_rwl[77], ram_rwl[75], ram_rwl[73], ram_rwl[71], |
| 2388 | ram_rwl[69], ram_rwl[67], ram_rwl[65], ram_rwl[63], ram_rwl[61], |
| 2389 | ram_rwl[59], ram_rwl[57], ram_rwl[55], ram_rwl[53], ram_rwl[51], |
| 2390 | ram_rwl[49], ram_rwl[47], ram_rwl[45], ram_rwl[43], ram_rwl[41], |
| 2391 | ram_rwl[39], ram_rwl[37], ram_rwl[35], ram_rwl[33], ram_rwl[31], |
| 2392 | ram_rwl[29], ram_rwl[27], ram_rwl[25], ram_rwl[23], ram_rwl[21], |
| 2393 | ram_rwl[19], ram_rwl[17], ram_rwl[15], ram_rwl[13], ram_rwl[11], |
| 2394 | ram_rwl[9], ram_rwl[7], ram_rwl[5], ram_rwl[3], ram_rwl[1]}}; |
| 2395 | |
| 2396 | assign any_wwl = |
| 2397 | | ram_wwl[`ENTRIES-1:0]; |
| 2398 | |
| 2399 | assign any_rwl = |
| 2400 | | ram_rwl[`ENTRIES-1:0]; |
| 2401 | |
| 2402 | |
| 2403 | |
| 2404 | |
| 2405 | |
| 2406 | |
| 2407 | |
| 2408 | |
| 2409 | |
| 2410 | |
| 2411 | |
| 2412 | //---------------------------------------------------------------------- |
| 2413 | // Declarations |
| 2414 | //---------------------------------------------------------------------- |
| 2415 | |
| 2416 | reg [37:0] tlb_data[`ENTRIES-1:0] ; // this models the data array |
| 2417 | |
| 2418 | integer n; |
| 2419 | |
| 2420 | `ifndef NOINITMEM |
| 2421 | /////////////////////////////////////// |
| 2422 | // Initialize the arrays. // |
| 2423 | /////////////////////////////////////// |
| 2424 | initial begin |
| 2425 | for (n = 0; n < `ENTRIES; n = n + 1) begin |
| 2426 | tlb_data[n] = {38 {1'b0}}; |
| 2427 | end |
| 2428 | `ifdef ENABLE_DUMPMEM |
| 2429 | if ($test$plusargs("DUMPMEM_DTLB")) begin |
| 2430 | $fsdbDumpMem(tlb_data, 0, `ENTRIES); |
| 2431 | end |
| 2432 | `endif |
| 2433 | end |
| 2434 | `endif |
| 2435 | |
| 2436 | |
| 2437 | |
| 2438 | |
| 2439 | |
| 2440 | /////////////////////////////////////////////////////////////// |
| 2441 | // Write // |
| 2442 | /////////////////////////////////////////////////////////////// |
| 2443 | always @(negedge l1clk) begin |
| 2444 | |
| 2445 | for (n = 0; n < `ENTRIES; n = n + 1) begin |
| 2446 | if (ram_wwl[n]) begin |
| 2447 | tlb_data[n] <= tte_data[37:0]; |
| 2448 | |
| 2449 | |
| 2450 | |
| 2451 | |
| 2452 | n = `ENTRIES; |
| 2453 | |
| 2454 | end // if (ram_wl[n]) |
| 2455 | end // for (n = 0; n < `ENTRIES; n = n + 1) |
| 2456 | |
| 2457 | end // always @ (ram_wl[`ENTRIES-1:0]) |
| 2458 | |
| 2459 | |
| 2460 | |
| 2461 | /////////////////////////////////////////////////////////////// |
| 2462 | // Read // |
| 2463 | /////////////////////////////////////////////////////////////// |
| 2464 | |
| 2465 | // ram_rwl is now second half cycle signal... so no need to latch |
| 2466 | // Only force outputs to X if read and write at same time |
| 2467 | // or on multiple hit |
| 2468 | assign rd_tte_data[37:0] = |
| 2469 | ({38 {any_rwl & ~any_wwl & ~force_data_to_x}} & tlb_data[encoded_rwl]) | |
| 2470 | ({38 {any_rwl & any_wwl & 1'bx}}) | |
| 2471 | ({38 {force_data_to_x & 1'bx}}) ; |
| 2472 | |
| 2473 | |
| 2474 | |
| 2475 | |
| 2476 | |
| 2477 | /////////////////////////////////////////////////////////////// |
| 2478 | // Construct the physical page number // |
| 2479 | /////////////////////////////////////////////////////////////// |
| 2480 | assign tte_pa[39:13] = {rd_tte_data[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], |
| 2481 | rd_tte_data[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO], |
| 2482 | rd_tte_data[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO], |
| 2483 | rd_tte_data[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO]}; |
| 2484 | |
| 2485 | assign pa[12:11] = va[12:11]; |
| 2486 | |
| 2487 | assign pa[15:13] = |
| 2488 | (~rd_tte_data[`DATA_VA_15_13_V] & tlb_cam_flopped & ~tlb_bypass) ? |
| 2489 | tte_pa[15:13] : va[15:13] ; |
| 2490 | assign pa[21:16] = |
| 2491 | (~rd_tte_data[`DATA_VA_21_16_V] & tlb_cam_flopped & ~tlb_bypass) ? |
| 2492 | tte_pa[21:16] : va[21:16] ; |
| 2493 | assign pa[27:22] = |
| 2494 | (~rd_tte_data[`DATA_VA_27_22_V] & tlb_cam_flopped & ~tlb_bypass) ? |
| 2495 | tte_pa[27:22] : va[27:22] ; |
| 2496 | assign pa[39:28] = |
| 2497 | (tlb_cam_flopped & ~tlb_bypass) ? |
| 2498 | tte_pa[39:28] : va[39:28]; |
| 2499 | |
| 2500 | |
| 2501 | |
| 2502 | |
| 2503 | supply0 vss; // <- port for ground |
| 2504 | supply1 vdd; // <- port for power |
| 2505 | |
| 2506 | endmodule |
| 2507 | `endif // `ifndef FPGA |
| 2508 | |
| 2509 | `ifdef FPGA |
| 2510 | module n2_tlb_tl_128x59_ram(l1clk, tlb_bypass, tlb_cam_flopped, ram_wwl, |
| 2511 | ram_rwl, tte_data, va, force_data_to_x, pa, rd_tte_data); |
| 2512 | |
| 2513 | input l1clk; |
| 2514 | input tlb_bypass; |
| 2515 | input tlb_cam_flopped; |
| 2516 | input [(128 - 1):0] ram_wwl; |
| 2517 | input [(128 - 1):0] ram_rwl; |
| 2518 | input [37:0] tte_data; |
| 2519 | input [39:11] va; |
| 2520 | input force_data_to_x; |
| 2521 | output [39:11] pa; |
| 2522 | output [37:0] rd_tte_data; |
| 2523 | |
| 2524 | wire [6:0] encoded_rwl; |
| 2525 | wire any_wwl; |
| 2526 | wire any_rwl; |
| 2527 | wire [39:13] tte_pa; |
| 2528 | |
| 2529 | reg [37:0] tlb_data[(128 - 1):0]; |
| 2530 | integer n; |
| 2531 | supply0 vss; |
| 2532 | supply1 vdd; |
| 2533 | |
| 2534 | assign encoded_rwl[6:0] = {(|{ram_rwl[127:64]}), (|{ram_rwl[127:96], |
| 2535 | ram_rwl[63:32]}), (|{ram_rwl[127:112], ram_rwl[95:80], |
| 2536 | ram_rwl[63:48], ram_rwl[31:16]}), (|{ram_rwl[127:120], |
| 2537 | ram_rwl[111:104], ram_rwl[95:88], ram_rwl[79:72], |
| 2538 | ram_rwl[63:56], ram_rwl[47:40], ram_rwl[31:24], ram_rwl[15:8]}), |
| 2539 | (|{ram_rwl[127:124], ram_rwl[119:116], ram_rwl[111:108], |
| 2540 | ram_rwl[103:100], ram_rwl[95:92], ram_rwl[87:84], |
| 2541 | ram_rwl[79:76], ram_rwl[71:68], ram_rwl[63:60], ram_rwl[55:52], |
| 2542 | ram_rwl[47:44], ram_rwl[39:36], ram_rwl[31:28], ram_rwl[23:20], |
| 2543 | ram_rwl[15:12], ram_rwl[7:4]}), (|{ram_rwl[127:126], |
| 2544 | ram_rwl[123:122], ram_rwl[119:118], ram_rwl[115:114], |
| 2545 | ram_rwl[111:110], ram_rwl[107:106], ram_rwl[103:102], |
| 2546 | ram_rwl[99:98], ram_rwl[95:94], ram_rwl[91:90], ram_rwl[87:86], |
| 2547 | ram_rwl[83:82], ram_rwl[79:78], ram_rwl[75:74], ram_rwl[71:70], |
| 2548 | ram_rwl[67:66], ram_rwl[63:62], ram_rwl[59:58], ram_rwl[55:54], |
| 2549 | ram_rwl[51:50], ram_rwl[47:46], ram_rwl[43:42], ram_rwl[39:38], |
| 2550 | ram_rwl[35:34], ram_rwl[31:30], ram_rwl[27:26], ram_rwl[23:22], |
| 2551 | ram_rwl[19:18], ram_rwl[15:14], ram_rwl[11:10], ram_rwl[7:6], |
| 2552 | ram_rwl[3:2]}), (|{ram_rwl[127], ram_rwl[125], ram_rwl[123], |
| 2553 | ram_rwl[121], ram_rwl[119], ram_rwl[117], ram_rwl[115], |
| 2554 | ram_rwl[113], ram_rwl[111], ram_rwl[109], ram_rwl[107], |
| 2555 | ram_rwl[105], ram_rwl[103], ram_rwl[101], ram_rwl[99], |
| 2556 | ram_rwl[97], ram_rwl[95], ram_rwl[93], ram_rwl[91], ram_rwl[89], |
| 2557 | ram_rwl[87], ram_rwl[85], ram_rwl[83], ram_rwl[81], ram_rwl[79], |
| 2558 | ram_rwl[77], ram_rwl[75], ram_rwl[73], ram_rwl[71], ram_rwl[69], |
| 2559 | ram_rwl[67], ram_rwl[65], ram_rwl[63], ram_rwl[61], ram_rwl[59], |
| 2560 | ram_rwl[57], ram_rwl[55], ram_rwl[53], ram_rwl[51], ram_rwl[49], |
| 2561 | ram_rwl[47], ram_rwl[45], ram_rwl[43], ram_rwl[41], ram_rwl[39], |
| 2562 | ram_rwl[37], ram_rwl[35], ram_rwl[33], ram_rwl[31], ram_rwl[29], |
| 2563 | ram_rwl[27], ram_rwl[25], ram_rwl[23], ram_rwl[21], ram_rwl[19], |
| 2564 | ram_rwl[17], ram_rwl[15], ram_rwl[13], ram_rwl[11], ram_rwl[9], |
| 2565 | ram_rwl[7], ram_rwl[5], ram_rwl[3], ram_rwl[1]})}; |
| 2566 | assign any_wwl = (|ram_wwl[(128 - 1):0]); |
| 2567 | assign any_rwl = (|ram_rwl[(128 - 1):0]); |
| 2568 | assign rd_tte_data[37:0] = ((({38 {((any_rwl & (~any_wwl)) & |
| 2569 | (~force_data_to_x))}} & tlb_data[encoded_rwl]) | {38 {((any_rwl |
| 2570 | & any_wwl) & 1'bx)}}) | {38 {(force_data_to_x & 1'bx)}}); |
| 2571 | assign tte_pa[39:13] = {rd_tte_data[35:24], rd_tte_data[23:18], |
| 2572 | rd_tte_data[16:11], rd_tte_data[9:7]}; |
| 2573 | assign pa[12:11] = va[12:11]; |
| 2574 | assign pa[15:13] = ((((~rd_tte_data[6]) & tlb_cam_flopped) & (~ |
| 2575 | tlb_bypass)) ? tte_pa[15:13] : va[15:13]); |
| 2576 | assign pa[21:16] = ((((~rd_tte_data[10]) & tlb_cam_flopped) & (~ |
| 2577 | tlb_bypass)) ? tte_pa[21:16] : va[21:16]); |
| 2578 | assign pa[27:22] = ((((~rd_tte_data[17]) & tlb_cam_flopped) & (~ |
| 2579 | tlb_bypass)) ? tte_pa[27:22] : va[27:22]); |
| 2580 | assign pa[39:28] = ((tlb_cam_flopped & (~tlb_bypass)) ? tte_pa[39:28] : |
| 2581 | va[39:28]); |
| 2582 | |
| 2583 | initial begin |
| 2584 | for (n = 0; (n < 128); n = (n + 1)) begin |
| 2585 | tlb_data[n] = {38 {1'b0}}; |
| 2586 | end |
| 2587 | end |
| 2588 | always @(negedge l1clk) begin |
| 2589 | for (n = 0; (n < 128); n = (n + 1)) begin |
| 2590 | if (ram_wwl[n]) begin |
| 2591 | tlb_data[n] <= tte_data[37:0]; |
| 2592 | end |
| 2593 | end |
| 2594 | end |
| 2595 | endmodule |
| 2596 | |
| 2597 | `endif |
| 2598 | |
| 2599 | |
| 2600 | |
| 2601 | module n2_tlb_tl_128x59_multihit ( |
| 2602 | ram_rwl, |
| 2603 | tlb_bypass, |
| 2604 | tlb_cam_mhit, |
| 2605 | force_data_to_x) ; |
| 2606 | wire [7:0] sum; |
| 2607 | wire multiple_match; |
| 2608 | wire unused; |
| 2609 | |
| 2610 | |
| 2611 | `define ENTRIES 128 |
| 2612 | //`define INDEX 6 |
| 2613 | |
| 2614 | |
| 2615 | input [`ENTRIES-1:0] ram_rwl; |
| 2616 | input tlb_bypass; |
| 2617 | |
| 2618 | |
| 2619 | |
| 2620 | output tlb_cam_mhit; |
| 2621 | output force_data_to_x; |
| 2622 | |
| 2623 | |
| 2624 | |
| 2625 | |
| 2626 | |
| 2627 | assign sum[7:0] = |
| 2628 | {{7 {1'b0}}, ram_rwl[0]} + |
| 2629 | {{7 {1'b0}}, ram_rwl[1]} + |
| 2630 | {{7 {1'b0}}, ram_rwl[2]} + |
| 2631 | {{7 {1'b0}}, ram_rwl[3]} + |
| 2632 | {{7 {1'b0}}, ram_rwl[4]} + |
| 2633 | {{7 {1'b0}}, ram_rwl[5]} + |
| 2634 | {{7 {1'b0}}, ram_rwl[6]} + |
| 2635 | {{7 {1'b0}}, ram_rwl[7]} + |
| 2636 | {{7 {1'b0}}, ram_rwl[8]} + |
| 2637 | {{7 {1'b0}}, ram_rwl[9]} + |
| 2638 | {{7 {1'b0}}, ram_rwl[10]} + |
| 2639 | {{7 {1'b0}}, ram_rwl[11]} + |
| 2640 | {{7 {1'b0}}, ram_rwl[12]} + |
| 2641 | {{7 {1'b0}}, ram_rwl[13]} + |
| 2642 | {{7 {1'b0}}, ram_rwl[14]} + |
| 2643 | {{7 {1'b0}}, ram_rwl[15]} + |
| 2644 | {{7 {1'b0}}, ram_rwl[16]} + |
| 2645 | {{7 {1'b0}}, ram_rwl[17]} + |
| 2646 | {{7 {1'b0}}, ram_rwl[18]} + |
| 2647 | {{7 {1'b0}}, ram_rwl[19]} + |
| 2648 | {{7 {1'b0}}, ram_rwl[20]} + |
| 2649 | {{7 {1'b0}}, ram_rwl[21]} + |
| 2650 | {{7 {1'b0}}, ram_rwl[22]} + |
| 2651 | {{7 {1'b0}}, ram_rwl[23]} + |
| 2652 | {{7 {1'b0}}, ram_rwl[24]} + |
| 2653 | {{7 {1'b0}}, ram_rwl[25]} + |
| 2654 | {{7 {1'b0}}, ram_rwl[26]} + |
| 2655 | {{7 {1'b0}}, ram_rwl[27]} + |
| 2656 | {{7 {1'b0}}, ram_rwl[28]} + |
| 2657 | {{7 {1'b0}}, ram_rwl[29]} + |
| 2658 | {{7 {1'b0}}, ram_rwl[30]} + |
| 2659 | {{7 {1'b0}}, ram_rwl[31]} + |
| 2660 | {{7 {1'b0}}, ram_rwl[32]} + |
| 2661 | {{7 {1'b0}}, ram_rwl[33]} + |
| 2662 | {{7 {1'b0}}, ram_rwl[34]} + |
| 2663 | {{7 {1'b0}}, ram_rwl[35]} + |
| 2664 | {{7 {1'b0}}, ram_rwl[36]} + |
| 2665 | {{7 {1'b0}}, ram_rwl[37]} + |
| 2666 | {{7 {1'b0}}, ram_rwl[38]} + |
| 2667 | {{7 {1'b0}}, ram_rwl[39]} + |
| 2668 | {{7 {1'b0}}, ram_rwl[40]} + |
| 2669 | {{7 {1'b0}}, ram_rwl[41]} + |
| 2670 | {{7 {1'b0}}, ram_rwl[42]} + |
| 2671 | {{7 {1'b0}}, ram_rwl[43]} + |
| 2672 | {{7 {1'b0}}, ram_rwl[44]} + |
| 2673 | {{7 {1'b0}}, ram_rwl[45]} + |
| 2674 | {{7 {1'b0}}, ram_rwl[46]} + |
| 2675 | {{7 {1'b0}}, ram_rwl[47]} + |
| 2676 | {{7 {1'b0}}, ram_rwl[48]} + |
| 2677 | {{7 {1'b0}}, ram_rwl[49]} + |
| 2678 | {{7 {1'b0}}, ram_rwl[50]} + |
| 2679 | {{7 {1'b0}}, ram_rwl[51]} + |
| 2680 | {{7 {1'b0}}, ram_rwl[52]} + |
| 2681 | {{7 {1'b0}}, ram_rwl[53]} + |
| 2682 | {{7 {1'b0}}, ram_rwl[54]} + |
| 2683 | {{7 {1'b0}}, ram_rwl[55]} + |
| 2684 | {{7 {1'b0}}, ram_rwl[56]} + |
| 2685 | {{7 {1'b0}}, ram_rwl[57]} + |
| 2686 | {{7 {1'b0}}, ram_rwl[58]} + |
| 2687 | {{7 {1'b0}}, ram_rwl[59]} + |
| 2688 | {{7 {1'b0}}, ram_rwl[60]} + |
| 2689 | {{7 {1'b0}}, ram_rwl[61]} + |
| 2690 | {{7 {1'b0}}, ram_rwl[62]} + |
| 2691 | {{7 {1'b0}}, ram_rwl[63]} + |
| 2692 | {{7 {1'b0}}, ram_rwl[64]} + |
| 2693 | {{7 {1'b0}}, ram_rwl[65]} + |
| 2694 | {{7 {1'b0}}, ram_rwl[66]} + |
| 2695 | {{7 {1'b0}}, ram_rwl[67]} + |
| 2696 | {{7 {1'b0}}, ram_rwl[68]} + |
| 2697 | {{7 {1'b0}}, ram_rwl[69]} + |
| 2698 | {{7 {1'b0}}, ram_rwl[70]} + |
| 2699 | {{7 {1'b0}}, ram_rwl[71]} + |
| 2700 | {{7 {1'b0}}, ram_rwl[72]} + |
| 2701 | {{7 {1'b0}}, ram_rwl[73]} + |
| 2702 | {{7 {1'b0}}, ram_rwl[74]} + |
| 2703 | {{7 {1'b0}}, ram_rwl[75]} + |
| 2704 | {{7 {1'b0}}, ram_rwl[76]} + |
| 2705 | {{7 {1'b0}}, ram_rwl[77]} + |
| 2706 | {{7 {1'b0}}, ram_rwl[78]} + |
| 2707 | {{7 {1'b0}}, ram_rwl[79]} + |
| 2708 | {{7 {1'b0}}, ram_rwl[80]} + |
| 2709 | {{7 {1'b0}}, ram_rwl[81]} + |
| 2710 | {{7 {1'b0}}, ram_rwl[82]} + |
| 2711 | {{7 {1'b0}}, ram_rwl[83]} + |
| 2712 | {{7 {1'b0}}, ram_rwl[84]} + |
| 2713 | {{7 {1'b0}}, ram_rwl[85]} + |
| 2714 | {{7 {1'b0}}, ram_rwl[86]} + |
| 2715 | {{7 {1'b0}}, ram_rwl[87]} + |
| 2716 | {{7 {1'b0}}, ram_rwl[88]} + |
| 2717 | {{7 {1'b0}}, ram_rwl[89]} + |
| 2718 | {{7 {1'b0}}, ram_rwl[90]} + |
| 2719 | {{7 {1'b0}}, ram_rwl[91]} + |
| 2720 | {{7 {1'b0}}, ram_rwl[92]} + |
| 2721 | {{7 {1'b0}}, ram_rwl[93]} + |
| 2722 | {{7 {1'b0}}, ram_rwl[94]} + |
| 2723 | {{7 {1'b0}}, ram_rwl[95]} + |
| 2724 | {{7 {1'b0}}, ram_rwl[96]} + |
| 2725 | {{7 {1'b0}}, ram_rwl[97]} + |
| 2726 | {{7 {1'b0}}, ram_rwl[98]} + |
| 2727 | {{7 {1'b0}}, ram_rwl[99]} + |
| 2728 | {{7 {1'b0}}, ram_rwl[100]} + |
| 2729 | {{7 {1'b0}}, ram_rwl[101]} + |
| 2730 | {{7 {1'b0}}, ram_rwl[102]} + |
| 2731 | {{7 {1'b0}}, ram_rwl[103]} + |
| 2732 | {{7 {1'b0}}, ram_rwl[104]} + |
| 2733 | {{7 {1'b0}}, ram_rwl[105]} + |
| 2734 | {{7 {1'b0}}, ram_rwl[106]} + |
| 2735 | {{7 {1'b0}}, ram_rwl[107]} + |
| 2736 | {{7 {1'b0}}, ram_rwl[108]} + |
| 2737 | {{7 {1'b0}}, ram_rwl[109]} + |
| 2738 | {{7 {1'b0}}, ram_rwl[110]} + |
| 2739 | {{7 {1'b0}}, ram_rwl[111]} + |
| 2740 | {{7 {1'b0}}, ram_rwl[112]} + |
| 2741 | {{7 {1'b0}}, ram_rwl[113]} + |
| 2742 | {{7 {1'b0}}, ram_rwl[114]} + |
| 2743 | {{7 {1'b0}}, ram_rwl[115]} + |
| 2744 | {{7 {1'b0}}, ram_rwl[116]} + |
| 2745 | {{7 {1'b0}}, ram_rwl[117]} + |
| 2746 | {{7 {1'b0}}, ram_rwl[118]} + |
| 2747 | {{7 {1'b0}}, ram_rwl[119]} + |
| 2748 | {{7 {1'b0}}, ram_rwl[120]} + |
| 2749 | {{7 {1'b0}}, ram_rwl[121]} + |
| 2750 | {{7 {1'b0}}, ram_rwl[122]} + |
| 2751 | {{7 {1'b0}}, ram_rwl[123]} + |
| 2752 | {{7 {1'b0}}, ram_rwl[124]} + |
| 2753 | {{7 {1'b0}}, ram_rwl[125]} + |
| 2754 | {{7 {1'b0}}, ram_rwl[126]} + |
| 2755 | {{7 {1'b0}}, ram_rwl[127]} ; |
| 2756 | |
| 2757 | |
| 2758 | assign force_data_to_x = |
| 2759 | (| sum[7:1]); |
| 2760 | |
| 2761 | assign multiple_match = |
| 2762 | (| sum[7:1]) & ~tlb_bypass; |
| 2763 | |
| 2764 | assign unused = sum[0]; |
| 2765 | |
| 2766 | assign tlb_cam_mhit = |
| 2767 | multiple_match; |
| 2768 | |
| 2769 | |
| 2770 | supply0 vss; // <- port for ground |
| 2771 | supply1 vdd; // <- port for power |
| 2772 | endmodule |
| 2773 | |
| 2774 | |
| 2775 | `ifndef FPGA |
| 2776 | module n2_tlb_tl_128x59_ubit ( |
| 2777 | l1clk, |
| 2778 | disable_clear_ubit, |
| 2779 | tlb_bypass, |
| 2780 | ram_rwl, |
| 2781 | ram_wwl, |
| 2782 | tte_ubit, |
| 2783 | tlb_wr_flopped, |
| 2784 | tlb_rd_flopped, |
| 2785 | tlb_cam_flopped, |
| 2786 | used, |
| 2787 | rd_tte_u_bit) ; |
| 2788 | wire all_entries_used; |
| 2789 | |
| 2790 | |
| 2791 | `define ENTRIES 128 |
| 2792 | |
| 2793 | |
| 2794 | |
| 2795 | input l1clk; |
| 2796 | input disable_clear_ubit; |
| 2797 | |
| 2798 | input tlb_bypass; |
| 2799 | input [`ENTRIES-1:0] ram_rwl; |
| 2800 | input [`ENTRIES-1:0] ram_wwl; |
| 2801 | input tte_ubit; |
| 2802 | |
| 2803 | input tlb_wr_flopped; |
| 2804 | input tlb_rd_flopped; |
| 2805 | input tlb_cam_flopped; |
| 2806 | |
| 2807 | |
| 2808 | |
| 2809 | output [`ENTRIES-1:0] used; |
| 2810 | output rd_tte_u_bit; |
| 2811 | |
| 2812 | |
| 2813 | |
| 2814 | //---------------------------------------------------------------------- |
| 2815 | // Declarations |
| 2816 | //---------------------------------------------------------------------- |
| 2817 | reg [`ENTRIES-1:0] used; |
| 2818 | |
| 2819 | integer n; |
| 2820 | |
| 2821 | reg rd_tte_u_bit_in; |
| 2822 | |
| 2823 | |
| 2824 | `ifndef NOINITMEM |
| 2825 | /////////////////////////////////////// |
| 2826 | // Initialize the arrays. // |
| 2827 | /////////////////////////////////////// |
| 2828 | initial begin |
| 2829 | used[`ENTRIES-1:0] = {`ENTRIES {1'b0}} ; |
| 2830 | end |
| 2831 | `endif |
| 2832 | |
| 2833 | |
| 2834 | |
| 2835 | assign all_entries_used = |
| 2836 | (& used[`ENTRIES-1:0]) & ~disable_clear_ubit; |
| 2837 | |
| 2838 | |
| 2839 | always @(negedge l1clk) begin |
| 2840 | // Maintain the used bits |
| 2841 | if (all_entries_used) begin |
| 2842 | used[`ENTRIES-1:0] <= {`ENTRIES {1'b0}}; |
| 2843 | end |
| 2844 | |
| 2845 | if (~all_entries_used & ((~tlb_bypass & tlb_cam_flopped) | tlb_wr_flopped)) begin |
| 2846 | for (n = 0; n < `ENTRIES; n = n + 1) begin |
| 2847 | if (ram_rwl[n]) begin |
| 2848 | used[n] <= 1'b1; |
| 2849 | end |
| 2850 | if (ram_wwl[n]) begin |
| 2851 | used[n] <= tte_ubit; |
| 2852 | end |
| 2853 | end |
| 2854 | end // if (~all_entries_used & ((~tlb_bypass & tlb_cam_flopped) | tlb_wr_flopped)) |
| 2855 | |
| 2856 | |
| 2857 | end // always @ (negedge l1clk) |
| 2858 | |
| 2859 | |
| 2860 | |
| 2861 | |
| 2862 | /////////////////////////////////////////////////////////////// |
| 2863 | // Read U bit |
| 2864 | /////////////////////////////////////////////////////////////// |
| 2865 | |
| 2866 | |
| 2867 | always @(ram_rwl[`ENTRIES-1:0] or used[`ENTRIES-1:0] or tlb_rd_flopped) begin |
| 2868 | |
| 2869 | rd_tte_u_bit_in = {1'b0}; |
| 2870 | |
| 2871 | if (tlb_rd_flopped & (| ram_rwl[`ENTRIES-1:0])) begin |
| 2872 | for (n = 0; n < `ENTRIES; n = n + 1) begin |
| 2873 | if (ram_rwl[n]) begin |
| 2874 | rd_tte_u_bit_in = used[n]; |
| 2875 | |
| 2876 | |
| 2877 | n = `ENTRIES; |
| 2878 | |
| 2879 | end // if (ram_wl[n]) |
| 2880 | end // for (n = 0; n < `ENTRIES; n = n + 1) |
| 2881 | end // if (tlb_rd_flopped & (| ram_rwl[`ENTRIES-1:0])) |
| 2882 | else if (~tlb_rd_flopped & (| ram_rwl[`ENTRIES-1:0])) begin |
| 2883 | rd_tte_u_bit_in = {1'bx}; |
| 2884 | end |
| 2885 | |
| 2886 | end |
| 2887 | |
| 2888 | assign rd_tte_u_bit = |
| 2889 | rd_tte_u_bit_in; |
| 2890 | |
| 2891 | |
| 2892 | supply0 vss; // <- port for ground |
| 2893 | supply1 vdd; // <- port for power |
| 2894 | endmodule |
| 2895 | |
| 2896 | `endif // `ifndef FPGA |
| 2897 | |
| 2898 | `ifdef FPGA |
| 2899 | |
| 2900 | module n2_tlb_tl_128x59_ubit(l1clk, disable_clear_ubit, tlb_bypass, ram_rwl, |
| 2901 | ram_wwl, tte_ubit, tlb_wr_flopped, tlb_rd_flopped, tlb_cam_flopped, |
| 2902 | used, rd_tte_u_bit); |
| 2903 | |
| 2904 | input l1clk; |
| 2905 | input disable_clear_ubit; |
| 2906 | input tlb_bypass; |
| 2907 | input [(128 - 1):0] ram_rwl; |
| 2908 | input [(128 - 1):0] ram_wwl; |
| 2909 | input tte_ubit; |
| 2910 | input tlb_wr_flopped; |
| 2911 | input tlb_rd_flopped; |
| 2912 | input tlb_cam_flopped; |
| 2913 | output [(128 - 1):0] used; |
| 2914 | output rd_tte_u_bit; |
| 2915 | |
| 2916 | wire all_entries_used; |
| 2917 | reg [(128 - 1):0] used; |
| 2918 | integer n; |
| 2919 | reg rd_tte_u_bit_in; |
| 2920 | supply0 vss; |
| 2921 | supply1 vdd; |
| 2922 | |
| 2923 | assign all_entries_used = ((&used[(128 - 1):0]) & (~disable_clear_ubit)) |
| 2924 | ; |
| 2925 | assign rd_tte_u_bit = rd_tte_u_bit_in; |
| 2926 | |
| 2927 | initial begin |
| 2928 | used[(128 - 1):0] = {128 {1'b0}}; |
| 2929 | end |
| 2930 | always @(negedge l1clk) begin |
| 2931 | if (all_entries_used) begin |
| 2932 | used[(128 - 1):0] <= {128 {1'b0}}; |
| 2933 | end |
| 2934 | if ((~all_entries_used) & (((~tlb_bypass) & tlb_cam_flopped) | |
| 2935 | tlb_wr_flopped)) begin |
| 2936 | for (n = 0; (n < 128); n = (n + 1)) begin |
| 2937 | if (ram_rwl[n]) begin |
| 2938 | used[n] <= 1'b1; |
| 2939 | end |
| 2940 | if (ram_wwl[n]) begin |
| 2941 | used[n] <= tte_ubit; |
| 2942 | end |
| 2943 | end |
| 2944 | end |
| 2945 | end |
| 2946 | always @(ram_rwl[(128 - 1):0] or used[(128 - 1):0] or tlb_rd_flopped) |
| 2947 | begin |
| 2948 | rd_tte_u_bit_in = {1'b0}; |
| 2949 | if (tlb_rd_flopped & (|ram_rwl[(128 - 1):0])) begin |
| 2950 | for (n = 0; (n < 128); n = (n + 1)) begin |
| 2951 | if (ram_rwl[n]) begin |
| 2952 | rd_tte_u_bit_in = used[n]; |
| 2953 | end |
| 2954 | end |
| 2955 | end |
| 2956 | else if ((~tlb_rd_flopped) & (|ram_rwl[(128 - 1):0])) begin |
| 2957 | rd_tte_u_bit_in = {1'bx}; |
| 2958 | end |
| 2959 | end |
| 2960 | endmodule |
| 2961 | |
| 2962 | `endif // `ifdef FPGA |
| 2963 | |
| 2964 | |
| 2965 | |
| 2966 | |
| 2967 | module n2_tlb_tl_128x59_repl_index ( |
| 2968 | l1clk, |
| 2969 | used, |
| 2970 | valid, |
| 2971 | tlb_replacement_index) ; |
| 2972 | wire [127:0] nu_or_nv; |
| 2973 | wire [127:0] used_and_valid; |
| 2974 | wire [1:0] enc4_00; |
| 2975 | wire sel4_00_b; |
| 2976 | wire [1:0] enc4_01; |
| 2977 | wire sel4_01_b; |
| 2978 | wire [1:0] enc4_02; |
| 2979 | wire sel4_02_b; |
| 2980 | wire [1:0] enc4_03; |
| 2981 | wire sel4_03_b; |
| 2982 | wire [1:0] enc4_04; |
| 2983 | wire sel4_04_b; |
| 2984 | wire [1:0] enc4_05; |
| 2985 | wire sel4_05_b; |
| 2986 | wire [1:0] enc4_06; |
| 2987 | wire sel4_06_b; |
| 2988 | wire [1:0] enc4_07; |
| 2989 | wire sel4_07_b; |
| 2990 | wire [1:0] enc4_08; |
| 2991 | wire sel4_08_b; |
| 2992 | wire [1:0] enc4_09; |
| 2993 | wire sel4_09_b; |
| 2994 | wire [1:0] enc4_10; |
| 2995 | wire sel4_10_b; |
| 2996 | wire [1:0] enc4_11; |
| 2997 | wire sel4_11_b; |
| 2998 | wire [1:0] enc4_12; |
| 2999 | wire sel4_12_b; |
| 3000 | wire [1:0] enc4_13; |
| 3001 | wire sel4_13_b; |
| 3002 | wire [1:0] enc4_14; |
| 3003 | wire sel4_14_b; |
| 3004 | wire [1:0] enc4_15; |
| 3005 | wire sel4_15_b; |
| 3006 | wire [1:0] enc4_16; |
| 3007 | wire sel4_16_b; |
| 3008 | wire [1:0] enc4_17; |
| 3009 | wire sel4_17_b; |
| 3010 | wire [1:0] enc4_18; |
| 3011 | wire sel4_18_b; |
| 3012 | wire [1:0] enc4_19; |
| 3013 | wire sel4_19_b; |
| 3014 | wire [1:0] enc4_20; |
| 3015 | wire sel4_20_b; |
| 3016 | wire [1:0] enc4_21; |
| 3017 | wire sel4_21_b; |
| 3018 | wire [1:0] enc4_22; |
| 3019 | wire sel4_22_b; |
| 3020 | wire [1:0] enc4_23; |
| 3021 | wire sel4_23_b; |
| 3022 | wire [1:0] enc4_24; |
| 3023 | wire sel4_24_b; |
| 3024 | wire [1:0] enc4_25; |
| 3025 | wire sel4_25_b; |
| 3026 | wire [1:0] enc4_26; |
| 3027 | wire sel4_26_b; |
| 3028 | wire [1:0] enc4_27; |
| 3029 | wire sel4_27_b; |
| 3030 | wire [1:0] enc4_28; |
| 3031 | wire sel4_28_b; |
| 3032 | wire [1:0] enc4_29; |
| 3033 | wire sel4_29_b; |
| 3034 | wire [1:0] enc4_30; |
| 3035 | wire sel4_30_b; |
| 3036 | wire [1:0] enc4_31; |
| 3037 | wire sel4_31_b; |
| 3038 | wire [2:0] enc8_00; |
| 3039 | wire sel8_00_b; |
| 3040 | wire [2:0] enc8_01; |
| 3041 | wire sel8_01_b; |
| 3042 | wire [2:0] enc8_02; |
| 3043 | wire sel8_02_b; |
| 3044 | wire [2:0] enc8_03; |
| 3045 | wire sel8_03_b; |
| 3046 | wire [2:0] enc8_04; |
| 3047 | wire sel8_04_b; |
| 3048 | wire [2:0] enc8_05; |
| 3049 | wire sel8_05_b; |
| 3050 | wire [2:0] enc8_06; |
| 3051 | wire sel8_06_b; |
| 3052 | wire [2:0] enc8_07; |
| 3053 | wire sel8_07_b; |
| 3054 | wire [2:0] enc8_08; |
| 3055 | wire sel8_08_b; |
| 3056 | wire [2:0] enc8_09; |
| 3057 | wire sel8_09_b; |
| 3058 | wire [2:0] enc8_10; |
| 3059 | wire sel8_10_b; |
| 3060 | wire [2:0] enc8_11; |
| 3061 | wire sel8_11_b; |
| 3062 | wire [2:0] enc8_12; |
| 3063 | wire sel8_12_b; |
| 3064 | wire [2:0] enc8_13; |
| 3065 | wire sel8_13_b; |
| 3066 | wire [2:0] enc8_14; |
| 3067 | wire sel8_14_b; |
| 3068 | wire [2:0] enc8_15; |
| 3069 | wire sel8_15_b; |
| 3070 | wire [3:0] enc16_0; |
| 3071 | wire sel16_0_b; |
| 3072 | wire [3:0] enc16_1; |
| 3073 | wire sel16_1_b; |
| 3074 | wire [3:0] enc16_2; |
| 3075 | wire sel16_2_b; |
| 3076 | wire [3:0] enc16_3; |
| 3077 | wire sel16_3_b; |
| 3078 | wire [3:0] enc16_4; |
| 3079 | wire sel16_4_b; |
| 3080 | wire [3:0] enc16_5; |
| 3081 | wire sel16_5_b; |
| 3082 | wire [3:0] enc16_6; |
| 3083 | wire sel16_6_b; |
| 3084 | wire [3:0] enc16_7; |
| 3085 | wire sel16_7_b; |
| 3086 | wire unused; |
| 3087 | wire [3:0] enc16_l_0; |
| 3088 | wire [3:0] enc16_l_1; |
| 3089 | wire [3:0] enc16_l_2; |
| 3090 | wire [3:0] enc16_l_3; |
| 3091 | wire [3:0] enc16_l_4; |
| 3092 | wire [3:0] enc16_l_5; |
| 3093 | wire [3:0] enc16_l_6; |
| 3094 | wire [3:0] enc16_l_7; |
| 3095 | wire sel16_l_0_b; |
| 3096 | wire sel16_l_1_b; |
| 3097 | wire sel16_l_2_b; |
| 3098 | wire sel16_l_3_b; |
| 3099 | wire sel16_l_4_b; |
| 3100 | wire sel16_l_5_b; |
| 3101 | wire sel16_l_6_b; |
| 3102 | wire sel16_l_7_b_unused; |
| 3103 | wire [4:0] enc32_0; |
| 3104 | wire sel32_0_b; |
| 3105 | wire [4:0] enc32_1; |
| 3106 | wire sel32_1_b; |
| 3107 | wire [4:0] enc32_2; |
| 3108 | wire sel32_2_b; |
| 3109 | wire [4:0] enc32_3; |
| 3110 | wire [5:0] enc64_0; |
| 3111 | wire sel64_0_b; |
| 3112 | wire [5:0] enc64_1; |
| 3113 | wire [6:0] enc128_0; |
| 3114 | |
| 3115 | |
| 3116 | `define ENTRIES 128 |
| 3117 | `define INDEX 6 |
| 3118 | |
| 3119 | |
| 3120 | input l1clk; |
| 3121 | |
| 3122 | input [`ENTRIES-1:0] used; |
| 3123 | input [`ENTRIES-1:0] valid; |
| 3124 | |
| 3125 | |
| 3126 | output [`INDEX:0] tlb_replacement_index; |
| 3127 | |
| 3128 | |
| 3129 | |
| 3130 | assign nu_or_nv[`ENTRIES-1:0] = |
| 3131 | ~valid[`ENTRIES-1:0] | ~used[`ENTRIES-1:0]; |
| 3132 | |
| 3133 | assign used_and_valid[`ENTRIES-1:0] = |
| 3134 | ~nu_or_nv[`ENTRIES-1:0]; |
| 3135 | |
| 3136 | |
| 3137 | // 4 bit priority encoders |
| 3138 | assign enc4_00[1] = used_and_valid[0] & used_and_valid[1]; |
| 3139 | assign enc4_00[0] = used_and_valid[0] & (~used_and_valid[1] | used_and_valid[2]); |
| 3140 | assign sel4_00_b = &used_and_valid[3:0]; |
| 3141 | |
| 3142 | assign enc4_01[1] = used_and_valid[4] & used_and_valid[5]; |
| 3143 | assign enc4_01[0] = used_and_valid[4] & (~used_and_valid[5] | used_and_valid[6]); |
| 3144 | assign sel4_01_b = &used_and_valid[7:4]; |
| 3145 | |
| 3146 | assign enc4_02[1] = used_and_valid[8] & used_and_valid[9]; |
| 3147 | assign enc4_02[0] = used_and_valid[8] & (~used_and_valid[9] | used_and_valid[10]); |
| 3148 | assign sel4_02_b = &used_and_valid[11:8]; |
| 3149 | |
| 3150 | assign enc4_03[1] = used_and_valid[12] & used_and_valid[13]; |
| 3151 | assign enc4_03[0] = used_and_valid[12] & (~used_and_valid[13] | used_and_valid[14]); |
| 3152 | assign sel4_03_b = &used_and_valid[15:12]; |
| 3153 | |
| 3154 | assign enc4_04[1] = used_and_valid[16] & used_and_valid[17]; |
| 3155 | assign enc4_04[0] = used_and_valid[16] & (~used_and_valid[17] | used_and_valid[18]); |
| 3156 | assign sel4_04_b = &used_and_valid[19:16]; |
| 3157 | |
| 3158 | assign enc4_05[1] = used_and_valid[20] & used_and_valid[21]; |
| 3159 | assign enc4_05[0] = used_and_valid[20] & (~used_and_valid[21] | used_and_valid[22]); |
| 3160 | assign sel4_05_b = &used_and_valid[23:20]; |
| 3161 | |
| 3162 | assign enc4_06[1] = used_and_valid[24] & used_and_valid[25]; |
| 3163 | assign enc4_06[0] = used_and_valid[24] & (~used_and_valid[25] | used_and_valid[26]); |
| 3164 | assign sel4_06_b = &used_and_valid[27:24]; |
| 3165 | |
| 3166 | assign enc4_07[1] = used_and_valid[28] & used_and_valid[29]; |
| 3167 | assign enc4_07[0] = used_and_valid[28] & (~used_and_valid[29] | used_and_valid[30]); |
| 3168 | assign sel4_07_b = &used_and_valid[31:28]; |
| 3169 | |
| 3170 | assign enc4_08[1] = used_and_valid[32] & used_and_valid[33]; |
| 3171 | assign enc4_08[0] = used_and_valid[32] & (~used_and_valid[33] | used_and_valid[34]); |
| 3172 | assign sel4_08_b = &used_and_valid[35:32]; |
| 3173 | |
| 3174 | assign enc4_09[1] = used_and_valid[36] & used_and_valid[37]; |
| 3175 | assign enc4_09[0] = used_and_valid[36] & (~used_and_valid[37] | used_and_valid[38]); |
| 3176 | assign sel4_09_b = &used_and_valid[39:36]; |
| 3177 | |
| 3178 | assign enc4_10[1] = used_and_valid[40] & used_and_valid[41]; |
| 3179 | assign enc4_10[0] = used_and_valid[40] & (~used_and_valid[41] | used_and_valid[42]); |
| 3180 | assign sel4_10_b = &used_and_valid[43:40]; |
| 3181 | |
| 3182 | assign enc4_11[1] = used_and_valid[44] & used_and_valid[45]; |
| 3183 | assign enc4_11[0] = used_and_valid[44] & (~used_and_valid[45] | used_and_valid[46]); |
| 3184 | assign sel4_11_b = &used_and_valid[47:44]; |
| 3185 | |
| 3186 | assign enc4_12[1] = used_and_valid[48] & used_and_valid[49]; |
| 3187 | assign enc4_12[0] = used_and_valid[48] & (~used_and_valid[49] | used_and_valid[50]); |
| 3188 | assign sel4_12_b = &used_and_valid[51:48]; |
| 3189 | |
| 3190 | assign enc4_13[1] = used_and_valid[52] & used_and_valid[53]; |
| 3191 | assign enc4_13[0] = used_and_valid[52] & (~used_and_valid[53] | used_and_valid[54]); |
| 3192 | assign sel4_13_b = &used_and_valid[55:52]; |
| 3193 | |
| 3194 | assign enc4_14[1] = used_and_valid[56] & used_and_valid[57]; |
| 3195 | assign enc4_14[0] = used_and_valid[56] & (~used_and_valid[57] | used_and_valid[58]); |
| 3196 | assign sel4_14_b = &used_and_valid[59:56]; |
| 3197 | |
| 3198 | assign enc4_15[1] = used_and_valid[60] & used_and_valid[61]; |
| 3199 | assign enc4_15[0] = used_and_valid[60] & (~used_and_valid[61] | used_and_valid[62]); |
| 3200 | assign sel4_15_b = &used_and_valid[63:60]; |
| 3201 | |
| 3202 | assign enc4_16[1] = used_and_valid[64] & used_and_valid[65]; |
| 3203 | assign enc4_16[0] = used_and_valid[64] & (~used_and_valid[65] | used_and_valid[66]); |
| 3204 | assign sel4_16_b = &used_and_valid[67:64]; |
| 3205 | |
| 3206 | assign enc4_17[1] = used_and_valid[68] & used_and_valid[69]; |
| 3207 | assign enc4_17[0] = used_and_valid[68] & (~used_and_valid[69] | used_and_valid[70]); |
| 3208 | assign sel4_17_b = &used_and_valid[71:68]; |
| 3209 | |
| 3210 | assign enc4_18[1] = used_and_valid[72] & used_and_valid[73]; |
| 3211 | assign enc4_18[0] = used_and_valid[72] & (~used_and_valid[73] | used_and_valid[74]); |
| 3212 | assign sel4_18_b = &used_and_valid[75:72]; |
| 3213 | |
| 3214 | assign enc4_19[1] = used_and_valid[76] & used_and_valid[77]; |
| 3215 | assign enc4_19[0] = used_and_valid[76] & (~used_and_valid[77] | used_and_valid[78]); |
| 3216 | assign sel4_19_b = &used_and_valid[79:76]; |
| 3217 | |
| 3218 | assign enc4_20[1] = used_and_valid[80] & used_and_valid[81]; |
| 3219 | assign enc4_20[0] = used_and_valid[80] & (~used_and_valid[81] | used_and_valid[82]); |
| 3220 | assign sel4_20_b = &used_and_valid[83:80]; |
| 3221 | |
| 3222 | assign enc4_21[1] = used_and_valid[84] & used_and_valid[85]; |
| 3223 | assign enc4_21[0] = used_and_valid[84] & (~used_and_valid[85] | used_and_valid[86]); |
| 3224 | assign sel4_21_b = &used_and_valid[87:84]; |
| 3225 | |
| 3226 | assign enc4_22[1] = used_and_valid[88] & used_and_valid[89]; |
| 3227 | assign enc4_22[0] = used_and_valid[88] & (~used_and_valid[89] | used_and_valid[90]); |
| 3228 | assign sel4_22_b = &used_and_valid[91:88]; |
| 3229 | |
| 3230 | assign enc4_23[1] = used_and_valid[92] & used_and_valid[93]; |
| 3231 | assign enc4_23[0] = used_and_valid[92] & (~used_and_valid[93] | used_and_valid[94]); |
| 3232 | assign sel4_23_b = &used_and_valid[95:92]; |
| 3233 | |
| 3234 | assign enc4_24[1] = used_and_valid[96] & used_and_valid[97]; |
| 3235 | assign enc4_24[0] = used_and_valid[96] & (~used_and_valid[97] | used_and_valid[98]); |
| 3236 | assign sel4_24_b = &used_and_valid[99:96]; |
| 3237 | |
| 3238 | assign enc4_25[1] = used_and_valid[100] & used_and_valid[101]; |
| 3239 | assign enc4_25[0] = used_and_valid[100] & (~used_and_valid[101] | used_and_valid[102]); |
| 3240 | assign sel4_25_b = &used_and_valid[103:100]; |
| 3241 | |
| 3242 | assign enc4_26[1] = used_and_valid[104] & used_and_valid[105]; |
| 3243 | assign enc4_26[0] = used_and_valid[104] & (~used_and_valid[105] | used_and_valid[106]); |
| 3244 | assign sel4_26_b = &used_and_valid[107:104]; |
| 3245 | |
| 3246 | assign enc4_27[1] = used_and_valid[108] & used_and_valid[109]; |
| 3247 | assign enc4_27[0] = used_and_valid[108] & (~used_and_valid[109] | used_and_valid[110]); |
| 3248 | assign sel4_27_b = &used_and_valid[111:108]; |
| 3249 | |
| 3250 | assign enc4_28[1] = used_and_valid[112] & used_and_valid[113]; |
| 3251 | assign enc4_28[0] = used_and_valid[112] & (~used_and_valid[113] | used_and_valid[114]); |
| 3252 | assign sel4_28_b = &used_and_valid[115:112]; |
| 3253 | |
| 3254 | assign enc4_29[1] = used_and_valid[116] & used_and_valid[117]; |
| 3255 | assign enc4_29[0] = used_and_valid[116] & (~used_and_valid[117] | used_and_valid[118]); |
| 3256 | assign sel4_29_b = &used_and_valid[119:116]; |
| 3257 | |
| 3258 | assign enc4_30[1] = used_and_valid[120] & used_and_valid[121]; |
| 3259 | assign enc4_30[0] = used_and_valid[120] & (~used_and_valid[121] | used_and_valid[122]); |
| 3260 | assign sel4_30_b = &used_and_valid[123:120]; |
| 3261 | |
| 3262 | assign enc4_31[1] = used_and_valid[124] & used_and_valid[125]; |
| 3263 | assign enc4_31[0] = used_and_valid[124] & (~used_and_valid[125] | used_and_valid[126]); |
| 3264 | assign sel4_31_b = &used_and_valid[127:124]; |
| 3265 | |
| 3266 | |
| 3267 | // Now generate 8 bit group encodings |
| 3268 | assign enc8_00[2] = sel4_00_b; |
| 3269 | assign enc8_00[1:0] = (enc4_00[1:0] & {2 {~sel4_00_b}}) | (enc4_01[1:0] & {2 {sel4_00_b}}); |
| 3270 | assign sel8_00_b = sel4_00_b & sel4_01_b; |
| 3271 | |
| 3272 | assign enc8_01[2] = sel4_02_b; |
| 3273 | assign enc8_01[1:0] = (enc4_02[1:0] & {2 {~sel4_02_b}}) | (enc4_03[1:0] & {2 {sel4_02_b}}); |
| 3274 | assign sel8_01_b = sel4_02_b & sel4_03_b; |
| 3275 | |
| 3276 | assign enc8_02[2] = sel4_04_b; |
| 3277 | assign enc8_02[1:0] = (enc4_04[1:0] & {2 {~sel4_04_b}}) | (enc4_05[1:0] & {2 {sel4_04_b}}); |
| 3278 | assign sel8_02_b = sel4_04_b & sel4_05_b; |
| 3279 | |
| 3280 | assign enc8_03[2] = sel4_06_b; |
| 3281 | assign enc8_03[1:0] = (enc4_06[1:0] & {2 {~sel4_06_b}}) | (enc4_07[1:0] & {2 {sel4_06_b}}); |
| 3282 | assign sel8_03_b = sel4_06_b & sel4_07_b; |
| 3283 | |
| 3284 | assign enc8_04[2] = sel4_08_b; |
| 3285 | assign enc8_04[1:0] = (enc4_08[1:0] & {2 {~sel4_08_b}}) | (enc4_09[1:0] & {2 {sel4_08_b}}); |
| 3286 | assign sel8_04_b = sel4_08_b & sel4_09_b; |
| 3287 | |
| 3288 | assign enc8_05[2] = sel4_10_b; |
| 3289 | assign enc8_05[1:0] = (enc4_10[1:0] & {2 {~sel4_10_b}}) | (enc4_11[1:0] & {2 {sel4_10_b}}); |
| 3290 | assign sel8_05_b = sel4_10_b & sel4_11_b; |
| 3291 | |
| 3292 | assign enc8_06[2] = sel4_12_b; |
| 3293 | assign enc8_06[1:0] = (enc4_12[1:0] & {2 {~sel4_12_b}}) | (enc4_13[1:0] & {2 {sel4_12_b}}); |
| 3294 | assign sel8_06_b = sel4_12_b & sel4_13_b; |
| 3295 | |
| 3296 | assign enc8_07[2] = sel4_14_b; |
| 3297 | assign enc8_07[1:0] = (enc4_14[1:0] & {2 {~sel4_14_b}}) | (enc4_15[1:0] & {2 {sel4_14_b}}); |
| 3298 | assign sel8_07_b = sel4_14_b & sel4_15_b; |
| 3299 | |
| 3300 | assign enc8_08[2] = sel4_16_b; |
| 3301 | assign enc8_08[1:0] = (enc4_16[1:0] & {2 {~sel4_16_b}}) | (enc4_17[1:0] & {2 {sel4_16_b}}); |
| 3302 | assign sel8_08_b = sel4_16_b & sel4_17_b; |
| 3303 | |
| 3304 | assign enc8_09[2] = sel4_18_b; |
| 3305 | assign enc8_09[1:0] = (enc4_18[1:0] & {2 {~sel4_18_b}}) | (enc4_19[1:0] & {2 {sel4_18_b}}); |
| 3306 | assign sel8_09_b = sel4_18_b & sel4_19_b; |
| 3307 | |
| 3308 | assign enc8_10[2] = sel4_20_b; |
| 3309 | assign enc8_10[1:0] = (enc4_20[1:0] & {2 {~sel4_20_b}}) | (enc4_21[1:0] & {2 {sel4_20_b}}); |
| 3310 | assign sel8_10_b = sel4_20_b & sel4_21_b; |
| 3311 | |
| 3312 | assign enc8_11[2] = sel4_22_b; |
| 3313 | assign enc8_11[1:0] = (enc4_22[1:0] & {2 {~sel4_22_b}}) | (enc4_23[1:0] & {2 {sel4_22_b}}); |
| 3314 | assign sel8_11_b = sel4_22_b & sel4_23_b; |
| 3315 | |
| 3316 | assign enc8_12[2] = sel4_24_b; |
| 3317 | assign enc8_12[1:0] = (enc4_24[1:0] & {2 {~sel4_24_b}}) | (enc4_25[1:0] & {2 {sel4_24_b}}); |
| 3318 | assign sel8_12_b = sel4_24_b & sel4_25_b; |
| 3319 | |
| 3320 | assign enc8_13[2] = sel4_26_b; |
| 3321 | assign enc8_13[1:0] = (enc4_26[1:0] & {2 {~sel4_26_b}}) | (enc4_27[1:0] & {2 {sel4_26_b}}); |
| 3322 | assign sel8_13_b = sel4_26_b & sel4_27_b; |
| 3323 | |
| 3324 | assign enc8_14[2] = sel4_28_b; |
| 3325 | assign enc8_14[1:0] = (enc4_28[1:0] & {2 {~sel4_28_b}}) | (enc4_29[1:0] & {2 {sel4_28_b}}); |
| 3326 | assign sel8_14_b = sel4_28_b & sel4_29_b; |
| 3327 | |
| 3328 | assign enc8_15[2] = sel4_30_b; |
| 3329 | assign enc8_15[1:0] = (enc4_30[1:0] & {2 {~sel4_30_b}}) | (enc4_31[1:0] & {2 {sel4_30_b}}); |
| 3330 | assign sel8_15_b = sel4_30_b & sel4_31_b; |
| 3331 | |
| 3332 | |
| 3333 | // Now generate 16 bit group encodings |
| 3334 | assign enc16_0[3] = sel8_00_b; |
| 3335 | assign enc16_0[2:0] = (enc8_00[2:0] & {3 {~sel8_00_b}}) | (enc8_01[2:0] & {3 {sel8_00_b}}); |
| 3336 | assign sel16_0_b = sel8_00_b & sel8_01_b; |
| 3337 | |
| 3338 | assign enc16_1[3] = sel8_02_b; |
| 3339 | assign enc16_1[2:0] = (enc8_02[2:0] & {3 {~sel8_02_b}}) | (enc8_03[2:0] & {3 {sel8_02_b}}); |
| 3340 | assign sel16_1_b = sel8_02_b & sel8_03_b; |
| 3341 | |
| 3342 | assign enc16_2[3] = sel8_04_b; |
| 3343 | assign enc16_2[2:0] = (enc8_04[2:0] & {3 {~sel8_04_b}}) | (enc8_05[2:0] & {3 {sel8_04_b}}); |
| 3344 | assign sel16_2_b = sel8_04_b & sel8_05_b; |
| 3345 | |
| 3346 | assign enc16_3[3] = sel8_06_b; |
| 3347 | assign enc16_3[2:0] = (enc8_06[2:0] & {3 {~sel8_06_b}}) | (enc8_07[2:0] & {3 {sel8_06_b}}); |
| 3348 | assign sel16_3_b = sel8_06_b & sel8_07_b; |
| 3349 | |
| 3350 | assign enc16_4[3] = sel8_08_b; |
| 3351 | assign enc16_4[2:0] = (enc8_08[2:0] & {3 {~sel8_08_b}}) | (enc8_09[2:0] & {3 {sel8_08_b}}); |
| 3352 | assign sel16_4_b = sel8_08_b & sel8_09_b; |
| 3353 | |
| 3354 | assign enc16_5[3] = sel8_10_b; |
| 3355 | assign enc16_5[2:0] = (enc8_10[2:0] & {3 {~sel8_10_b}}) | (enc8_11[2:0] & {3 {sel8_10_b}}); |
| 3356 | assign sel16_5_b = sel8_10_b & sel8_11_b; |
| 3357 | |
| 3358 | assign enc16_6[3] = sel8_12_b; |
| 3359 | assign enc16_6[2:0] = (enc8_12[2:0] & {3 {~sel8_12_b}}) | (enc8_13[2:0] & {3 {sel8_12_b}}); |
| 3360 | assign sel16_6_b = sel8_12_b & sel8_13_b; |
| 3361 | |
| 3362 | assign enc16_7[3] = sel8_14_b; |
| 3363 | assign enc16_7[2:0] = (enc8_14[2:0] & {3 {~sel8_14_b}}) | (enc8_15[2:0] & {3 {sel8_14_b}}); |
| 3364 | assign sel16_7_b = sel8_14_b & sel8_15_b; |
| 3365 | |
| 3366 | |
| 3367 | // Now flop (nonscan) |
| 3368 | |
| 3369 | n2_tlb_tl_128x59_cust_msff_ctl_macro__width_40 enc16_lat ( |
| 3370 | .scan_in (1'b0), |
| 3371 | .scan_out (unused), |
| 3372 | .l1clk (l1clk), |
| 3373 | .siclk (1'b0), |
| 3374 | .soclk (1'b0), |
| 3375 | .din ({enc16_0[3:0], |
| 3376 | enc16_1[3:0], |
| 3377 | enc16_2[3:0], |
| 3378 | enc16_3[3:0], |
| 3379 | enc16_4[3:0], |
| 3380 | enc16_5[3:0], |
| 3381 | enc16_6[3:0], |
| 3382 | enc16_7[3:0], |
| 3383 | sel16_0_b, |
| 3384 | sel16_1_b, |
| 3385 | sel16_2_b, |
| 3386 | sel16_3_b, |
| 3387 | sel16_4_b, |
| 3388 | sel16_5_b, |
| 3389 | sel16_6_b, |
| 3390 | sel16_7_b}), |
| 3391 | .dout ({enc16_l_0[3:0], |
| 3392 | enc16_l_1[3:0], |
| 3393 | enc16_l_2[3:0], |
| 3394 | enc16_l_3[3:0], |
| 3395 | enc16_l_4[3:0], |
| 3396 | enc16_l_5[3:0], |
| 3397 | enc16_l_6[3:0], |
| 3398 | enc16_l_7[3:0], |
| 3399 | sel16_l_0_b, |
| 3400 | sel16_l_1_b, |
| 3401 | sel16_l_2_b, |
| 3402 | sel16_l_3_b, |
| 3403 | sel16_l_4_b, |
| 3404 | sel16_l_5_b, |
| 3405 | sel16_l_6_b, |
| 3406 | sel16_l_7_b_unused}) |
| 3407 | ); |
| 3408 | |
| 3409 | |
| 3410 | |
| 3411 | // Now generate 32 bit group encodings |
| 3412 | assign enc32_0[4] = sel16_l_0_b; |
| 3413 | assign enc32_0[3:0] = (enc16_l_0[3:0] & {4 {~sel16_l_0_b}}) | (enc16_l_1[3:0] & {4 {sel16_l_0_b}}); |
| 3414 | assign sel32_0_b = sel16_l_0_b & sel16_l_1_b; |
| 3415 | |
| 3416 | assign enc32_1[4] = sel16_l_2_b; |
| 3417 | assign enc32_1[3:0] = (enc16_l_2[3:0] & {4 {~sel16_l_2_b}}) | (enc16_l_3[3:0] & {4 {sel16_l_2_b}}); |
| 3418 | assign sel32_1_b = sel16_l_2_b & sel16_l_3_b; |
| 3419 | |
| 3420 | assign enc32_2[4] = sel16_l_4_b; |
| 3421 | assign enc32_2[3:0] = (enc16_l_4[3:0] & {4 {~sel16_l_4_b}}) | (enc16_l_5[3:0] & {4 {sel16_l_4_b}}); |
| 3422 | assign sel32_2_b = sel16_l_4_b & sel16_l_5_b; |
| 3423 | |
| 3424 | assign enc32_3[4] = sel16_l_6_b; |
| 3425 | assign enc32_3[3:0] = (enc16_l_6[3:0] & {4 {~sel16_l_6_b}}) | (enc16_l_7[3:0] & {4 {sel16_l_6_b}}); |
| 3426 | |
| 3427 | |
| 3428 | |
| 3429 | // Now generate 64 bit group encodings |
| 3430 | assign enc64_0[5] = sel32_0_b; |
| 3431 | assign enc64_0[4:0] = (enc32_0[4:0] & {5 {~sel32_0_b}}) | (enc32_1[4:0] & {5 {sel32_0_b}}); |
| 3432 | assign sel64_0_b = sel32_0_b & sel32_1_b; |
| 3433 | |
| 3434 | assign enc64_1[5] = sel32_2_b; |
| 3435 | assign enc64_1[4:0] = (enc32_2[4:0] & {5 {~sel32_2_b}}) | (enc32_3[4:0] & {5 {sel32_2_b}}); |
| 3436 | |
| 3437 | |
| 3438 | |
| 3439 | // Now generate 128 bit group encodings |
| 3440 | assign enc128_0[6] = sel64_0_b; |
| 3441 | assign enc128_0[5:0] = (enc64_0[5:0] & {6 {~sel64_0_b}}) | (enc64_1[5:0] & {6 {sel64_0_b}}); |
| 3442 | |
| 3443 | |
| 3444 | assign tlb_replacement_index[6:0] = enc128_0[6:0]; |
| 3445 | |
| 3446 | |
| 3447 | supply0 vss; // <- port for ground |
| 3448 | supply1 vdd; // <- port for power |
| 3449 | endmodule |
| 3450 | |
| 3451 | |
| 3452 | |
| 3453 | |
| 3454 | |
| 3455 | |
| 3456 | // any PARAMS parms go into naming of macro |
| 3457 | |
| 3458 | module n2_tlb_tl_128x59_cust_msff_ctl_macro__width_40 ( |
| 3459 | din, |
| 3460 | l1clk, |
| 3461 | scan_in, |
| 3462 | siclk, |
| 3463 | soclk, |
| 3464 | dout, |
| 3465 | scan_out); |
| 3466 | wire [39:0] fdin; |
| 3467 | wire [38:0] so; |
| 3468 | |
| 3469 | input [39:0] din; |
| 3470 | input l1clk; |
| 3471 | input scan_in; |
| 3472 | |
| 3473 | |
| 3474 | input siclk; |
| 3475 | input soclk; |
| 3476 | |
| 3477 | output [39:0] dout; |
| 3478 | output scan_out; |
| 3479 | assign fdin[39:0] = din[39:0]; |
| 3480 | |
| 3481 | |
| 3482 | |
| 3483 | |
| 3484 | |
| 3485 | |
| 3486 | dff #(40) d0_0 ( |
| 3487 | .l1clk(l1clk), |
| 3488 | .siclk(siclk), |
| 3489 | .soclk(soclk), |
| 3490 | .d(fdin[39:0]), |
| 3491 | .si({scan_in,so[38:0]}), |
| 3492 | .so({so[38:0],scan_out}), |
| 3493 | .q(dout[39:0]) |
| 3494 | ); |
| 3495 | |
| 3496 | |
| 3497 | |
| 3498 | |
| 3499 | |
| 3500 | |
| 3501 | |
| 3502 | |
| 3503 | |
| 3504 | |
| 3505 | |
| 3506 | |
| 3507 | endmodule |
| 3508 | |
| 3509 | |
| 3510 | |
| 3511 | |
| 3512 | |
| 3513 | |
| 3514 | |
| 3515 | |
| 3516 | |
| 3517 | // |
| 3518 | // invert macro |
| 3519 | // |
| 3520 | // |
| 3521 | |
| 3522 | |
| 3523 | |
| 3524 | |
| 3525 | |
| 3526 | module n2_tlb_tl_128x59_cust_inv_macro__width_27 ( |
| 3527 | din, |
| 3528 | dout); |
| 3529 | input [26:0] din; |
| 3530 | output [26:0] dout; |
| 3531 | |
| 3532 | |
| 3533 | |
| 3534 | |
| 3535 | |
| 3536 | |
| 3537 | inv #(27) d0_0 ( |
| 3538 | .in(din[26:0]), |
| 3539 | .out(dout[26:0]) |
| 3540 | ); |
| 3541 | |
| 3542 | |
| 3543 | |
| 3544 | |
| 3545 | |
| 3546 | |
| 3547 | |
| 3548 | |
| 3549 | |
| 3550 | endmodule |
| 3551 | |
| 3552 | |
| 3553 | |
| 3554 | |
| 3555 | |
| 3556 | |
| 3557 | |
| 3558 | |
| 3559 | |
| 3560 | // any PARAMS parms go into naming of macro |
| 3561 | |
| 3562 | module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_27 ( |
| 3563 | din, |
| 3564 | l1clk, |
| 3565 | scan_in, |
| 3566 | siclk, |
| 3567 | soclk, |
| 3568 | dout, |
| 3569 | scan_out); |
| 3570 | wire [26:0] fdin; |
| 3571 | |
| 3572 | input [26:0] din; |
| 3573 | input l1clk; |
| 3574 | input [26:0] scan_in; |
| 3575 | |
| 3576 | |
| 3577 | input siclk; |
| 3578 | input soclk; |
| 3579 | |
| 3580 | output [26:0] dout; |
| 3581 | output [26:0] scan_out; |
| 3582 | assign fdin[26:0] = din[26:0]; |
| 3583 | |
| 3584 | |
| 3585 | |
| 3586 | |
| 3587 | |
| 3588 | |
| 3589 | dff #(27) d0_0 ( |
| 3590 | .l1clk(l1clk), |
| 3591 | .siclk(siclk), |
| 3592 | .soclk(soclk), |
| 3593 | .d(fdin[26:0]), |
| 3594 | .si(scan_in[26:0]), |
| 3595 | .so(scan_out[26:0]), |
| 3596 | .q(dout[26:0]) |
| 3597 | ); |
| 3598 | |
| 3599 | |
| 3600 | |
| 3601 | |
| 3602 | |
| 3603 | |
| 3604 | |
| 3605 | |
| 3606 | |
| 3607 | |
| 3608 | |
| 3609 | |
| 3610 | endmodule |
| 3611 | |
| 3612 | |
| 3613 | |
| 3614 | |
| 3615 | |
| 3616 | |
| 3617 | |
| 3618 | |
| 3619 | |
| 3620 | // |
| 3621 | // invert macro |
| 3622 | // |
| 3623 | // |
| 3624 | |
| 3625 | |
| 3626 | |
| 3627 | |
| 3628 | |
| 3629 | module n2_tlb_tl_128x59_cust_inv_macro__stack_66c__width_66 ( |
| 3630 | din, |
| 3631 | dout); |
| 3632 | input [65:0] din; |
| 3633 | output [65:0] dout; |
| 3634 | |
| 3635 | |
| 3636 | |
| 3637 | |
| 3638 | |
| 3639 | |
| 3640 | inv #(66) d0_0 ( |
| 3641 | .in(din[65:0]), |
| 3642 | .out(dout[65:0]) |
| 3643 | ); |
| 3644 | |
| 3645 | |
| 3646 | |
| 3647 | |
| 3648 | |
| 3649 | |
| 3650 | |
| 3651 | |
| 3652 | |
| 3653 | endmodule |
| 3654 | |
| 3655 | |
| 3656 | |
| 3657 | |
| 3658 | |
| 3659 | |
| 3660 | |
| 3661 | |
| 3662 | |
| 3663 | // any PARAMS parms go into naming of macro |
| 3664 | |
| 3665 | module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_66 ( |
| 3666 | din, |
| 3667 | l1clk, |
| 3668 | scan_in, |
| 3669 | siclk, |
| 3670 | soclk, |
| 3671 | dout, |
| 3672 | scan_out); |
| 3673 | wire [65:0] fdin; |
| 3674 | |
| 3675 | input [65:0] din; |
| 3676 | input l1clk; |
| 3677 | input [65:0] scan_in; |
| 3678 | |
| 3679 | |
| 3680 | input siclk; |
| 3681 | input soclk; |
| 3682 | |
| 3683 | output [65:0] dout; |
| 3684 | output [65:0] scan_out; |
| 3685 | assign fdin[65:0] = din[65:0]; |
| 3686 | |
| 3687 | |
| 3688 | |
| 3689 | |
| 3690 | |
| 3691 | |
| 3692 | dff #(66) d0_0 ( |
| 3693 | .l1clk(l1clk), |
| 3694 | .siclk(siclk), |
| 3695 | .soclk(soclk), |
| 3696 | .d(fdin[65:0]), |
| 3697 | .si(scan_in[65:0]), |
| 3698 | .so(scan_out[65:0]), |
| 3699 | .q(dout[65:0]) |
| 3700 | ); |
| 3701 | |
| 3702 | |
| 3703 | |
| 3704 | |
| 3705 | |
| 3706 | |
| 3707 | |
| 3708 | |
| 3709 | |
| 3710 | |
| 3711 | |
| 3712 | |
| 3713 | endmodule |
| 3714 | |
| 3715 | |
| 3716 | |
| 3717 | |
| 3718 | |
| 3719 | |
| 3720 | |
| 3721 | |
| 3722 | |
| 3723 | // |
| 3724 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) |
| 3725 | // |
| 3726 | // |
| 3727 | |
| 3728 | |
| 3729 | |
| 3730 | |
| 3731 | |
| 3732 | module n2_tlb_tl_128x59_cust_cmp_macro__width_32 ( |
| 3733 | din0, |
| 3734 | din1, |
| 3735 | dout); |
| 3736 | input [31:0] din0; |
| 3737 | input [31:0] din1; |
| 3738 | output dout; |
| 3739 | |
| 3740 | |
| 3741 | |
| 3742 | |
| 3743 | |
| 3744 | |
| 3745 | cmp #(32) m0_0 ( |
| 3746 | .in0(din0[31:0]), |
| 3747 | .in1(din1[31:0]), |
| 3748 | .out(dout) |
| 3749 | ); |
| 3750 | |
| 3751 | |
| 3752 | |
| 3753 | |
| 3754 | |
| 3755 | |
| 3756 | |
| 3757 | |
| 3758 | |
| 3759 | |
| 3760 | endmodule |
| 3761 | |
| 3762 | |
| 3763 | |
| 3764 | |
| 3765 | |
| 3766 | // |
| 3767 | // invert macro |
| 3768 | // |
| 3769 | // |
| 3770 | |
| 3771 | |
| 3772 | |
| 3773 | |
| 3774 | |
| 3775 | module n2_tlb_tl_128x59_cust_inv_macro__width_4 ( |
| 3776 | din, |
| 3777 | dout); |
| 3778 | input [3:0] din; |
| 3779 | output [3:0] dout; |
| 3780 | |
| 3781 | |
| 3782 | |
| 3783 | |
| 3784 | |
| 3785 | |
| 3786 | inv #(4) d0_0 ( |
| 3787 | .in(din[3:0]), |
| 3788 | .out(dout[3:0]) |
| 3789 | ); |
| 3790 | |
| 3791 | |
| 3792 | |
| 3793 | |
| 3794 | |
| 3795 | |
| 3796 | |
| 3797 | |
| 3798 | |
| 3799 | endmodule |
| 3800 | |
| 3801 | |
| 3802 | |
| 3803 | |
| 3804 | |
| 3805 | |
| 3806 | |
| 3807 | |
| 3808 | |
| 3809 | // any PARAMS parms go into naming of macro |
| 3810 | |
| 3811 | module n2_tlb_tl_128x59_cust_msff_ctl_macro__fs_1__width_4 ( |
| 3812 | din, |
| 3813 | l1clk, |
| 3814 | scan_in, |
| 3815 | siclk, |
| 3816 | soclk, |
| 3817 | dout, |
| 3818 | scan_out); |
| 3819 | wire [3:0] fdin; |
| 3820 | |
| 3821 | input [3:0] din; |
| 3822 | input l1clk; |
| 3823 | input [3:0] scan_in; |
| 3824 | |
| 3825 | |
| 3826 | input siclk; |
| 3827 | input soclk; |
| 3828 | |
| 3829 | output [3:0] dout; |
| 3830 | output [3:0] scan_out; |
| 3831 | assign fdin[3:0] = din[3:0]; |
| 3832 | |
| 3833 | |
| 3834 | |
| 3835 | |
| 3836 | |
| 3837 | |
| 3838 | dff #(4) d0_0 ( |
| 3839 | .l1clk(l1clk), |
| 3840 | .siclk(siclk), |
| 3841 | .soclk(soclk), |
| 3842 | .d(fdin[3:0]), |
| 3843 | .si(scan_in[3:0]), |
| 3844 | .so(scan_out[3:0]), |
| 3845 | .q(dout[3:0]) |
| 3846 | ); |
| 3847 | |
| 3848 | |
| 3849 | |
| 3850 | |
| 3851 | |
| 3852 | |
| 3853 | |
| 3854 | |
| 3855 | |
| 3856 | |
| 3857 | |
| 3858 | |
| 3859 | endmodule |
| 3860 | |
| 3861 | |
| 3862 | |
| 3863 | |
| 3864 | |
| 3865 | |
| 3866 | |
| 3867 | |
| 3868 | |
| 3869 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 3870 | // also for pass-gate with decoder |
| 3871 | |
| 3872 | |
| 3873 | |
| 3874 | |
| 3875 | |
| 3876 | // any PARAMS parms go into naming of macro |
| 3877 | |
| 3878 | module n2_tlb_tl_128x59_cust_mux_macro__mux_aonpe__ports_4__width_1 ( |
| 3879 | din0, |
| 3880 | sel0, |
| 3881 | din1, |
| 3882 | sel1, |
| 3883 | din2, |
| 3884 | sel2, |
| 3885 | din3, |
| 3886 | sel3, |
| 3887 | dout); |
| 3888 | wire buffout0; |
| 3889 | wire buffout1; |
| 3890 | wire buffout2; |
| 3891 | wire buffout3; |
| 3892 | |
| 3893 | input [0:0] din0; |
| 3894 | input sel0; |
| 3895 | input [0:0] din1; |
| 3896 | input sel1; |
| 3897 | input [0:0] din2; |
| 3898 | input sel2; |
| 3899 | input [0:0] din3; |
| 3900 | input sel3; |
| 3901 | output [0:0] dout; |
| 3902 | |
| 3903 | |
| 3904 | |
| 3905 | |
| 3906 | |
| 3907 | cl_dp1_muxbuff4_8x c0_0 ( |
| 3908 | .in0(sel0), |
| 3909 | .in1(sel1), |
| 3910 | .in2(sel2), |
| 3911 | .in3(sel3), |
| 3912 | .out0(buffout0), |
| 3913 | .out1(buffout1), |
| 3914 | .out2(buffout2), |
| 3915 | .out3(buffout3) |
| 3916 | ); |
| 3917 | mux4s #(1) d0_0 ( |
| 3918 | .sel0(buffout0), |
| 3919 | .sel1(buffout1), |
| 3920 | .sel2(buffout2), |
| 3921 | .sel3(buffout3), |
| 3922 | .in0(din0[0:0]), |
| 3923 | .in1(din1[0:0]), |
| 3924 | .in2(din2[0:0]), |
| 3925 | .in3(din3[0:0]), |
| 3926 | .dout(dout[0:0]) |
| 3927 | ); |
| 3928 | |
| 3929 | |
| 3930 | |
| 3931 | |
| 3932 | |
| 3933 | |
| 3934 | |
| 3935 | |
| 3936 | |
| 3937 | |
| 3938 | |
| 3939 | |
| 3940 | |
| 3941 | endmodule |
| 3942 | |
| 3943 | |
| 3944 | // |
| 3945 | // parity macro (even parity) |
| 3946 | // |
| 3947 | // |
| 3948 | |
| 3949 | |
| 3950 | |
| 3951 | |
| 3952 | |
| 3953 | module n2_tlb_tl_128x59_cust_prty_macro__width_32 ( |
| 3954 | din, |
| 3955 | dout); |
| 3956 | input [31:0] din; |
| 3957 | output dout; |
| 3958 | |
| 3959 | |
| 3960 | |
| 3961 | |
| 3962 | |
| 3963 | |
| 3964 | |
| 3965 | prty #(32) m0_0 ( |
| 3966 | .in(din[31:0]), |
| 3967 | .out(dout) |
| 3968 | ); |
| 3969 | |
| 3970 | |
| 3971 | |
| 3972 | |
| 3973 | |
| 3974 | |
| 3975 | |
| 3976 | |
| 3977 | |
| 3978 | |
| 3979 | endmodule |
| 3980 | |
| 3981 | |
| 3982 | |
| 3983 | |
| 3984 | |
| 3985 | // |
| 3986 | // parity macro (even parity) |
| 3987 | // |
| 3988 | // |
| 3989 | |
| 3990 | |
| 3991 | |
| 3992 | |
| 3993 | |
| 3994 | module n2_tlb_tl_128x59_cust_prty_macro__width_8 ( |
| 3995 | din, |
| 3996 | dout); |
| 3997 | input [7:0] din; |
| 3998 | output dout; |
| 3999 | |
| 4000 | |
| 4001 | |
| 4002 | |
| 4003 | |
| 4004 | |
| 4005 | |
| 4006 | prty #(8) m0_0 ( |
| 4007 | .in(din[7:0]), |
| 4008 | .out(dout) |
| 4009 | ); |
| 4010 | |
| 4011 | |
| 4012 | |
| 4013 | |
| 4014 | |
| 4015 | |
| 4016 | |
| 4017 | |
| 4018 | |
| 4019 | |
| 4020 | endmodule |
| 4021 | |
| 4022 | |
| 4023 | |
| 4024 | |