| 1 | |
| 2 | =============================================================================== |
| 3 | Installation Instructions for OpenSPARC T2 design and verification database |
| 4 | =============================================================================== |
| 5 | |
| 6 | 1. Download OpenSPARCT2.tar.bz2 file to your directory. |
| 7 | e.g. you downloaded this file to "/home/johndoe/OpenSPARCT2" directory. |
| 8 | |
| 9 | 2. Unzip downloaded file by using following command: |
| 10 | |
| 11 | % bunzip2 OpenSPARCT2.tar.bz2 |
| 12 | |
| 13 | This step will create OpenSPARCT2.tar file. |
| 14 | |
| 15 | 3. Extract files from tar file by using following command: |
| 16 | |
| 17 | % tar xvf OpenSPARCT2.tar |
| 18 | |
| 19 | 4. Setup environment variables by editing OpenSPARCT2.cshrc file. |
| 20 | |
| 21 | Please set the following variables in OpenSPARCT2.cshrc file so you can |
| 22 | source the file for setting them up at your terminal. |
| 23 | |
| 24 | (a) DV_ROOT Directory where you extracted the |
| 25 | OpenSPARCT2.tar file |
| 26 | (b) MODEL_DIR Directory where you will run your |
| 27 | simulations, you need create this |
| 28 | directory first before starting build and run |
| 29 | (c) CC_BIN Directory location for C compiler binaries |
| 30 | (e.g. cc, gcc, etc.) |
| 31 | (d) VCS_HOME Directory location for Synopsys VCS installation |
| 32 | (RTL simulator) |
| 33 | (e) VERA_HOME Directory location for Synopsys Vera installation |
| 34 | (verification suite) |
| 35 | (f) NOVAS_HOME Directory location for Novas Debussy/Verdi |
| 36 | installation (for linking waveform dumping PLI) |
| 37 | (g) NCV_HOME Directory location for Cadence NC-Verilog |
| 38 | installation (RTL simulator) |
| 39 | (h) SYN_HOME Directory location for Synopsys Design Compiler |
| 40 | installation. |
| 41 | (i) LM_LICENSE_FILE Specify all of the license files for the |
| 42 | aforementioned CAD tools. |
| 43 | |
| 44 | EDA Tools Requirements |
| 45 | ======================= |
| 46 | ----------------------------------------------------------------------------- |
| 47 | | T2 w/o IO SubSystem | T2 w/ IO SubSystem |
| 48 | | Solaris Linux | Solaris Linux |
| 49 | ----------------------------------------------------------------------------- |
| 50 | EDA Simulation | |
| 51 | =============== | |
| 52 | VCS | 2006.06-SP2-1 2006.06-4 | 2006.06-SP2-1 2006.06-4 |
| 53 | Vera | X-2005.12-1 X-2005.12-11| X-2005.12-1 X-2005.12-11 |
| 54 | NC Verilog | 6.11.s3 06.20-s006 | 6.11.s3 06.20-s006 |
| 55 | Debussy | 2008.04 2008.04 | 2008.04 2008.04 |
| 56 | Denali PureSpec | 3.2.053 -NA- | 3.2.053 -NA- |
| 57 | |
| 58 | Software Tools | |
| 59 | ============= | |
| 60 | C/C++ Compiler| gcc 3.3.2 gcc 3.3.2 | gcc 3.3.2 gcc 3.3.2 |
| 61 | |
| 62 | EDA Synthesis | |
| 63 | ============= | |
| 64 | Design Compiler |X2005.09 X2005.09 | X2005.09 X2005.09 |
| 65 | |
| 66 | FPGA Synthesis | |
| 67 | ============== | |
| 68 | Synplify Pro | Version 9.2 | |
| 69 | Xilinx ISE | 10.1.03 | |
| 70 | ----------------------------------------------------------------------------- |
| 71 | Note: The SOC component, PEU SystemC behaviroal model, uses SystemC 2.2 |
| 72 | which is a beta feature in VCS 2006.06. You will required to get |
| 73 | VCS beta licence key to compile this model. |
| 74 | |
| 75 | Exmple environment settings: |
| 76 | ============================ |
| 77 | |
| 78 | setenv DV_ROOT /home/johndoe/OpenSPARCT2 |
| 79 | setenv MODEL_DIR /home/johndoe/OpenSPARCT2/build |
| 80 | setenv CC_BIN /import/freetools/local/gcc/3.3.2 |
| 81 | setenv VCS_HOME /import/EDAtools/vcs/vcs7.1.3 |
| 82 | setenv VERA_HOME /import/EDAtools/vera/vera,v6.3.10/5.x |
| 83 | setenv NOVAS_HOME /import/EDAtools/debussy/debussy,v5.4v9/5.x |
| 84 | setenv DENALI /import/EDAtools/denali/v3.2.053_32bit |
| 85 | setenv NCV_HOME /import/EDAtools/ncverilog/ncverilog,v6.11.s3/5.x |
| 86 | setenv SYN_HOME /import/EDAtools/synopsys/synopsys.vX-2005.09 |
| 87 | setenv SYNP_HOME /import/EDAtools/linux/synplicity/synplify.v9.2/fpga_92 |
| 88 | setenv XILINX_HOME /import/EDAtools/pkgs/xilinx/xilinx.vm10.1/ISE |
| 89 | setenv LM_LICENSE_FILE /import/EDAtools/licenses/keys/synopsys/synopsys_key:/import/EDAtools/licenses/keys/cadence/cadence_key:/import/EDAtools/licenses/keys/novas/novas_key |
| 90 | |
| 91 | |
| 92 | NOTE - In the 1.0 release of the OpenSPARC T2, the only supported RTL simulator |
| 93 | was Synopsys VCS version 7.1.3 or later. Also note that the Vera |
| 94 | verification platform from Synopsys was also required for simulations |
| 95 | to work. |
| 96 | |
| 97 | In the version 1.1, you can also invoke NC-Verilog as the RTL simulator, |
| 98 | but Vera (from Synopsys) will still be required to run all of the |
| 99 | verification, coverage and checker related aspects within the design. |
| 100 | |
| 101 | |
| 102 | 5. After you have set all of the environment variables as above, source the file at |
| 103 | your terminal prompt by using following command : |
| 104 | |
| 105 | % source OpenSPARCT2.cshrc |
| 106 | |
| 107 | |
| 108 | 6. The OpenSPARC T2 Design/Verification package now comes with following different |
| 109 | environments: |
| 110 | ------------------------------------------------------------------------- |
| 111 | Environment | Platform Supported |
| 112 | | Solaris Linux |
| 113 | | VCS NCVerilog VCS NCVerilog |
| 114 | ------------------------------------------------------------------------- |
| 115 | cmp1 | Y Y Y Y |
| 116 | cmp8 | Y Y Y Y |
| 117 | fc1 (default no NIU and PEU) | Y Y Y Y |
| 118 | fc8 (default no NIU and PEU) | Y Y Y Y |
| 119 | fc1 (PEU SystemC & NIU RTL) | Y N N N |
| 120 | fc8 (PEU SystemC & NIU RTL) | Y N N N |
| 121 | fc1 (PEU SystemC & NIU SystemC)| Y N N N |
| 122 | fc8 (PEU SystemC & NIU SystemC)| Y N N N |
| 123 | fpga_1c8t (fpga system model) | Y N N N |
| 124 | ------------------------------------------------------------------------- |
| 125 | |
| 126 | Note : a. SystemC models are fully behavioral level models. |
| 127 | b. NIU SystemC behavioral model code is based upon the NIU SAM code. |
| 128 | The NIU SAM library is located at $DV_ROOT/verif/model/systemc/niu/n2niu.so |
| 129 | c. For more details on synthesizable system-level model for FPGA, |
| 130 | please see README_FPGA file. |
| 131 | |
| 132 | |
| 133 | (i) The cmp1 environment consists of one SPARC CPU core, crossbar, Level 2 cache. |
| 134 | Does not include memory controller unit, or any of the on-chip I/O sub-systems. |
| 135 | It means you can run upto 8 threads in this model. |
| 136 | |
| 137 | (ii) The cmp8 environment consists of 8 SPARC CPU cores, crossbar, Level 2 cache. |
| 138 | Does not include memory controller unit, or any of the on-chip I/O sub-systems. |
| 139 | It means you can run all 64 threads in this model. |
| 140 | |
| 141 | (iii) The fc1 environment consists of one SPARC CPU core, crossbar, Level 2 cache, |
| 142 | memory controller unit, and all of the on-chip I/O sub-systems, except PCI-Express. |
| 143 | You can run upto 8 threads in this model. |
| 144 | |
| 145 | (iv) The fc8 environment consists of the complete OpenSPARC T2 chip including |
| 146 | 8 SPARC CPU coress, crossbar, Level 2 cache, memory controller unit, and all of |
| 147 | the on-chip I/O sub-systems except PCI-Express. You can run all 64 threads in this |
| 148 | model. |
| 149 | |
| 150 | |
| 151 | Each of the above environments comes with the "mini" regression and "all" |
| 152 | regression suites. Mini regressions comprise of only a few tests for quick |
| 153 | validation, whereas all regressions, comprise of an extensive set of tests |
| 154 | targetted at verifying majority of the blocks making up the OpenSPARC T2 design. |
| 155 | |
| 156 | To run regressions, please use the 'sims' script. |
| 157 | 'Sims' is a perl-based utility that is used to set-up and run all of the |
| 158 | required underlying utilities and tools for a complete build and regression. |
| 159 | |
| 160 | |
| 161 | The 2 important sims command parameters to remember are : |
| 162 | (Note: 'sims' supports a whole bunch of commands, so please do a % sims -h |
| 163 | to get help on those options) |
| 164 | |
| 165 | |
| 166 | A. -sys : system environment type |
| 167 | |
| 168 | Please set this to either cmp1, cmp8, fc1 or fc8. |
| 169 | |
| 170 | For example: -sys=cmp1 |
| 171 | |
| 172 | |
| 173 | B. -group : Regression group |
| 174 | |
| 175 | There are 8 choices for regression suites: (for both VCS and NC-Verilog) |
| 176 | |
| 177 | ------------------------------------- |
| 178 | MINI ALL |
| 179 | -------------------------------------- |
| 180 | (i) mp1_mini_T2 cmp1_all_T2 |
| 181 | (ii) cmp8_mini_T2 cmp8_all_T2 |
| 182 | (iii) fc1_mini_T2 fc1_all_T2 |
| 183 | (iv) fc8_mini_T2 fc8_all_T2 |
| 184 | -------------------------------------- |
| 185 | |
| 186 | For example : -group=cmp1_mini_T2 |
| 187 | |
| 188 | |
| 189 | --------------------------------------- |
| 190 | |
| 191 | |
| 192 | Below are some examples for running regressions, note that the diags |
| 193 | (or functional tests) comprising a diaglist will by default be run sequentially, |
| 194 | 1-by-1. |
| 195 | |
| 196 | You will need to craft a mechanism at your end that allows you to distribute |
| 197 | the simulation runs across several CPUs so as to complete the regressions |
| 198 | faster by parallelly launching the simulation runs. |
| 199 | |
| 200 | If the script/wrapper that you have devised for sending a job to an available |
| 201 | CPU is called 'job_submit' (for example), then you only need to append the |
| 202 | following argument to 'sims' (in addition to all the ones mentioned above) |
| 203 | |
| 204 | -sim_q_command="job_submit ... ... ..." |
| 205 | |
| 206 | where "... ... ..." implies whatever arguments are needed to be supplied to your |
| 207 | script/wrapper for launching the job to a free avaliable CPU. |
| 208 | |
| 209 | |
| 210 | |
| 211 | Here are all of the 8 regression suites that are supported. By default, commands |
| 212 | are meant for running with VCS (Synopsys RTL simulator). If however, you wish to |
| 213 | run the OpenSparc T2 models using NC-Verilog (Cadence RTL simulator), then you just |
| 214 | need to append |
| 215 | |
| 216 | -sim=ncv |
| 217 | |
| 218 | to the rest of the arguments and that is it. |
| 219 | |
| 220 | |
| 221 | Note: when using NC-Verilog, you will also require Synopsys Vera to run most |
| 222 | of the verification related aspects within ncsim. It will not work otherwise. |
| 223 | |
| 224 | |
| 225 | |
| 226 | (1) To run mini regression for cmp1 environment, type |
| 227 | |
| 228 | % sims -sys=cmp1 -group=cmp1_mini_T2 |
| 229 | OR |
| 230 | % sims -sys=cmp1 -group=cmp1_mini_T2 -sim_q_command="job_submit ... ... ..." |
| 231 | (which is to be used only if you have devised the scheme for |
| 232 | parallelizing your runs) |
| 233 | |
| 234 | |
| 235 | |
| 236 | For NC-Verilog, the arguments would be |
| 237 | % sims -sys=cmp1 -group=cmp1_mini_T2 -sim=ncv |
| 238 | OR |
| 239 | % sims -sys=cmp1 -group=cmp1_mini_T2 -sim=ncv -sim_q_command="job_submit ... ..." |
| 240 | |
| 241 | |
| 242 | |
| 243 | (2) To run mini regression for cmp8 environment, type |
| 244 | |
| 245 | % sims -sys=cmp8 -group=cmp8_mini_T2 |
| 246 | OR |
| 247 | % sims -sys=cmp8 -group=cmp8_mini_T2 -sim=ncv (for NC-Verilog) |
| 248 | |
| 249 | |
| 250 | (3) To run mini regression for fc1 environment, type |
| 251 | |
| 252 | % sims -sys=fc1 -group=fc1_mini_T2 |
| 253 | OR |
| 254 | % sims -sys=fc1 -group=fc1_mini_T2 -sim=ncv (for NC-Verilog) |
| 255 | |
| 256 | |
| 257 | (4) To run mini regression for fc8 environment, type |
| 258 | |
| 259 | |
| 260 | % sims -sys=fc8 -group=fc8_mini_T2 |
| 261 | OR |
| 262 | % sims -sys=fc8 -group=fc8_mini_T2 -sim=ncv (for NC-Verilog) |
| 263 | |
| 264 | |
| 265 | |
| 266 | (5) To run full regression for cmp1 environment, type |
| 267 | |
| 268 | % sims -sys=cmp1 -group=cmp1_all_T2 |
| 269 | OR |
| 270 | % sims -sys=cmp1 -group=cmp1_all_T2 -sim=ncv (for NC-Verilog) |
| 271 | |
| 272 | |
| 273 | (6) To run full regression for cmp8 environment, type |
| 274 | |
| 275 | % sims -sys=cmp8 -group=cmp8_all_T2 |
| 276 | OR |
| 277 | % sims -sys=cmp8 -group=cmp8_all_T2 -sim=ncv (for NC-Verilog) |
| 278 | |
| 279 | |
| 280 | |
| 281 | (7) To run full regression for fc1 environment, type |
| 282 | |
| 283 | % sims -sys=fc1 -group=fc1_all_T2 |
| 284 | OR |
| 285 | % sims -sys=fc1 -group=fc1_all_T2 -sim=ncv (for NC-Verilog) |
| 286 | |
| 287 | |
| 288 | |
| 289 | (8) To run full regression for fc8 environment, type |
| 290 | |
| 291 | % sims -sys=fc8 -group=fc8_all_T2 |
| 292 | OR |
| 293 | % sims -sys=fc8 -group=fc8_all_T2 -sim=ncv (for NC-Verilog) |
| 294 | |
| 295 | |
| 296 | (9) To run full regression for fc1 environment, with NIU RTL and PIU SystemC model |
| 297 | |
| 298 | % sims -sys=fc1 -group=fc1_all_T2 -config_cpp_args=-DPEU_SYSC_NIU_RTL |
| 299 | |
| 300 | |
| 301 | (10) To run full regression for fc8 environment, with NIU RTL and PIU SystemC model |
| 302 | |
| 303 | % sims -sys=fc8 -group=fc8_all_T2 -config_cpp_args=-DPEU_SYSC_NIU_RTL |
| 304 | |
| 305 | (11) To run full regression for fc1 environment, with NIU and PIU SystemC model |
| 306 | |
| 307 | % sims -sys=fc1 -group=fc1_all_T2 -config_cpp_args=-DPEU_SYSC_NIU_SYSC |
| 308 | |
| 309 | |
| 310 | (12) To run full regression for fc8 environment, with NIU and PIU SystemC model |
| 311 | |
| 312 | % sims -sys=fc8 -group=fc8_all_T2 -config_cpp_args=-DPEU_SYSC_NIU_SYSC |
| 313 | |
| 314 | |
| 315 | ---------------------------------------- |
| 316 | |
| 317 | |
| 318 | *** If you already have a VCS or NC-Verilog model built and you want to |
| 319 | use that to run your regression, you can do the following, which can be |
| 320 | useful since you may not want to rebuild your simulation binaries or |
| 321 | snapshots all the time (from scratch). |
| 322 | |
| 323 | |
| 324 | |
| 325 | (i) using a VCS -built model |
| 326 | |
| 327 | % sims -sys=cmp1 -group=cmp1_mini_T2 -nobuild \ |
| 328 | -model_rel_name=vcs_build_2008_02_16_0 |
| 329 | |
| 330 | (to get the -model_rel_name=<...>, you simply look into the original |
| 331 | sims.log file under your $MODEL_DIR, search for the string |
| 332 | "-model_rel_name", and then parse it exactly as it appears) |
| 333 | |
| 334 | |
| 335 | (ii) using a NC-Verilog built model |
| 336 | |
| 337 | % sims -sys=cmp1 -group=cmp1_mini_T2 -sim=ncv -nobuild \ |
| 338 | -model_rel_name=ncv_build_2008_02_16_0 |
| 339 | |
| 340 | |
| 341 | If you wish to rerun a particular test using a simulation binary of your choice, |
| 342 | here is what you need to do. |
| 343 | |
| 344 | since you are rerunning, you obviously have the old 'sims.log' file for the |
| 345 | particular diag that you are trying to run. Once you go inside that run directory, |
| 346 | type the following command: |
| 347 | |
| 348 | % sims -rerun -model_rel_name=vcs_build_2008_02_16_0 (for VCS) |
| 349 | |
| 350 | OR |
| 351 | |
| 352 | % sims -rerun -sim=ncv -model_rel_name=ncv_build_2008_02_16_0 (for NC-Verilog) |
| 353 | |
| 354 | |
| 355 | This will then rerun the diag for you using the simulation binary that is |
| 356 | located inside the "-model_rel_name=<...>" directory that you have entered. |
| 357 | |
| 358 | |
| 359 | |
| 360 | To get help on "sims", simply type |
| 361 | |
| 362 | % sims -h |
| 363 | |
| 364 | |
| 365 | 7. Block level model building |
| 366 | |
| 367 | Every block of the OpenSPARC T2 comes with a relevant filelist that allows |
| 368 | users to compile the model for that particular block. You can execute a |
| 369 | simple simulator command to achieve that. For example, to build simulation |
| 370 | model for the "ccx" block, execute following command: |
| 371 | |
| 372 | cd $DV_ROOT/design/sys/iop/ccx |
| 373 | vcs -f ccx.flist -timescale=1ps/1ps +v2k |
| 374 | |
| 375 | Or to build full OpenSPARC T2 CPU model, type |
| 376 | |
| 377 | cd $DV_ROOT/design/sys/iop/cpu |
| 378 | vcs -f cpu.flist -timescale=1ps/1ps +v2k |
| 379 | |
| 380 | One can build verification test benches in addition to the ones provided |
| 381 | by this distribution at the block level. |
| 382 | |
| 383 | |
| 384 | 8. Synthesis |
| 385 | |
| 386 | Before attempting to run synthesis, please make sure you have SYN_HOME |
| 387 | environment variable pointing to Synopsys Design Compiler installation. |
| 388 | |
| 389 | Use "rsyn" script to run synthesis on control and datapath blocks of the |
| 390 | OpenSPARC T2 design. For example, to run synthesis on ccu block of the |
| 391 | OpenSPARC T2 design, type following command: |
| 392 | |
| 393 | rsyn ccu |
| 394 | |
| 395 | To run synthesis on all the control and datapath blocks of the chip, run |
| 396 | |
| 397 | rsyn -all |
| 398 | |
| 399 | For the usage of this command, simply type |
| 400 | |
| 401 | rsyn -h |
| 402 | |
| 403 | 9. FPGA Synthesis and Simulation |
| 404 | |
| 405 | A fully synthesizable, reduced footprint, System-level model has been |
| 406 | developed, suitable for FPGA and Emulation Platforms. |
| 407 | This model has CORE, CCX and WISHBONE Memory Controller (OpenCores). |
| 408 | This environment supports RTL Simulation, FPGA Synthesis and Gate- |
| 409 | level simulation with a one-to-one correspondence (i.e a given test |
| 410 | runs unchanged in the RTL & Gate environmentS. |
| 411 | |
| 412 | Please see more details in README_FPGA file in this dir. |
| 413 | |
| 414 | |
| 415 | |
| 416 | 10. Platforms |
| 417 | |
| 418 | With the release 1.1 of the OpenSPARC T2, both synthesis and simulation |
| 419 | environments are supported for following platforms |
| 420 | |
| 421 | - Solaris 9 running on SPARC |
| 422 | - Solaris 10 running on SPARC |
| 423 | - Red Hat Linux 2.6 and above running on x64 |
| 424 | |
| 425 | IMPORTANT - Full chip environment with PEU and NIU is currently unsupported on |
| 426 | Linux/x64 platform. It is only supported on the Solaris 9, and Solaris 10 running |
| 427 | on SPARC. |
| 428 | |
| 429 | |
| 430 | 11. Documents |
| 431 | |
| 432 | Following documents (.pdf format) are available under 'doc' directory : |
| 433 | |
| 434 | OpenSPARC T2 Core Micro-Architecture Specification |
| 435 | OpenSPARC T2 SoC Micro-Architecture Specification |
| 436 | |
| 437 | |
| 438 | |