| 1 | ////////////////////////////////////////////////////////////////////// |
| 2 | //// //// |
| 3 | //// uart_top.v //// |
| 4 | //// //// |
| 5 | //// //// |
| 6 | //// This file is part of the "UART 16550 compatible" project //// |
| 7 | //// http://www.opencores.org/cores/uart16550/ //// |
| 8 | //// //// |
| 9 | //// Documentation related to this project: //// |
| 10 | //// - http://www.opencores.org/cores/uart16550/ //// |
| 11 | //// //// |
| 12 | //// Projects compatibility: //// |
| 13 | //// - WISHBONE //// |
| 14 | //// RS232 Protocol //// |
| 15 | //// 16550D uart (mostly supported) //// |
| 16 | //// //// |
| 17 | //// Overview (main Features): //// |
| 18 | //// UART core top level. //// |
| 19 | //// //// |
| 20 | //// Known problems (limits): //// |
| 21 | //// Note that transmitter and receiver instances are inside //// |
| 22 | //// the uart_regs.v file. //// |
| 23 | //// //// |
| 24 | //// To Do: //// |
| 25 | //// Nothing so far. //// |
| 26 | //// //// |
| 27 | //// Author(s): //// |
| 28 | //// - gorban@opencores.org //// |
| 29 | //// - Jacob Gorban //// |
| 30 | //// - Igor Mohor (igorm@opencores.org) //// |
| 31 | //// //// |
| 32 | //// Created: 2001/05/12 //// |
| 33 | //// Last Updated: 2001/05/17 //// |
| 34 | //// (See log for the revision history) //// |
| 35 | //// //// |
| 36 | //// //// |
| 37 | ////////////////////////////////////////////////////////////////////// |
| 38 | //// //// |
| 39 | //// Copyright (C) 2000, 2001 Authors //// |
| 40 | //// //// |
| 41 | //// This source file may be used and distributed without //// |
| 42 | //// restriction provided that this copyright statement is not //// |
| 43 | //// removed from the file and that any derivative work contains //// |
| 44 | //// the original copyright notice and the associated disclaimer. //// |
| 45 | //// //// |
| 46 | //// This source file is free software; you can redistribute it //// |
| 47 | //// and/or modify it under the terms of the GNU Lesser General //// |
| 48 | //// Public License as published by the Free Software Foundation; //// |
| 49 | //// either version 2.1 of the License, or (at your option) any //// |
| 50 | //// later version. //// |
| 51 | //// //// |
| 52 | //// This source is distributed in the hope that it will be //// |
| 53 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
| 54 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
| 55 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
| 56 | //// details. //// |
| 57 | //// //// |
| 58 | //// You should have received a copy of the GNU Lesser General //// |
| 59 | //// Public License along with this source; if not, download it //// |
| 60 | //// from http://www.opencores.org/lgpl.shtml //// |
| 61 | //// //// |
| 62 | ////////////////////////////////////////////////////////////////////// |
| 63 | // |
| 64 | // CVS Revision History |
| 65 | // |
| 66 | // $Log: uart_top.v,v $ |
| 67 | // Revision 1.19 2002/07/29 21:16:18 gorban |
| 68 | // The uart_defines.v file is included again in sources. |
| 69 | // |
| 70 | // Revision 1.18 2002/07/22 23:02:23 gorban |
| 71 | // Bug Fixes: |
| 72 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
| 73 | // Problem reported by Kenny.Tung. |
| 74 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
| 75 | // |
| 76 | // Improvements: |
| 77 | // * Made FIFO's as general inferrable memory where possible. |
| 78 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
| 79 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
| 80 | // |
| 81 | // * Added optional baudrate output (baud_o). |
| 82 | // This is identical to BAUDOUT* signal on 16550 chip. |
| 83 | // It outputs 16xbit_clock_rate - the divided clock. |
| 84 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
| 85 | // |
| 86 | // Revision 1.17 2001/12/19 08:40:03 mohor |
| 87 | // Warnings fixed (unused signals removed). |
| 88 | // |
| 89 | // Revision 1.16 2001/12/06 14:51:04 gorban |
| 90 | // Bug in LSR[0] is fixed. |
| 91 | // All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. |
| 92 | // |
| 93 | // Revision 1.15 2001/12/03 21:44:29 gorban |
| 94 | // Updated specification documentation. |
| 95 | // Added full 32-bit data bus interface, now as default. |
| 96 | // Address is 5-bit wide in 32-bit data bus mode. |
| 97 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. |
| 98 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. |
| 99 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. |
| 100 | // My small test bench is modified to work with 32-bit mode. |
| 101 | // |
| 102 | // Revision 1.14 2001/11/07 17:51:52 gorban |
| 103 | // Heavily rewritten interrupt and LSR subsystems. |
| 104 | // Many bugs hopefully squashed. |
| 105 | // |
| 106 | // Revision 1.13 2001/10/20 09:58:40 gorban |
| 107 | // Small synopsis fixes |
| 108 | // |
| 109 | // Revision 1.12 2001/08/25 15:46:19 gorban |
| 110 | // Modified port names again |
| 111 | // |
| 112 | // Revision 1.11 2001/08/24 21:01:12 mohor |
| 113 | // Things connected to parity changed. |
| 114 | // Clock devider changed. |
| 115 | // |
| 116 | // Revision 1.10 2001/08/23 16:05:05 mohor |
| 117 | // Stop bit bug fixed. |
| 118 | // Parity bug fixed. |
| 119 | // WISHBONE read cycle bug fixed, |
| 120 | // OE indicator (Overrun Error) bug fixed. |
| 121 | // PE indicator (Parity Error) bug fixed. |
| 122 | // Register read bug fixed. |
| 123 | // |
| 124 | // Revision 1.4 2001/05/31 20:08:01 gorban |
| 125 | // FIFO changes and other corrections. |
| 126 | // |
| 127 | // Revision 1.3 2001/05/21 19:12:02 gorban |
| 128 | // Corrected some Linter messages. |
| 129 | // |
| 130 | // Revision 1.2 2001/05/17 18:34:18 gorban |
| 131 | // First 'stable' release. Should be sythesizable now. Also added new header. |
| 132 | // |
| 133 | // Revision 1.0 2001-05-17 21:27:12+02 jacob |
| 134 | // Initial revision |
| 135 | // |
| 136 | // |
| 137 | |
| 138 | `timescale 1 ns / 10 ps |
| 139 | module uart_top(wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, |
| 140 | wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i, int_o, stx_pad_o, srx_pad_i, |
| 141 | rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i, baud_o) |
| 142 | ; |
| 143 | |
| 144 | parameter uart_data_width = 8; |
| 145 | parameter uart_addr_width = 3; |
| 146 | |
| 147 | input wb_clk_i; |
| 148 | input wb_rst_i; |
| 149 | input [(uart_addr_width - 1):0] |
| 150 | wb_adr_i; |
| 151 | input [(uart_data_width - 1):0] |
| 152 | wb_dat_i; |
| 153 | output [(uart_data_width - 1):0] |
| 154 | wb_dat_o; |
| 155 | input wb_we_i; |
| 156 | input wb_stb_i; |
| 157 | input wb_cyc_i; |
| 158 | input [3:0] wb_sel_i; |
| 159 | output wb_ack_o; |
| 160 | output int_o; |
| 161 | input srx_pad_i; |
| 162 | output stx_pad_o; |
| 163 | output rts_pad_o; |
| 164 | input cts_pad_i; |
| 165 | output dtr_pad_o; |
| 166 | input dsr_pad_i; |
| 167 | input ri_pad_i; |
| 168 | input dcd_pad_i; |
| 169 | output baud_o; |
| 170 | |
| 171 | wire [7:0] wb_dat8_i; |
| 172 | wire [7:0] wb_dat8_o; |
| 173 | wire [31:0] wb_dat32_o; |
| 174 | wire [(uart_addr_width - 1):0] |
| 175 | wb_adr_int; |
| 176 | wire we_o; |
| 177 | wire re_o; |
| 178 | |
| 179 | uart_wb wb_interface( |
| 180 | .clk (wb_clk_i), |
| 181 | .wb_rst_i (wb_rst_i), |
| 182 | .wb_dat_i (wb_dat_i), |
| 183 | .wb_dat_o (wb_dat_o), |
| 184 | .wb_dat8_i (wb_dat8_i), |
| 185 | .wb_dat8_o (wb_dat8_o), |
| 186 | .wb_dat32_o (32'b0), |
| 187 | .wb_sel_i (4'b0), |
| 188 | .wb_we_i (wb_we_i), |
| 189 | .wb_stb_i (wb_stb_i), |
| 190 | .wb_cyc_i (wb_cyc_i), |
| 191 | .wb_ack_o (wb_ack_o), |
| 192 | .wb_adr_i (wb_adr_i), |
| 193 | .wb_adr_int (wb_adr_int), |
| 194 | .we_o (we_o), |
| 195 | .re_o (re_o)); |
| 196 | uart_regs regs( |
| 197 | .clk (wb_clk_i), |
| 198 | .wb_rst_i (wb_rst_i), |
| 199 | .wb_addr_i (wb_adr_int), |
| 200 | .wb_dat_i (wb_dat8_i), |
| 201 | .wb_dat_o (wb_dat8_o), |
| 202 | .wb_we_i (we_o), |
| 203 | .wb_re_i (re_o), |
| 204 | .modem_inputs ({cts_pad_i, dsr_pad_i, |
| 205 | ri_pad_i, dcd_pad_i}), |
| 206 | .stx_pad_o (stx_pad_o), |
| 207 | .srx_pad_i (srx_pad_i), |
| 208 | .rts_pad_o (rts_pad_o), |
| 209 | .dtr_pad_o (dtr_pad_o), |
| 210 | .int_o (int_o), |
| 211 | .baud_o (baud_o)); |
| 212 | |
| 213 | initial begin |
| 214 | $display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n") |
| 215 | ; |
| 216 | $display("(%m) UART INFO: Has baudrate output\n"); |
| 217 | end |
| 218 | endmodule |