| 1 | ////////////////////////////////////////////////////////////////////// |
| 2 | //// //// |
| 3 | //// uart_wb.v //// |
| 4 | //// //// |
| 5 | //// //// |
| 6 | //// This file is part of the "UART 16550 compatible" project //// |
| 7 | //// http://www.opencores.org/cores/uart16550/ //// |
| 8 | //// //// |
| 9 | //// Documentation related to this project: //// |
| 10 | //// - http://www.opencores.org/cores/uart16550/ //// |
| 11 | //// //// |
| 12 | //// Projects compatibility: //// |
| 13 | //// - WISHBONE //// |
| 14 | //// RS232 Protocol //// |
| 15 | //// 16550D uart (mostly supported) //// |
| 16 | //// //// |
| 17 | //// Overview (main Features): //// |
| 18 | //// UART core WISHBONE interface. //// |
| 19 | //// //// |
| 20 | //// Known problems (limits): //// |
| 21 | //// Inserts one wait state on all transfers. //// |
| 22 | //// Note affected signals and the way they are affected. //// |
| 23 | //// //// |
| 24 | //// To Do: //// |
| 25 | //// Nothing. //// |
| 26 | //// //// |
| 27 | //// Author(s): //// |
| 28 | //// - gorban@opencores.org //// |
| 29 | //// - Jacob Gorban //// |
| 30 | //// - Igor Mohor (igorm@opencores.org) //// |
| 31 | //// //// |
| 32 | //// Created: 2001/05/12 //// |
| 33 | //// Last Updated: 2001/05/17 //// |
| 34 | //// (See log for the revision history) //// |
| 35 | //// //// |
| 36 | //// //// |
| 37 | ////////////////////////////////////////////////////////////////////// |
| 38 | //// //// |
| 39 | //// Copyright (C) 2000, 2001 Authors //// |
| 40 | //// //// |
| 41 | //// This source file may be used and distributed without //// |
| 42 | //// restriction provided that this copyright statement is not //// |
| 43 | //// removed from the file and that any derivative work contains //// |
| 44 | //// the original copyright notice and the associated disclaimer. //// |
| 45 | //// //// |
| 46 | //// This source file is free software; you can redistribute it //// |
| 47 | //// and/or modify it under the terms of the GNU Lesser General //// |
| 48 | //// Public License as published by the Free Software Foundation; //// |
| 49 | //// either version 2.1 of the License, or (at your option) any //// |
| 50 | //// later version. //// |
| 51 | //// //// |
| 52 | //// This source is distributed in the hope that it will be //// |
| 53 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
| 54 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
| 55 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
| 56 | //// details. //// |
| 57 | //// //// |
| 58 | //// You should have received a copy of the GNU Lesser General //// |
| 59 | //// Public License along with this source; if not, download it //// |
| 60 | //// from http://www.opencores.org/lgpl.shtml //// |
| 61 | //// //// |
| 62 | ////////////////////////////////////////////////////////////////////// |
| 63 | // |
| 64 | // CVS Revision History |
| 65 | // |
| 66 | // $Log: uart_wb.v,v $ |
| 67 | // Revision 1.17 2004/05/21 12:35:15 tadejm |
| 68 | // Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode. |
| 69 | // |
| 70 | // Revision 1.16 2002/07/29 21:16:18 gorban |
| 71 | // The uart_defines.v file is included again in sources. |
| 72 | // |
| 73 | // Revision 1.15 2002/07/22 23:02:23 gorban |
| 74 | // Bug Fixes: |
| 75 | // * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. |
| 76 | // Problem reported by Kenny.Tung. |
| 77 | // * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. |
| 78 | // |
| 79 | // Improvements: |
| 80 | // * Made FIFO's as general inferrable memory where possible. |
| 81 | // So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). |
| 82 | // This saves about 1/3 of the Slice count and reduces P&R and synthesis times. |
| 83 | // |
| 84 | // * Added optional baudrate output (baud_o). |
| 85 | // This is identical to BAUDOUT* signal on 16550 chip. |
| 86 | // It outputs 16xbit_clock_rate - the divided clock. |
| 87 | // It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. |
| 88 | // |
| 89 | // Revision 1.12 2001/12/19 08:03:34 mohor |
| 90 | // Warnings cleared. |
| 91 | // |
| 92 | // Revision 1.11 2001/12/06 14:51:04 gorban |
| 93 | // Bug in LSR[0] is fixed. |
| 94 | // All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. |
| 95 | // |
| 96 | // Revision 1.10 2001/12/03 21:44:29 gorban |
| 97 | // Updated specification documentation. |
| 98 | // Added full 32-bit data bus interface, now as default. |
| 99 | // Address is 5-bit wide in 32-bit data bus mode. |
| 100 | // Added wb_sel_i input to the core. It's used in the 32-bit mode. |
| 101 | // Added debug interface with two 32-bit read-only registers in 32-bit mode. |
| 102 | // Bits 5 and 6 of LSR are now only cleared on TX FIFO write. |
| 103 | // My small test bench is modified to work with 32-bit mode. |
| 104 | // |
| 105 | // Revision 1.9 2001/10/20 09:58:40 gorban |
| 106 | // Small synopsis fixes |
| 107 | // |
| 108 | // Revision 1.8 2001/08/24 21:01:12 mohor |
| 109 | // Things connected to parity changed. |
| 110 | // Clock devider changed. |
| 111 | // |
| 112 | // Revision 1.7 2001/08/23 16:05:05 mohor |
| 113 | // Stop bit bug fixed. |
| 114 | // Parity bug fixed. |
| 115 | // WISHBONE read cycle bug fixed, |
| 116 | // OE indicator (Overrun Error) bug fixed. |
| 117 | // PE indicator (Parity Error) bug fixed. |
| 118 | // Register read bug fixed. |
| 119 | // |
| 120 | // Revision 1.4 2001/05/31 20:08:01 gorban |
| 121 | // FIFO changes and other corrections. |
| 122 | // |
| 123 | // Revision 1.3 2001/05/21 19:12:01 gorban |
| 124 | // Corrected some Linter messages. |
| 125 | // |
| 126 | // Revision 1.2 2001/05/17 18:34:18 gorban |
| 127 | // First 'stable' release. Should be sythesizable now. Also added new header. |
| 128 | // |
| 129 | // Revision 1.0 2001-05-17 21:27:13+02 jacob |
| 130 | // Initial revision |
| 131 | // |
| 132 | // |
| 133 | |
| 134 | // UART core WISHBONE interface |
| 135 | // |
| 136 | // Author: Jacob Gorban (jacob.gorban@flextronicssemi.com) |
| 137 | // Company: Flextronics Semiconductor |
| 138 | // |
| 139 | |
| 140 | `timescale 1 ns / 10 ps |
| 141 | module uart_wb(clk, wb_rst_i, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i, |
| 142 | wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, |
| 143 | wb_sel_i, we_o, re_o); |
| 144 | |
| 145 | input clk; |
| 146 | input wb_rst_i; |
| 147 | input wb_we_i; |
| 148 | input wb_stb_i; |
| 149 | input wb_cyc_i; |
| 150 | input [3:0] wb_sel_i; |
| 151 | input [(3 - 1):0] wb_adr_i; |
| 152 | input [7:0] wb_dat_i; |
| 153 | output [7:0] wb_dat_o; |
| 154 | output [(3 - 1):0] wb_adr_int; |
| 155 | input [7:0] wb_dat8_o; |
| 156 | output [7:0] wb_dat8_i; |
| 157 | input [31:0] wb_dat32_o; |
| 158 | output wb_ack_o; |
| 159 | output we_o; |
| 160 | output re_o; |
| 161 | |
| 162 | reg [7:0] wb_dat_is; |
| 163 | reg [(3 - 1):0] wb_adr_is; |
| 164 | reg wb_we_is; |
| 165 | reg wb_cyc_is; |
| 166 | reg wb_stb_is; |
| 167 | reg [3:0] wb_sel_is; |
| 168 | reg [7:0] wb_dat_o; |
| 169 | reg [7:0] wb_dat8_i; |
| 170 | reg wb_ack_o; |
| 171 | reg wre; |
| 172 | reg [1:0] wbstate; |
| 173 | |
| 174 | assign we_o = (wb_we_is & wb_ack_o); |
| 175 | assign re_o = ((((~wb_we_is) & wb_stb_is) & wb_cyc_is) & wre); |
| 176 | assign wb_adr_int = wb_adr_is; |
| 177 | |
| 178 | always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin |
| 179 | wb_ack_o <= #(1) 1'b0; |
| 180 | wbstate <= #(1) 0; |
| 181 | wre <= #(1) 1'b1; |
| 182 | end |
| 183 | else begin |
| 184 | case (wbstate) |
| 185 | 0: begin |
| 186 | if (wb_stb_is & wb_cyc_is) begin |
| 187 | wre <= #(1) 0; |
| 188 | wbstate <= #(1) 1; |
| 189 | wb_ack_o <= #(1) 1; |
| 190 | end |
| 191 | else |
| 192 | begin |
| 193 | wre <= #(1) 1; |
| 194 | wb_ack_o <= #(1) 0; |
| 195 | end |
| 196 | end |
| 197 | 1: begin |
| 198 | wb_ack_o <= #(1) 0; |
| 199 | wbstate <= #(1) 2; |
| 200 | wre <= #(1) 0; |
| 201 | end |
| 202 | 2, 3: begin |
| 203 | wb_ack_o <= #(1) 0; |
| 204 | wbstate <= #(1) 0; |
| 205 | wre <= #(1) 0; |
| 206 | end |
| 207 | endcase |
| 208 | end |
| 209 | always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin |
| 210 | wb_adr_is <= #(1) 0; |
| 211 | wb_we_is <= #(1) 0; |
| 212 | wb_cyc_is <= #(1) 0; |
| 213 | wb_stb_is <= #(1) 0; |
| 214 | wb_dat_is <= #(1) 0; |
| 215 | wb_sel_is <= #(1) 0; |
| 216 | end |
| 217 | else |
| 218 | begin |
| 219 | wb_adr_is <= #(1) wb_adr_i; |
| 220 | wb_we_is <= #(1) wb_we_i; |
| 221 | wb_cyc_is <= #(1) wb_cyc_i; |
| 222 | wb_stb_is <= #(1) wb_stb_i; |
| 223 | wb_dat_is <= #(1) wb_dat_i; |
| 224 | wb_sel_is <= #(1) wb_sel_i; |
| 225 | end |
| 226 | always @(posedge clk or posedge wb_rst_i) if (wb_rst_i) begin |
| 227 | wb_dat_o <= #(1) 0; |
| 228 | end |
| 229 | else begin |
| 230 | wb_dat_o <= #(1) wb_dat8_o; |
| 231 | end |
| 232 | always @(wb_dat_is) wb_dat8_i = wb_dat_is; |
| 233 | endmodule |