| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_gcs_gc.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_gcs_gc ( |
| 36 | |
| 37 | // Clock and Reset |
| 38 | |
| 39 | clk, |
| 40 | rst_l, |
| 41 | |
| 42 | // Mondo Input Vector from the ISS |
| 43 | |
| 44 | int_req_vec, |
| 45 | |
| 46 | // Interface to Group Controller Arbiter |
| 47 | |
| 48 | gcs_req, |
| 49 | gcs_ino, |
| 50 | gcs_gnt, |
| 51 | |
| 52 | // Interface from the Reply status |
| 53 | |
| 54 | rss2gcs_rply, |
| 55 | rss2gcs_id, |
| 56 | rss2gcs_valid, |
| 57 | |
| 58 | // Interface for Interrupt Retry Timer |
| 59 | |
| 60 | iss2gcs_counter_limit, |
| 61 | static_gc_id, |
| 62 | |
| 63 | // Debug Interface |
| 64 | |
| 65 | fsm_dbg |
| 66 | |
| 67 | ); |
| 68 | |
| 69 | //############################################################################ |
| 70 | // PORT DECLARATIONS |
| 71 | //############################################################################ |
| 72 | |
| 73 | //------------------------------------------------------------------------ |
| 74 | // Clock and Reset Signals |
| 75 | //------------------------------------------------------------------------ |
| 76 | |
| 77 | input clk; |
| 78 | input rst_l; |
| 79 | |
| 80 | //------------------------------------------------------------------------ |
| 81 | // Mondo Input Vector from the ISS |
| 82 | //------------------------------------------------------------------------ |
| 83 | |
| 84 | |
| 85 | input [63:0] int_req_vec; //Requests to issue and interrupt |
| 86 | |
| 87 | //----------------------------------------------------- |
| 88 | // Interface to Group Controller Arbiter |
| 89 | //----------------------------------------------------- |
| 90 | |
| 91 | output gcs_req; // Request to group controller arbiter |
| 92 | output [5:0] gcs_ino; // INO for requesting mondo |
| 93 | input gcs_gnt; // Acknowldge for Request signal |
| 94 | |
| 95 | |
| 96 | //----------------------------------------------------- |
| 97 | // Interface from the Reply status block |
| 98 | //----------------------------------------------------- |
| 99 | |
| 100 | input rss2gcs_rply; // Reply type from RSS ack =1 nack =0 |
| 101 | input [1:0] rss2gcs_id; // Group controller ID for response |
| 102 | input rss2gcs_valid; // Valid signal to validate respose |
| 103 | |
| 104 | //----------------------------------------------------- |
| 105 | // Interface for Interrupt Retry Timer |
| 106 | //----------------------------------------------------- |
| 107 | |
| 108 | input [24:0] iss2gcs_counter_limit; // Cuunter Limit fo rthe retry counter |
| 109 | input [1:0] static_gc_id; // Id for group controller |
| 110 | |
| 111 | //----------------------------------------------------- |
| 112 | // Debug Interface |
| 113 | //----------------------------------------------------- |
| 114 | |
| 115 | output [`FIRE_DEBUG_WDTH-1:0] fsm_dbg; |
| 116 | |
| 117 | |
| 118 | //############################################################################ |
| 119 | // SIGNAL DECLARATIONS |
| 120 | //############################################################################ |
| 121 | |
| 122 | //------------------------ |
| 123 | // Wires |
| 124 | //------------------------ |
| 125 | wire update_winner; |
| 126 | wire [63:0] int_req_vec; |
| 127 | wire [63:0] int_winner_vec; |
| 128 | |
| 129 | wire timer_start; // Signal to start retry timer |
| 130 | wire timer_done; // SIgnal showing the retry timer is done |
| 131 | |
| 132 | |
| 133 | //############################################################################ |
| 134 | // MODULE INSTANCIATIONS |
| 135 | //############################################################################ |
| 136 | |
| 137 | |
| 138 | pcie_common_frr_arbiter #(64) frr_gc_arb( |
| 139 | |
| 140 | .clk (clk), |
| 141 | .rst_l (rst_l), |
| 142 | |
| 143 | .current_request_vector (int_req_vec), |
| 144 | .update_winner (update_winner), |
| 145 | |
| 146 | // Arbiter Outputs |
| 147 | |
| 148 | .current_winner_vector (int_winner_vec) |
| 149 | |
| 150 | ); |
| 151 | |
| 152 | |
| 153 | |
| 154 | dmu_imu_gcs_gc_cnt cnt( |
| 155 | |
| 156 | .clk (clk), |
| 157 | .rst_l (rst_l), |
| 158 | |
| 159 | .timer_start (timer_start), |
| 160 | .timer_done (timer_done), |
| 161 | |
| 162 | .iss2gcs_counter_limit (iss2gcs_counter_limit) |
| 163 | |
| 164 | ); |
| 165 | |
| 166 | |
| 167 | dmu_imu_gcs_gc_fsm fsm ( |
| 168 | |
| 169 | .clk (clk), |
| 170 | .rst_l (rst_l), |
| 171 | |
| 172 | .int_req_vec (int_req_vec), |
| 173 | .int_winner_vec (int_winner_vec), |
| 174 | |
| 175 | .update_winner (update_winner), |
| 176 | |
| 177 | .gcs_req (gcs_req), |
| 178 | .gcs_ino (gcs_ino), |
| 179 | .gcs_gnt (gcs_gnt), |
| 180 | |
| 181 | .rss2gcs_rply (rss2gcs_rply), |
| 182 | .rss2gcs_id (rss2gcs_id), |
| 183 | .rss2gcs_valid (rss2gcs_valid), |
| 184 | |
| 185 | .timer_start (timer_start), |
| 186 | .timer_done (timer_done), |
| 187 | |
| 188 | .static_gc_id (static_gc_id), |
| 189 | |
| 190 | .fsm_dbg (fsm_dbg) |
| 191 | |
| 192 | ); |
| 193 | |
| 194 | endmodule |