| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_mmu_qcb_qmc.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_mmu_qcb_qmc |
| 36 | ( |
| 37 | clk, // clock |
| 38 | rst_l, // reset |
| 39 | csr2qcb_ds_a, // csr debug select a |
| 40 | csr2qcb_ds_b, // csr debug select b |
| 41 | irb2qcb_enq, // irb srm enqueue |
| 42 | orb2qcb_full, // orb isr queue full |
| 43 | tcb2qcb_hld, // tcb hold |
| 44 | tcb2qcb_vld, // tcb valid bits |
| 45 | qpc2qmc_vld, // qpc valid bits |
| 46 | qrc2qmc_vld, // qrc valid bits |
| 47 | qvc2qmc_vld, // qvc valid bits |
| 48 | qcb2csr_dbg_a, // csr debug bus a |
| 49 | qcb2csr_dbg_b, // csr debug bus b |
| 50 | qcb2csr_paq, // csr physical address queue not empty |
| 51 | qcb2csr_vaq, // csr virtual address queue not empty |
| 52 | qcb2irb_full, // irb queue full |
| 53 | qcb2orb_enq, // orb srm enqueue |
| 54 | qcb2tcb_hld, // tcb hold |
| 55 | qcb2tcb_vld, // tcb valid |
| 56 | qmc2qpc_enq, // qpc enqueue |
| 57 | qmc2qpc_deq, // qpc dequeue |
| 58 | qmc2qrc_enq, // qrc enqueue |
| 59 | qmc2qrc_deq, // qrc dequeue |
| 60 | qmc2qvc_enq, // qvc enqueue |
| 61 | qmc2qvc_deq // qvc dequeue |
| 62 | ); |
| 63 | |
| 64 | // ---------------------------------------------------------------------------- |
| 65 | // Ports |
| 66 | // ---------------------------------------------------------------------------- |
| 67 | input clk; |
| 68 | input rst_l; |
| 69 | |
| 70 | input [`FIRE_DLC_MMU_CSR_DS_BITS] csr2qcb_ds_a; |
| 71 | input [`FIRE_DLC_MMU_CSR_DS_BITS] csr2qcb_ds_b; |
| 72 | input irb2qcb_enq; |
| 73 | input orb2qcb_full; |
| 74 | input tcb2qcb_hld; |
| 75 | input [`FIRE_DLC_MMU_PLS_DPTH:1] tcb2qcb_vld; |
| 76 | input [`FIRE_DLC_MMU_PAQ_DPTH-1:0] qpc2qmc_vld; |
| 77 | input [`FIRE_DLC_MMU_RDQ_DPTH-1:0] qrc2qmc_vld; |
| 78 | input [`FIRE_DLC_MMU_VAQ_DPTH-1:0] qvc2qmc_vld; |
| 79 | |
| 80 | output [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_a; |
| 81 | output [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_b; |
| 82 | output qcb2csr_paq; |
| 83 | output qcb2csr_vaq; |
| 84 | output qcb2irb_full; |
| 85 | output qcb2orb_enq; |
| 86 | output qcb2tcb_hld; |
| 87 | output qcb2tcb_vld; |
| 88 | output qmc2qpc_enq; |
| 89 | output qmc2qpc_deq; |
| 90 | output qmc2qrc_enq; |
| 91 | output qmc2qrc_deq; |
| 92 | output qmc2qvc_enq; |
| 93 | output qmc2qvc_deq; |
| 94 | |
| 95 | // ---------------------------------------------------------------------------- |
| 96 | // Variables |
| 97 | // ---------------------------------------------------------------------------- |
| 98 | wire [`FIRE_DBG_DATA_BITS] qcb2csr_dbg_a, qcb2csr_dbg_b; |
| 99 | |
| 100 | reg qcb2orb_enq; |
| 101 | reg qcb2tcb_hld; |
| 102 | reg deq, nxt_deq; |
| 103 | |
| 104 | reg [`FIRE_DLC_MMU_CSR_DS_BITS] dbg_sel [0:1]; |
| 105 | reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1]; |
| 106 | |
| 107 | integer i; |
| 108 | |
| 109 | // ---------------------------------------------------------------------------- |
| 110 | // Combinational |
| 111 | // ---------------------------------------------------------------------------- |
| 112 | wire qcb2csr_paq = qpc2qmc_vld[0]; |
| 113 | wire qcb2csr_vaq = qvc2qmc_vld[0]; |
| 114 | |
| 115 | wire vaq_full = qvc2qmc_vld[`FIRE_DLC_MMU_VAQ_DPTH-2]; |
| 116 | wire rdq_full = qrc2qmc_vld[`FIRE_DLC_MMU_RDQ_DPTH-2]; |
| 117 | |
| 118 | wire qcb2irb_full = vaq_full | rdq_full; |
| 119 | |
| 120 | wire enq = tcb2qcb_vld[`FIRE_DLC_MMU_PLS_DPTH]; |
| 121 | |
| 122 | always @ (orb2qcb_full or qpc2qmc_vld or enq or deq) begin |
| 123 | case ({enq, deq}) // synopsys parallel_case |
| 124 | 2'b00 : nxt_deq = qpc2qmc_vld[0] & ~orb2qcb_full; |
| 125 | 2'b01 : nxt_deq = qpc2qmc_vld[1] & ~orb2qcb_full; |
| 126 | 2'b10 : nxt_deq = ~orb2qcb_full; |
| 127 | 2'b11 : nxt_deq = ~orb2qcb_full; |
| 128 | endcase |
| 129 | end |
| 130 | |
| 131 | always @ (orb2qcb_full or tcb2qcb_vld or qpc2qmc_vld ) begin |
| 132 | if (!orb2qcb_full) begin |
| 133 | qcb2tcb_hld = 1'b0; |
| 134 | end |
| 135 | else begin |
| 136 | case (tcb2qcb_vld) // synopsys parallel_case |
| 137 | 3'b000 : qcb2tcb_hld = 1'b0; |
| 138 | 3'b001 : qcb2tcb_hld = qpc2qmc_vld[3]; |
| 139 | 3'b010 : qcb2tcb_hld = qpc2qmc_vld[3]; |
| 140 | 3'b011 : qcb2tcb_hld = qpc2qmc_vld[2]; |
| 141 | 3'b100 : qcb2tcb_hld = qpc2qmc_vld[3]; |
| 142 | 3'b101 : qcb2tcb_hld = qpc2qmc_vld[2]; |
| 143 | 3'b110 : qcb2tcb_hld = qpc2qmc_vld[2]; |
| 144 | 3'b111 : qcb2tcb_hld = qpc2qmc_vld[1]; |
| 145 | endcase |
| 146 | end |
| 147 | end |
| 148 | |
| 149 | wire qcb2tcb_vld = qvc2qmc_vld[0]; |
| 150 | |
| 151 | wire qmc2qpc_enq = enq; |
| 152 | |
| 153 | wire qmc2qrc_enq = irb2qcb_enq; |
| 154 | wire qmc2qvc_enq = irb2qcb_enq; |
| 155 | |
| 156 | wire qmc2qpc_deq = deq; |
| 157 | wire qmc2qrc_deq = deq; |
| 158 | |
| 159 | wire qmc2qvc_deq = qvc2qmc_vld[0] & ~tcb2qcb_hld; |
| 160 | |
| 161 | // ---------------------------------------------------------------------------- |
| 162 | // Debug |
| 163 | // ---------------------------------------------------------------------------- |
| 164 | always @ (csr2qcb_ds_a or csr2qcb_ds_b) begin |
| 165 | dbg_sel[0] = csr2qcb_ds_a; |
| 166 | dbg_sel[1] = csr2qcb_ds_b; |
| 167 | end |
| 168 | |
| 169 | assign qcb2csr_dbg_a = dbg_bus[0]; |
| 170 | assign qcb2csr_dbg_b = dbg_bus[1]; |
| 171 | |
| 172 | // ---------------------------------------------------------------------------- |
| 173 | // Sequential |
| 174 | // ---------------------------------------------------------------------------- |
| 175 | always @ (posedge clk) begin |
| 176 | if (!rst_l) begin |
| 177 | qcb2orb_enq <= 0; |
| 178 | deq <= 0; |
| 179 | end |
| 180 | else begin |
| 181 | qcb2orb_enq <= nxt_deq; |
| 182 | deq <= nxt_deq; |
| 183 | end |
| 184 | end |
| 185 | |
| 186 | always @ (posedge clk) |
| 187 | if(~rst_l) begin : dbg_rst |
| 188 | integer j; |
| 189 | for (j = 0; j < 2; j = j + 1) begin |
| 190 | dbg_bus[j] <= 8'h00; |
| 191 | end |
| 192 | end |
| 193 | else begin |
| 194 | for (i = 0; i < 2; i = i + 1) begin |
| 195 | case (dbg_sel[i]) // synopsys infer_mux |
| 196 | 3'b000: dbg_bus[i] <= { qpc2qmc_vld, qvc2qmc_vld }; |
| 197 | 3'b001: dbg_bus[i] <= qrc2qmc_vld; |
| 198 | 3'b010: dbg_bus[i] <= 8'h00; |
| 199 | 3'b011: dbg_bus[i] <= 8'h00; |
| 200 | 3'b100: dbg_bus[i] <= 8'h00; |
| 201 | 3'b101: dbg_bus[i] <= 8'h00; |
| 202 | 3'b110: dbg_bus[i] <= 8'h00; |
| 203 | 3'b111: dbg_bus[i] <= 8'h00; |
| 204 | endcase |
| 205 | end |
| 206 | end |
| 207 | |
| 208 | endmodule // dmu_mmu_qcb_qmc |