| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dec_del_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dec_del_ctl ( |
| 36 | l2clk, |
| 37 | scan_in, |
| 38 | tcu_pce_ov, |
| 39 | spc_aclk, |
| 40 | spc_bclk, |
| 41 | tcu_scan_en, |
| 42 | lsu_dec_pmen, |
| 43 | lsu_exu_pmen, |
| 44 | spc_core_running_status, |
| 45 | power_throttle, |
| 46 | lb_lbist_running, |
| 47 | pku_idest_p, |
| 48 | pku_fdest_p, |
| 49 | pku_fsrc_rd_p, |
| 50 | pku_lsu_p, |
| 51 | pku_fgu_p, |
| 52 | pku_pdist_p, |
| 53 | pku_twocycle_p, |
| 54 | pku_inst_cnt_brtaken00, |
| 55 | pku_inst_cnt_brtaken01, |
| 56 | pku_inst_cnt_brtaken02, |
| 57 | pku_inst_cnt_brtaken03, |
| 58 | pku_inst_cnt_brtaken04, |
| 59 | pku_inst_cnt_brtaken05, |
| 60 | pku_inst_cnt_brtaken06, |
| 61 | pku_inst_cnt_brtaken07, |
| 62 | pku_inst_cnt_brtaken10, |
| 63 | pku_inst_cnt_brtaken11, |
| 64 | pku_inst_cnt_brtaken12, |
| 65 | pku_inst_cnt_brtaken13, |
| 66 | pku_inst_cnt_brtaken14, |
| 67 | pku_inst_cnt_brtaken15, |
| 68 | pku_inst_cnt_brtaken16, |
| 69 | pku_inst_cnt_brtaken17, |
| 70 | exu_test_tid0, |
| 71 | exu_test_addr0, |
| 72 | exu_test_valid0, |
| 73 | exu_test_tid1, |
| 74 | exu_test_addr1, |
| 75 | exu_test_valid1, |
| 76 | ded_exc0_d, |
| 77 | ded_exc1_d, |
| 78 | tlu_dec_pstate_pef, |
| 79 | fgu_fprs_fef, |
| 80 | tlu_dec_hpstate_hpriv, |
| 81 | tlu_dec_pstate_priv, |
| 82 | dcd_wrtick_d, |
| 83 | lsu_cpq_stall, |
| 84 | dcd_callclass_d, |
| 85 | dcd_tcc_d, |
| 86 | dcd_specbr_d, |
| 87 | dcd_specfp_d, |
| 88 | dcd_exu_src_d, |
| 89 | dcd_killfgu_d, |
| 90 | dcd_sir_d, |
| 91 | dcd_stdfa_d, |
| 92 | pku_valid_e, |
| 93 | pku_annul_ds_dcti_brtaken0_e, |
| 94 | pku_annul_ds_dcti_brtaken1_e, |
| 95 | exu0_window_block, |
| 96 | exu1_window_block, |
| 97 | tlu_window_block, |
| 98 | fgu_idiv_stall, |
| 99 | fgu_fdiv_stall, |
| 100 | fgu_ecc_asi_stall, |
| 101 | dcd_fpdisable_d, |
| 102 | dcd_lsize0_d, |
| 103 | dcd_lsize1_d, |
| 104 | dcd_lsu_sign_ext_d, |
| 105 | dcd_load_d, |
| 106 | dcd_store_d, |
| 107 | dcd_sethi_d, |
| 108 | dcd_lsdouble_d, |
| 109 | dcd_prefetch_d, |
| 110 | dcd_flush_d, |
| 111 | dcd_memstbar_d, |
| 112 | dcd_pr_d, |
| 113 | dcd_priv_d, |
| 114 | dcd_hpr_d, |
| 115 | dcd_sr_d, |
| 116 | dcd_casa_d, |
| 117 | dcd_ldstub_d, |
| 118 | dcd_alt_d, |
| 119 | dcd_alti_d, |
| 120 | dcd_swap_d, |
| 121 | dcd_fsrc_rs1_d, |
| 122 | dcd_fsrc_rs2_d, |
| 123 | dcd_fpdest_single_d, |
| 124 | dcd_fp_rs1_single_d, |
| 125 | dcd_fp_rs2_single_d, |
| 126 | dcd_fsrsync_d, |
| 127 | dcd_done_d, |
| 128 | dcd_retry_d, |
| 129 | dec_inst0_rs1_d, |
| 130 | dec_inst0_rs2_d, |
| 131 | dec_inst0_raw_rd_d, |
| 132 | dec_inst1_rs1_d, |
| 133 | dec_inst1_rs2_d, |
| 134 | dec_inst1_raw_rd_d, |
| 135 | dcd_save_restore_d, |
| 136 | ded_oddwin0_d, |
| 137 | ded_oddwin1_d, |
| 138 | ded_perr_p, |
| 139 | ded_ferr_p, |
| 140 | ded_legal_p, |
| 141 | dec_inst0_b31, |
| 142 | dec_inst1_b31, |
| 143 | dec_inst0_op3_d, |
| 144 | dec_inst1_op3_d, |
| 145 | dec_inst0_opf_d, |
| 146 | dec_inst1_opf_d, |
| 147 | pku_base_pick_p, |
| 148 | pku_raw_pick0_p, |
| 149 | pku_raw_pick1_p, |
| 150 | pku_ds_e, |
| 151 | pku_load_flush_w, |
| 152 | tlu_flush_ifu, |
| 153 | pku_flush_f1, |
| 154 | pku_flush_f2, |
| 155 | pku_flush_lm, |
| 156 | pku_flush_lb, |
| 157 | pku_flush_m, |
| 158 | pku_flush_b, |
| 159 | dec_br_taken_e1, |
| 160 | spu_mult_request, |
| 161 | lsu_block_store_stall, |
| 162 | lsu_block_store_rd, |
| 163 | lsu_block_store_tid, |
| 164 | tlu_dtlb_reload_stall, |
| 165 | tlu_pstate_am, |
| 166 | dec_valid0_d, |
| 167 | dec_valid1_d, |
| 168 | dec_decode0_d, |
| 169 | dec_decode1_d, |
| 170 | del_noshift0_d, |
| 171 | del_noshift1_d, |
| 172 | dec_inst0_rd_d, |
| 173 | dec_inst1_rd_d, |
| 174 | dec_tid0_d, |
| 175 | dec_tid1_d, |
| 176 | dec_tid0_p, |
| 177 | dec_tid1_p, |
| 178 | dec_valid_e, |
| 179 | dec_pmu_valid_e, |
| 180 | dec_fgu_valid_e, |
| 181 | dec_frf_r1_addr_d, |
| 182 | dec_frf_r2_addr_d, |
| 183 | dec_frf_r2_addr_e, |
| 184 | dec_frf_r1_vld_d, |
| 185 | dec_frf_r2_vld_d, |
| 186 | dec_frf_r1_32b_d, |
| 187 | dec_frf_r2_32b_d, |
| 188 | dec_frf_r1_odd32b_d, |
| 189 | dec_frf_r2_odd32b_d, |
| 190 | dec_frf_w_addr_d, |
| 191 | dec_frf_w_vld_d, |
| 192 | dec_frf_w_32b_d, |
| 193 | dec_frf_w_odd32b_d, |
| 194 | dec_spu_grant_d, |
| 195 | dec_spu_grant_fgu_d, |
| 196 | dec_exu_src_vld_d, |
| 197 | dec_irf_w_addr_d, |
| 198 | dec_frf_store_d, |
| 199 | dec_fsr_store_d, |
| 200 | dec_fgu_op3_d, |
| 201 | dec_fgu_opf_d, |
| 202 | dec_fgu_decode_d, |
| 203 | dec_fgu_tid_d, |
| 204 | dec_flush_f1, |
| 205 | dec_flush_f2, |
| 206 | dec_flush_lm, |
| 207 | dec_flush_lb, |
| 208 | dec_flush_m, |
| 209 | dec_flush_b, |
| 210 | dec_block_store_b, |
| 211 | dec_exc0_m, |
| 212 | dec_exc1_m, |
| 213 | dec_inst0_cnt, |
| 214 | dec_inst1_cnt, |
| 215 | dec_tid0_m, |
| 216 | dec_tid1_m, |
| 217 | dec_inst_valid_m, |
| 218 | dec_lsu_inst_m, |
| 219 | dec_fgu_inst_m, |
| 220 | dec_cti_inst_m, |
| 221 | dec_illegal_inst_m, |
| 222 | dec_icache_perr_m, |
| 223 | dec_priv_exc_m, |
| 224 | dec_hpriv_exc_m, |
| 225 | dec_fpdisable_exc_m, |
| 226 | dec_br_taken_m, |
| 227 | dec_done_inst_m, |
| 228 | dec_retry_inst_m, |
| 229 | dec_sir_inst_m, |
| 230 | dec_ds_m, |
| 231 | dec_annul_ds_m, |
| 232 | dec_fgu_sel_e, |
| 233 | dec_fgu_sel_m, |
| 234 | dec_lsu_sel0_e, |
| 235 | dec_lsu_sel1_e, |
| 236 | dec_rs1_addr0_e, |
| 237 | dec_rs1_addr1_e, |
| 238 | dec_lsu_sel0_upper_e, |
| 239 | dec_lsu_sel1_upper_e, |
| 240 | dec_lsu_sel0_lower_e, |
| 241 | dec_lsu_sel1_lower_e, |
| 242 | dec_rs1_addr0_upper_e, |
| 243 | dec_rs1_addr1_upper_e, |
| 244 | del_pick_d, |
| 245 | dec_ld_inst_e, |
| 246 | dec_st_inst_e, |
| 247 | dec_fsr_ldst_e, |
| 248 | dec_fpldst_inst_e, |
| 249 | dec_ldst_dbl_e, |
| 250 | dec_pref_inst_e, |
| 251 | dec_flush_inst_e, |
| 252 | dec_memstbar_inst_e, |
| 253 | dec_sr_inst_e, |
| 254 | dec_pr_inst_e, |
| 255 | dec_hpr_inst_e, |
| 256 | dec_casa_inst_e, |
| 257 | dec_ldstub_inst_e, |
| 258 | dec_swap_inst_e, |
| 259 | dec_altspace_d, |
| 260 | dec_sign_ext_e, |
| 261 | dec_sraddr_e, |
| 262 | dec_imm_asi_vld_d, |
| 263 | dec_imm_asi_d, |
| 264 | dec_ldst_sz_e, |
| 265 | dec_ld_inst_d, |
| 266 | dec_lsu_tid0_d, |
| 267 | dec_lsu_tid1_d, |
| 268 | dec_lsu_tg_d, |
| 269 | dec_lsu_rd_e, |
| 270 | del_test0_sel_p, |
| 271 | del_twocycle0_std_p, |
| 272 | del_twocycle0_rs2_p, |
| 273 | del_default0_sel_p, |
| 274 | del_test1_sel_p, |
| 275 | del_twocycle1_std_p, |
| 276 | del_twocycle1_rs2_p, |
| 277 | del_default1_sel_p, |
| 278 | del_test_addr0_p, |
| 279 | del_test_addr1_p, |
| 280 | dec_instr0_type_d, |
| 281 | dec_instr1_type_d, |
| 282 | dec_exu_clken, |
| 283 | del_tg_clken, |
| 284 | scan_out, |
| 285 | dec_true_valid_e, |
| 286 | dec_load_flush_w, |
| 287 | dec_lsu_sel0_d, |
| 288 | dec_raw_pick_p, |
| 289 | dec_ierr_d, |
| 290 | dec_block_store_stall); |
| 291 | wire l1clk; |
| 292 | wire spares_scanin; |
| 293 | wire spares_scanout; |
| 294 | wire [1:0] pmu_valid_d; |
| 295 | wire [3:0] spare_5_0_lat_unused; |
| 296 | wire [1:0] pmu_valid_e; |
| 297 | wire pce_ov; |
| 298 | wire stop; |
| 299 | wire siclk; |
| 300 | wire soclk; |
| 301 | wire se; |
| 302 | wire callinst0_d; |
| 303 | wire callinst1_d; |
| 304 | wire [6:0] pdecode0_in; |
| 305 | wire [6:0] pdecode1_in; |
| 306 | wire [6:0] pdecode2_in; |
| 307 | wire [6:0] pdecode3_in; |
| 308 | wire [6:0] pdec0_in; |
| 309 | wire [6:0] pdecode0_d; |
| 310 | wire pdecode0f_scanin; |
| 311 | wire pdecode0f_scanout; |
| 312 | wire idest0_d; |
| 313 | wire fdest0_d; |
| 314 | wire fsrc0_rd_d; |
| 315 | wire lsu0_d; |
| 316 | wire fgu0_d; |
| 317 | wire pdist0_d; |
| 318 | wire twocycle0_d; |
| 319 | wire [6:0] pdecode4_in; |
| 320 | wire [6:0] pdecode5_in; |
| 321 | wire [6:0] pdecode6_in; |
| 322 | wire [6:0] pdecode7_in; |
| 323 | wire [6:0] pdec1_in; |
| 324 | wire [6:0] pdecode1_d; |
| 325 | wire pdecode1f_scanin; |
| 326 | wire pdecode1f_scanout; |
| 327 | wire idest1_d; |
| 328 | wire fdest1_d; |
| 329 | wire fsrc1_rd_d; |
| 330 | wire lsu1_d; |
| 331 | wire fgu1_d; |
| 332 | wire pdist1_d; |
| 333 | wire twocycle1_d; |
| 334 | wire [7:0] final_pick_p; |
| 335 | wire shift0_d; |
| 336 | wire [3:0] raw_pick0_in; |
| 337 | wire [3:0] pick0_d; |
| 338 | wire [3:0] pick0_in; |
| 339 | wire pick0f_scanin; |
| 340 | wire pick0f_scanout; |
| 341 | wire shift1_d; |
| 342 | wire [3:0] raw_pick1_in; |
| 343 | wire [3:0] pick1_d; |
| 344 | wire [3:0] pick1_in; |
| 345 | wire pick1f_scanin; |
| 346 | wire pick1f_scanout; |
| 347 | wire privstatef_scanin; |
| 348 | wire privstatef_scanout; |
| 349 | wire [7:0] tlu_priv; |
| 350 | wire [7:0] tlu_hpriv; |
| 351 | wire fef_scanin; |
| 352 | wire fef_scanout; |
| 353 | wire [7:0] tlu_pef; |
| 354 | wire [7:0] fgu_fef; |
| 355 | wire [1:0] priv_d; |
| 356 | wire [1:0] hpriv_d; |
| 357 | wire [1:0] fpdis_d; |
| 358 | wire [1:0] inst0_cnt_brtaken0; |
| 359 | wire [1:0] inst0_cnt_brtaken1; |
| 360 | wire [1:0] inst1_cnt_brtaken0; |
| 361 | wire [1:0] inst1_cnt_brtaken1; |
| 362 | wire [1:0] br_taken_e; |
| 363 | wire [1:0] ifetch_err_e; |
| 364 | wire [1:0] inst0_cnt; |
| 365 | wire [1:0] inst1_cnt; |
| 366 | wire instcntf_scanin; |
| 367 | wire instcntf_scanout; |
| 368 | wire exutestf_scanin; |
| 369 | wire exutestf_scanout; |
| 370 | wire [1:0] ttid0_p; |
| 371 | wire [1:0] ttid1_p; |
| 372 | wire test_stall0_in; |
| 373 | wire test_stall1_in; |
| 374 | wire teststallf_scanin; |
| 375 | wire teststallf_scanout; |
| 376 | wire test_stall0; |
| 377 | wire test_stall1; |
| 378 | wire [1:0] twocycle_p; |
| 379 | wire twocycle0_sel_p; |
| 380 | wire twocycle1_sel_p; |
| 381 | wire [1:0] tid0_p; |
| 382 | wire [1:0] tid1_p; |
| 383 | wire [1:0] tid0_d; |
| 384 | wire [1:0] tid1_d; |
| 385 | wire [7:0] valid_d_in; |
| 386 | wire [7:0] valid_d; |
| 387 | wire val_df_scanin; |
| 388 | wire val_df_scanout; |
| 389 | wire valid0_d_in; |
| 390 | wire valid1_d_in; |
| 391 | wire valid_df_scanin; |
| 392 | wire valid_df_scanout; |
| 393 | wire valid0_d; |
| 394 | wire valid1_d; |
| 395 | wire dtlb_reloadf_scanin; |
| 396 | wire dtlb_reloadf_scanout; |
| 397 | wire [1:0] dtlb_reload; |
| 398 | wire dtlb_reload_stall; |
| 399 | wire block_store0f_scanin; |
| 400 | wire block_store0f_scanout; |
| 401 | wire pre_block_store_stall; |
| 402 | wire block_store_stall_in; |
| 403 | wire block_store_stall; |
| 404 | wire reset_block_store_stall; |
| 405 | wire block_storef_scanin; |
| 406 | wire block_storef_scanout; |
| 407 | wire [4:0] block_store_rd_in; |
| 408 | wire [4:0] block_store_rd; |
| 409 | wire block_store_rdhif_scanin; |
| 410 | wire block_store_rdhif_scanout; |
| 411 | wire block_store_rdlof_scanin; |
| 412 | wire block_store_rdlof_scanout; |
| 413 | wire [2:0] block_store_tid_in; |
| 414 | wire [2:0] block_store_tid; |
| 415 | wire block_store_tidf_scanin; |
| 416 | wire block_store_tidf_scanout; |
| 417 | wire block_store_stall0; |
| 418 | wire block_store_stall1; |
| 419 | wire cpq_stall_in; |
| 420 | wire cpq_stallf_scanin; |
| 421 | wire cpq_stallf_scanout; |
| 422 | wire cpq_stall; |
| 423 | wire fecc_stall_in; |
| 424 | wire fecc_stallf_scanin; |
| 425 | wire fecc_stallf_scanout; |
| 426 | wire fecc_stall; |
| 427 | wire block_resetf_scanin; |
| 428 | wire block_resetf_scanout; |
| 429 | wire [2:0] block_rst_cnt_in; |
| 430 | wire [2:0] block_rst_cnt; |
| 431 | wire block_store_e_scanin; |
| 432 | wire block_store_e_scanout; |
| 433 | wire block_store_stall_e; |
| 434 | wire [2:0] block_store_tid_e; |
| 435 | wire block_store_m_scanin; |
| 436 | wire block_store_m_scanout; |
| 437 | wire block_store_stall_m; |
| 438 | wire [2:0] block_store_tid_m; |
| 439 | wire block_store_b_scanin; |
| 440 | wire block_store_b_scanout; |
| 441 | wire block_store_stall_b; |
| 442 | wire [2:0] block_store_tid_b; |
| 443 | wire set_lfavor; |
| 444 | wire lsusel0_d; |
| 445 | wire reset_lfavor; |
| 446 | wire lfavor_in; |
| 447 | wire lfavor; |
| 448 | wire lfavorf_scanin; |
| 449 | wire lfavorf_scanout; |
| 450 | wire set_ffavor; |
| 451 | wire fgusel0_d; |
| 452 | wire reset_ffavor; |
| 453 | wire ffavor_in; |
| 454 | wire ffavor; |
| 455 | wire ffavorf_scanin; |
| 456 | wire ffavorf_scanout; |
| 457 | wire set_sffavor; |
| 458 | wire lsu_float_case; |
| 459 | wire reset_sffavor; |
| 460 | wire sffavor_in; |
| 461 | wire sffavor; |
| 462 | wire sffavorf_scanin; |
| 463 | wire sffavorf_scanout; |
| 464 | wire mult_request_in; |
| 465 | wire mult_request; |
| 466 | wire mulrequestf_scanin; |
| 467 | wire mulrequestf_scanout; |
| 468 | wire crypto_mult_case0; |
| 469 | wire crypto_mult_case1; |
| 470 | wire set_cmfavor; |
| 471 | wire reset_cmfavor; |
| 472 | wire cmfavor; |
| 473 | wire cmfavor_grant_d; |
| 474 | wire idiv_hole_d; |
| 475 | wire [1:0] idiv_stall_d; |
| 476 | wire pdistblock_d; |
| 477 | wire cmfavor_in; |
| 478 | wire cmfavorf_scanin; |
| 479 | wire cmfavorf_scanout; |
| 480 | wire [1:0] pdistblock_in; |
| 481 | wire pdistblockf_scanin; |
| 482 | wire pdistblockf_scanout; |
| 483 | wire [1:0] pdistblock; |
| 484 | wire pdistrdf_scanin; |
| 485 | wire pdistrdf_scanout; |
| 486 | wire [4:0] pdist_rd; |
| 487 | wire pdisttidf_scanin; |
| 488 | wire pdisttidf_scanout; |
| 489 | wire [2:0] pdist_tid; |
| 490 | wire twocycle0_d_in; |
| 491 | wire twocycle0_df_scanin; |
| 492 | wire twocycle0_df_scanout; |
| 493 | wire twocycle0_stall; |
| 494 | wire twocycle1_d_in; |
| 495 | wire twocycle1_df_scanin; |
| 496 | wire twocycle1_df_scanout; |
| 497 | wire twocycle1_stall; |
| 498 | wire int_hole0_in; |
| 499 | wire inthole0_df_scanin; |
| 500 | wire inthole0_df_scanout; |
| 501 | wire [2:0] int_hole0_stall; |
| 502 | wire int_hole1_in; |
| 503 | wire inthole1_df_scanin; |
| 504 | wire inthole1_df_scanout; |
| 505 | wire [2:0] int_hole1_stall; |
| 506 | wire divstall_df_scanin; |
| 507 | wire divstall_df_scanout; |
| 508 | wire fdiv_stall_d; |
| 509 | wire [1:0] window_stall_in; |
| 510 | wire windowstall_df_scanin; |
| 511 | wire windowstall_df_scanout; |
| 512 | wire [1:0] window_stall_d; |
| 513 | wire [1:0] exu_clken_in; |
| 514 | wire exu_clkenf_scanin; |
| 515 | wire exu_clkenf_scanout; |
| 516 | wire block0; |
| 517 | wire [7:0] power_stall; |
| 518 | wire block1; |
| 519 | wire legal_f_scanin; |
| 520 | wire legal_f_scanout; |
| 521 | wire [1:0] legal_d; |
| 522 | wire illegal0_d; |
| 523 | wire [1:0] ifetch_err_d; |
| 524 | wire illegal1_d; |
| 525 | wire [1:0] perr_d; |
| 526 | wire [1:0] illegal_d; |
| 527 | wire illegal_f_scanin; |
| 528 | wire illegal_f_scanout; |
| 529 | wire [1:0] illegal_e; |
| 530 | wire [1:0] fpdisable_exc_d; |
| 531 | wire fpdisable_exc_f_scanin; |
| 532 | wire fpdisable_exc_f_scanout; |
| 533 | wire [1:0] fpdisable_exc_e; |
| 534 | wire [1:0] priv_exc_d; |
| 535 | wire [1:0] hpriv_exc_d; |
| 536 | wire parity_err_f_scanin; |
| 537 | wire parity_err_f_scanout; |
| 538 | wire [1:0] icdp_perr_d; |
| 539 | wire exc_f_scanin; |
| 540 | wire exc_f_scanout; |
| 541 | wire [1:0] priv_exc_e; |
| 542 | wire [1:0] hpriv_exc_e; |
| 543 | wire [1:0] icdp_perr_e; |
| 544 | wire ffavor_real; |
| 545 | wire lfavor_real; |
| 546 | wire [1:0] fguselect_d; |
| 547 | wire tgsel_f_scanin; |
| 548 | wire tgsel_f_scanout; |
| 549 | wire twocycle0_stall_e; |
| 550 | wire twocycle1_stall_e; |
| 551 | wire decode_lsu0_e; |
| 552 | wire decode_lsu1_e; |
| 553 | wire [1:0] pstate_am_in; |
| 554 | wire rs1_addr0_d; |
| 555 | wire decode_lsu0_d; |
| 556 | wire casa_or_pst_d; |
| 557 | wire rs1_addr1_d; |
| 558 | wire decode_lsu1_d; |
| 559 | wire lsu_sel0_lower_d; |
| 560 | wire lsu_sel1_lower_d; |
| 561 | wire lsu_sel0_upper_d; |
| 562 | wire lsu_sel1_upper_d; |
| 563 | wire rs1_addr0_upper_d; |
| 564 | wire rs1_addr1_upper_d; |
| 565 | wire exuself_scanin; |
| 566 | wire exuself_scanout; |
| 567 | wire tgselm_f_scanin; |
| 568 | wire tgselm_f_scanout; |
| 569 | wire [1:0] store_float; |
| 570 | wire [4:0] i0_rd; |
| 571 | wire [4:0] i1_rd; |
| 572 | wire [4:0] i0_rd_remap_d; |
| 573 | wire [4:0] i1_rd_remap_d; |
| 574 | wire [4:0] f0_rs1; |
| 575 | wire [4:0] f0_rs2; |
| 576 | wire [4:0] f0_rd; |
| 577 | wire [4:0] f1_rs1; |
| 578 | wire [4:0] f1_rs2; |
| 579 | wire [4:0] f1_rd; |
| 580 | wire [4:0] inst0_rs2; |
| 581 | wire [4:0] inst1_rs2; |
| 582 | wire frf_r2addre_f_scanin; |
| 583 | wire frf_r2addre_f_scanout; |
| 584 | wire inst0_rs2_raw_bit0; |
| 585 | wire inst1_rs2_raw_bit0; |
| 586 | wire fsr_store0; |
| 587 | wire fsr_store1; |
| 588 | wire flush_lexc_m; |
| 589 | wire ifetch_err_f_scanin; |
| 590 | wire ifetch_err_f_scanout; |
| 591 | wire ifetcherr_f_scanin; |
| 592 | wire ifetcherr_f_scanout; |
| 593 | wire [1:0] true_valid_d; |
| 594 | wire truevalid_f_scanin; |
| 595 | wire truevalid_f_scanout; |
| 596 | wire illegal0_pmu_d; |
| 597 | wire illegal1_pmu_d; |
| 598 | wire [1:0] illegal_pmu_d; |
| 599 | wire [1:0] priv_exc_pmu_d; |
| 600 | wire [1:0] hpriv_exc_pmu_d; |
| 601 | wire [1:0] fpdisable_exc_pmu_d; |
| 602 | wire [1:0] valid_e; |
| 603 | wire [1:0] ls_valid_e; |
| 604 | wire decode_fgu0_d; |
| 605 | wire decode_fgu1_d; |
| 606 | wire fgudec_f_scanin; |
| 607 | wire fgudec_f_scanout; |
| 608 | wire decode_fgu0_e; |
| 609 | wire decode_fgu1_e; |
| 610 | wire lsudec_f_scanin; |
| 611 | wire lsudec_f_scanout; |
| 612 | wire st_inst_d; |
| 613 | wire fsr_ldst_d; |
| 614 | wire ldste_f_scanin; |
| 615 | wire ldste_f_scanout; |
| 616 | wire ld_inst_e; |
| 617 | wire st_inst_e; |
| 618 | wire fsr_ldst_e; |
| 619 | wire lsu_valid_e; |
| 620 | wire fpldst_d; |
| 621 | wire load_float0_d; |
| 622 | wire store_float0_d; |
| 623 | wire load_float1_d; |
| 624 | wire store_float1_d; |
| 625 | wire lsdouble_d; |
| 626 | wire prefetch_d; |
| 627 | wire flush_d; |
| 628 | wire memstbar_d; |
| 629 | wire pr_d; |
| 630 | wire hpr_d; |
| 631 | wire sr_d; |
| 632 | wire pst_d; |
| 633 | wire casa_d; |
| 634 | wire ldstub_d; |
| 635 | wire swap_d; |
| 636 | wire altspacei_d; |
| 637 | wire sign_ext_d; |
| 638 | wire [1:0] lsize_d; |
| 639 | wire ldme_f_scanin; |
| 640 | wire ldme_f_scanout; |
| 641 | wire fpldst_e; |
| 642 | wire lsdouble_e; |
| 643 | wire prefetch_e; |
| 644 | wire flush_e; |
| 645 | wire memstbar_e; |
| 646 | wire hpr_e; |
| 647 | wire pr_e; |
| 648 | wire sr_e; |
| 649 | wire casa_e; |
| 650 | wire ldstub_e; |
| 651 | wire swap_e; |
| 652 | wire sign_ext_e; |
| 653 | wire [1:0] lsize_e; |
| 654 | wire [4:0] sraddr_d; |
| 655 | wire sraddr_f_scanin; |
| 656 | wire sraddr_f_scanout; |
| 657 | wire [4:0] sraddr_e; |
| 658 | wire lsu_rd0_msb; |
| 659 | wire lsu_rd1_msb; |
| 660 | wire [4:0] lsu_rd_d; |
| 661 | wire lsurd_f_scanin; |
| 662 | wire lsurd_f_scanout; |
| 663 | wire [4:0] lsu_rd_e; |
| 664 | wire [1:0] ds_m_in; |
| 665 | wire ds_m_scanin; |
| 666 | wire ds_m_scanout; |
| 667 | wire [7:0] annul_ds_dcti_e; |
| 668 | wire [1:0] annul_ds_m_in; |
| 669 | wire annul_m_scanin; |
| 670 | wire annul_m_scanout; |
| 671 | wire tid_e_scanin; |
| 672 | wire tid_e_scanout; |
| 673 | wire [1:0] tid1_e; |
| 674 | wire [1:0] tid0_e; |
| 675 | wire tid_m_scanin; |
| 676 | wire tid_m_scanout; |
| 677 | wire dec_e_scanin; |
| 678 | wire dec_e_scanout; |
| 679 | wire decode1_raw_e; |
| 680 | wire decode0_raw_e; |
| 681 | wire decode1_e; |
| 682 | wire decode0_e; |
| 683 | wire dec_m_scanin; |
| 684 | wire dec_m_scanout; |
| 685 | wire [1:0] inst_valid_m; |
| 686 | wire is_lsu1_d; |
| 687 | wire is_lsu0_d; |
| 688 | wire is_fgu1_d; |
| 689 | wire is_fgu0_d; |
| 690 | wire [1:0] cti_d; |
| 691 | wire inst_e_scanin; |
| 692 | wire inst_e_scanout; |
| 693 | wire [4:0] exc1_e; |
| 694 | wire [4:0] exc0_e; |
| 695 | wire [1:0] is_lsu_e; |
| 696 | wire [1:0] is_fgu_e; |
| 697 | wire [1:0] cti_e; |
| 698 | wire inst_m_scanin; |
| 699 | wire inst_m_scanout; |
| 700 | wire [4:0] exc1_m; |
| 701 | wire [4:0] exc0_m; |
| 702 | wire flush_lexc_e; |
| 703 | wire flush_lexc_f_scanin; |
| 704 | wire flush_lexc_f_scanout; |
| 705 | wire illegal_priv_m_scanin; |
| 706 | wire illegal_priv_m_scanout; |
| 707 | wire [1:0] illegal_inst_m; |
| 708 | wire [1:0] priv_exc_m; |
| 709 | wire [1:0] hpriv_exc_m; |
| 710 | wire [1:0] fpdisable_exc_m; |
| 711 | wire [1:0] br_taken_m; |
| 712 | wire [1:0] icdp_perr_m; |
| 713 | wire [1:0] done_d; |
| 714 | wire [1:0] retry_d; |
| 715 | wire [1:0] sir_d; |
| 716 | wire done_retry_e_scanin; |
| 717 | wire done_retry_e_scanout; |
| 718 | wire [1:0] done_e; |
| 719 | wire [1:0] retry_e; |
| 720 | wire [1:0] sir_e; |
| 721 | wire done_retry_m_scanin; |
| 722 | wire done_retry_m_scanout; |
| 723 | wire [1:0] done_inst_m; |
| 724 | wire [1:0] retry_inst_m; |
| 725 | wire [1:0] sir_inst_m; |
| 726 | wire [1:0] atomic_d; |
| 727 | wire l2miss0_d; |
| 728 | wire l2miss1_d; |
| 729 | wire itlbmiss0_d; |
| 730 | wire itlbmiss1_d; |
| 731 | wire icmiss0_d; |
| 732 | wire icmiss1_d; |
| 733 | wire other0_d; |
| 734 | wire branch0_d; |
| 735 | wire other1_d; |
| 736 | wire branch1_d; |
| 737 | wire power_stall1f_scanin; |
| 738 | wire power_stall1f_scanout; |
| 739 | wire [7:0] power_stall_in; |
| 740 | wire thread_activef_scanin; |
| 741 | wire thread_activef_scanout; |
| 742 | wire [7:0] thread_active; |
| 743 | wire power_throttle1f_scanin; |
| 744 | wire power_throttle1f_scanout; |
| 745 | wire [2:0] power_throt0; |
| 746 | wire [2:0] power_throttle1; |
| 747 | wire power_throttle02_f_scanin; |
| 748 | wire power_throttle02_f_scanout; |
| 749 | wire [2:0] power_throttle0; |
| 750 | wire power_throttle01_f_scanin; |
| 751 | wire power_throttle01_f_scanout; |
| 752 | wire power_throttle00_f_scanin; |
| 753 | wire power_throttle00_f_scanout; |
| 754 | wire change_power_stall; |
| 755 | wire [7:0] new_power_stall; |
| 756 | |
| 757 | |
| 758 | input l2clk; |
| 759 | input scan_in; |
| 760 | input tcu_pce_ov; // scan signals |
| 761 | input spc_aclk; |
| 762 | input spc_bclk; |
| 763 | input tcu_scan_en; |
| 764 | |
| 765 | |
| 766 | input lsu_dec_pmen; // power management enable for dec |
| 767 | input lsu_exu_pmen; // power management enable for exu |
| 768 | |
| 769 | input [7:0] spc_core_running_status; // active bits for each of the threads |
| 770 | |
| 771 | |
| 772 | input [2:0] power_throttle; // power throttle, [2:0] is encoded number of stalls in 8 cycle window |
| 773 | // 000 - no stalls, 001 - 1 stall, ... 111 - 7 stalls |
| 774 | input lb_lbist_running; |
| 775 | |
| 776 | input [7:0] pku_idest_p; |
| 777 | input [7:0] pku_fdest_p; |
| 778 | input [7:0] pku_fsrc_rd_p; |
| 779 | input [7:0] pku_lsu_p; |
| 780 | input [7:0] pku_fgu_p; |
| 781 | input [7:0] pku_pdist_p; |
| 782 | input [7:0] pku_twocycle_p; |
| 783 | |
| 784 | input [1:0] pku_inst_cnt_brtaken00; // count of inst at e,m,b stages for each thread, for tlu to generate PC at decode |
| 785 | input [1:0] pku_inst_cnt_brtaken01; |
| 786 | input [1:0] pku_inst_cnt_brtaken02; |
| 787 | input [1:0] pku_inst_cnt_brtaken03; |
| 788 | input [1:0] pku_inst_cnt_brtaken04; |
| 789 | input [1:0] pku_inst_cnt_brtaken05; |
| 790 | input [1:0] pku_inst_cnt_brtaken06; |
| 791 | input [1:0] pku_inst_cnt_brtaken07; |
| 792 | input [1:0] pku_inst_cnt_brtaken10; // count of inst at e,m,b stages for each thread, for tlu to generate PC at decode |
| 793 | input [1:0] pku_inst_cnt_brtaken11; |
| 794 | input [1:0] pku_inst_cnt_brtaken12; |
| 795 | input [1:0] pku_inst_cnt_brtaken13; |
| 796 | input [1:0] pku_inst_cnt_brtaken14; |
| 797 | input [1:0] pku_inst_cnt_brtaken15; |
| 798 | input [1:0] pku_inst_cnt_brtaken16; |
| 799 | input [1:0] pku_inst_cnt_brtaken17; |
| 800 | |
| 801 | input [1:0] exu_test_tid0; // exu test interface to the irf (bist or ecc errors) |
| 802 | input [4:0] exu_test_addr0; |
| 803 | input exu_test_valid0; |
| 804 | |
| 805 | input [1:0] exu_test_tid1; // exu test interface to the irf (bist or ecc errors) |
| 806 | input [4:0] exu_test_addr1; |
| 807 | input exu_test_valid1; |
| 808 | |
| 809 | input [4:0] ded_exc0_d; // ifetch related exceptions |
| 810 | input [4:0] ded_exc1_d; |
| 811 | |
| 812 | input [7:0] tlu_dec_pstate_pef; // pstate enable fp bit |
| 813 | input [7:0] fgu_fprs_fef; // fprs enable fp bit |
| 814 | input [7:0] tlu_dec_hpstate_hpriv; // hpriv bits |
| 815 | input [7:0] tlu_dec_pstate_priv; // priv bits |
| 816 | |
| 817 | input [1:0] dcd_wrtick_d; // write tick |
| 818 | |
| 819 | input lsu_cpq_stall; // lsu cannot take any more lsu operations, stall decode |
| 820 | input [1:0] dcd_callclass_d; // JMPs,CALLs,RETs |
| 821 | input [1:0] dcd_tcc_d; // tcc instruction |
| 822 | |
| 823 | input [1:0] dcd_specbr_d; // branch at decode |
| 824 | input [1:0] dcd_specfp_d; // FP at decode |
| 825 | |
| 826 | input [1:0] dcd_exu_src_d; // fgu sources will come from the integer unit |
| 827 | input [1:0] dcd_killfgu_d; // dont really send alignaddr, bmask to the fgu |
| 828 | |
| 829 | input [1:0] dcd_sir_d; // SIR inst at decode |
| 830 | input [1:0] dcd_stdfa_d; // for partial stores |
| 831 | |
| 832 | input [7:0] pku_valid_e; // valid for inst at e stage |
| 833 | input [7:0] pku_annul_ds_dcti_brtaken0_e; // dcti at e stage has annulled its delay slot (DS) |
| 834 | input [7:0] pku_annul_ds_dcti_brtaken1_e; // dcti at e stage has annulled its delay slot (DS) |
| 835 | |
| 836 | input exu0_window_block; // for saves,restores,traps on saves,restores,wrpr to cwp |
| 837 | input exu1_window_block; |
| 838 | input [1:0] tlu_window_block; // for dones and retries |
| 839 | |
| 840 | input [1:0] fgu_idiv_stall; // integer divide stall; no int ops to FGU |
| 841 | input fgu_fdiv_stall; // float divide stall; no float loads to the LSU |
| 842 | |
| 843 | input fgu_ecc_asi_stall; // fgu ecc stall |
| 844 | |
| 845 | input [1:0] dcd_fpdisable_d; // inst can cause a fpdisable exception |
| 846 | |
| 847 | |
| 848 | // decodes needed by the lsu |
| 849 | input [1:0] dcd_lsize0_d; // size of the lsu operation (byte,half,word,dword) |
| 850 | input [1:0] dcd_lsize1_d; |
| 851 | input [1:0] dcd_lsu_sign_ext_d; // lsu operation is a sign extended form |
| 852 | input [1:0] dcd_load_d; // op is load or load-like |
| 853 | input [1:0] dcd_store_d; // op is store or store-like |
| 854 | input [1:0] dcd_sethi_d; // op is special sethi |
| 855 | input [1:0] dcd_lsdouble_d; // ldd inst |
| 856 | input [1:0] dcd_prefetch_d; // prefetch inst |
| 857 | input [1:0] dcd_flush_d; // flush inst |
| 858 | input [1:0] dcd_memstbar_d; // membar, stbar |
| 859 | input [1:0] dcd_pr_d; // is a WRPR or RDPR inst |
| 860 | input [1:0] dcd_priv_d; // is a privileged inst |
| 861 | input [1:0] dcd_hpr_d; // is a hypervisor priv inst |
| 862 | input [1:0] dcd_sr_d; // ASR operation |
| 863 | input [1:0] dcd_casa_d; // CASA inst |
| 864 | input [1:0] dcd_ldstub_d; // LDSTUB inst |
| 865 | input [1:0] dcd_alt_d; // alternate but not imm |
| 866 | input [1:0] dcd_alti_d; // imm alternate |
| 867 | input [1:0] dcd_swap_d; // SWAP inst |
| 868 | |
| 869 | input [1:0] dcd_fsrc_rs1_d; // inst has rs1 FP source |
| 870 | input [1:0] dcd_fsrc_rs2_d; // inst has rs2 FP source |
| 871 | input [1:0] dcd_fpdest_single_d; // FP dest is single precision (SP) |
| 872 | input [1:0] dcd_fp_rs1_single_d; // FP rs1 source is SP |
| 873 | input [1:0] dcd_fp_rs2_single_d; // FP rs2 source is SP |
| 874 | input [1:0] dcd_fsrsync_d; // inst is LDFSR or STFSR |
| 875 | input [1:0] dcd_done_d; // inst is DONE inst |
| 876 | input [1:0] dcd_retry_d; // inst is a RETRY inst |
| 877 | |
| 878 | input [4:0] dec_inst0_rs1_d; // RS1 |
| 879 | input [4:0] dec_inst0_rs2_d; // RS2 |
| 880 | input [4:0] dec_inst0_raw_rd_d; // RD |
| 881 | input [4:0] dec_inst1_rs1_d; |
| 882 | input [4:0] dec_inst1_rs2_d; |
| 883 | input [4:0] dec_inst1_raw_rd_d; |
| 884 | |
| 885 | input [1:0] dcd_save_restore_d; // SAVE or RESTORE |
| 886 | input ded_oddwin0_d; // window is odd or not |
| 887 | input ded_oddwin1_d; |
| 888 | |
| 889 | input [1:0] ded_perr_p; // inst parity error |
| 890 | input [1:0] ded_ferr_p; // inst fetch error |
| 891 | input [1:0] ded_legal_p; // inst is a legal instruction |
| 892 | |
| 893 | input dec_inst0_b31; // bit 31 of instruction |
| 894 | input dec_inst1_b31; |
| 895 | |
| 896 | input [5:0] dec_inst0_op3_d; // op3 field of inst |
| 897 | input [5:0] dec_inst1_op3_d; |
| 898 | |
| 899 | input [7:0] dec_inst0_opf_d; // opf field of inst |
| 900 | input [7:0] dec_inst1_opf_d; |
| 901 | |
| 902 | input [7:0] pku_base_pick_p; // base pick without decode qualifications (includes cancel_pick, flush_buffer) |
| 903 | input [3:0] pku_raw_pick0_p; // pick with no qualifications (no cancel_pick, no flush_buffer) |
| 904 | input [7:4] pku_raw_pick1_p; |
| 905 | |
| 906 | input [7:0] pku_ds_e; // inst at e is a DS |
| 907 | |
| 908 | input [7:0] pku_load_flush_w; // load flush signals to IFU |
| 909 | input [7:0] tlu_flush_ifu; // trap flush |
| 910 | |
| 911 | input [7:0] pku_flush_f1; // flush signals for FGU f1,f2 stages |
| 912 | input [7:0] pku_flush_f2; |
| 913 | |
| 914 | input [7:0] pku_flush_lm; // flush signals for LSU M,B stages |
| 915 | input [7:0] pku_flush_lb; |
| 916 | |
| 917 | input [7:0] pku_flush_m; // flush signals for TLU M,B stages |
| 918 | input [7:0] pku_flush_b; |
| 919 | |
| 920 | input [1:0] dec_br_taken_e1; // taken branches |
| 921 | |
| 922 | input spu_mult_request; // crypto multiply request |
| 923 | |
| 924 | input lsu_block_store_stall; // stall decode to read the sources of the store |
| 925 | input [4:3] lsu_block_store_rd; // RD for the block store |
| 926 | input [2:0] lsu_block_store_tid; // tid for the block store |
| 927 | |
| 928 | input tlu_dtlb_reload_stall; // stall decode for 2 cycles on a DTLB miss; LSU can't take any more lsu ops |
| 929 | input [7:0] tlu_pstate_am; // address mask bit |
| 930 | |
| 931 | output dec_valid0_d; // inst is valid at d stage |
| 932 | output dec_valid1_d; |
| 933 | output dec_decode0_d; // inst is decoded at d stage (implies a shift) |
| 934 | output dec_decode1_d; |
| 935 | output del_noshift0_d; // inst is valid and not decoded (don't shift the decode stage) |
| 936 | output del_noshift1_d; |
| 937 | |
| 938 | // exu interface |
| 939 | output [4:0] dec_inst0_rd_d; // RD field (takes windows and calls into account) |
| 940 | output [4:0] dec_inst1_rd_d; |
| 941 | |
| 942 | output [1:0] dec_tid0_d; // TID for exu0 |
| 943 | output [1:0] dec_tid1_d; // TID for exu1 |
| 944 | output [1:0] dec_tid0_p; // TID for IRF |
| 945 | output [1:0] dec_tid1_p; |
| 946 | output [1:0] dec_valid_e; // thread group [0,1] is valid at e stage |
| 947 | output [1:0] dec_pmu_valid_e; // thread group [0,1] is valid at e stage; dont include ifetch_err |
| 948 | output dec_fgu_valid_e; // fgu is valid at e |
| 949 | |
| 950 | // fgu interface |
| 951 | output [4:0] dec_frf_r1_addr_d; // FRF r1 read addr |
| 952 | output [4:0] dec_frf_r2_addr_d; // FRF r2 read addr (including store-floats) |
| 953 | output [4:3] dec_frf_r2_addr_e; // FRF r2 read addr (for LSU) |
| 954 | output dec_frf_r1_vld_d; // FRF r1 read valid |
| 955 | output dec_frf_r2_vld_d; // FRF r2 read valid |
| 956 | output dec_frf_r1_32b_d; // FRF rs1 source is single-precision |
| 957 | output dec_frf_r2_32b_d; // FRF rs2 source is single-precision |
| 958 | output dec_frf_r1_odd32b_d; // FRF rs1 source is single-precision and odd |
| 959 | output dec_frf_r2_odd32b_d; // FRF rs2 source is single-precision and odd |
| 960 | output [4:0] dec_frf_w_addr_d; // FRF write addr |
| 961 | output dec_frf_w_vld_d; // FRF write addr is valid |
| 962 | output dec_frf_w_32b_d; // FRF write is single precision |
| 963 | output dec_frf_w_odd32b_d; // FRF write is single precision; rd is odd |
| 964 | output dec_spu_grant_d; // SPU grant for a crypto multiply |
| 965 | output dec_spu_grant_fgu_d; // SPU grant for a crypto multiply to the fgu |
| 966 | output dec_exu_src_vld_d; // FGU op has any valid source |
| 967 | output [4:0] dec_irf_w_addr_d; // RD for an integer op executed by the FGU |
| 968 | output dec_frf_store_d; // store-float of FRF data |
| 969 | output dec_fsr_store_d; // store-float of FSR data |
| 970 | output [5:0] dec_fgu_op3_d; // op3 field |
| 971 | output [7:0] dec_fgu_opf_d; // opf field |
| 972 | output dec_fgu_decode_d; // FGU op decoded this cycle |
| 973 | output [2:0] dec_fgu_tid_d; // TID for FGU op |
| 974 | output dec_flush_f1; // Flush f1 stage of the FGU |
| 975 | output dec_flush_f2; // Flush f2 stage of the FGU |
| 976 | output dec_flush_lm; // Flush the m stage of a load |
| 977 | output dec_flush_lb; // Flush the bypass stage of a load |
| 978 | output [1:0] dec_flush_m; // Flush the m stage of the ex units |
| 979 | output [1:0] dec_flush_b; // Flush the b stage of the ex units, also tlu |
| 980 | |
| 981 | output [7:0] dec_block_store_b; // block store at b stage to tlu |
| 982 | |
| 983 | // tlu interface |
| 984 | output [4:0] dec_exc0_m; // encoded exception status to tlu |
| 985 | output [4:0] dec_exc1_m; |
| 986 | output [1:0] dec_inst0_cnt; // inst cnt of e,m,b stage |
| 987 | output [1:0] dec_inst1_cnt; |
| 988 | output [1:0] dec_tid0_m; // thread id |
| 989 | output [1:0] dec_tid1_m; |
| 990 | output [1:0] dec_inst_valid_m; // inst is valid at m stage |
| 991 | output [1:0] dec_lsu_inst_m; // lsu inst at m stage |
| 992 | output [1:0] dec_fgu_inst_m; // fgu inst at m stage |
| 993 | output [1:0] dec_cti_inst_m; // fgu inst at m stage |
| 994 | |
| 995 | output [1:0] dec_illegal_inst_m; // illegal at m stage |
| 996 | output [1:0] dec_icache_perr_m; // icache parity error at m stage |
| 997 | output [1:0] dec_priv_exc_m; // priv exception at m stage |
| 998 | output [1:0] dec_hpriv_exc_m; // hypervison priv exception at m stage |
| 999 | output [1:0] dec_fpdisable_exc_m; // fp disable exception at m stage |
| 1000 | output [1:0] dec_br_taken_m; // br taken at m stage |
| 1001 | output [1:0] dec_done_inst_m; // done inst at m stage |
| 1002 | output [1:0] dec_retry_inst_m; // retry inst at m stage |
| 1003 | output [1:0] dec_sir_inst_m; // sir inst a m stage |
| 1004 | |
| 1005 | output [1:0] dec_ds_m; // this instruction is a DS |
| 1006 | output [1:0] dec_annul_ds_m; // DS at m stage is annulled |
| 1007 | |
| 1008 | output [1:0] dec_fgu_sel_e; // mux select between TG's for fgu ops |
| 1009 | output [1:0] dec_fgu_sel_m; // mux select between TG's for fgu ops |
| 1010 | |
| 1011 | output dec_lsu_sel0_e; // mux select between TG's for lsu ops |
| 1012 | output dec_lsu_sel1_e; |
| 1013 | |
| 1014 | output dec_rs1_addr0_e; |
| 1015 | output dec_rs1_addr1_e; |
| 1016 | |
| 1017 | output dec_lsu_sel0_upper_e; // mux select taking pstate AM into account |
| 1018 | output dec_lsu_sel1_upper_e; |
| 1019 | |
| 1020 | output dec_lsu_sel0_lower_e; // mux select taking pstate AM into account |
| 1021 | output dec_lsu_sel1_lower_e; |
| 1022 | |
| 1023 | output dec_rs1_addr0_upper_e; |
| 1024 | output dec_rs1_addr1_upper_e; |
| 1025 | |
| 1026 | |
| 1027 | output [7:0] del_pick_d; // picks to CCR logic |
| 1028 | |
| 1029 | // lsu interface |
| 1030 | output dec_ld_inst_e; // load inst |
| 1031 | output dec_st_inst_e; // store inst |
| 1032 | output dec_fsr_ldst_e; // LDFSR,STFSR |
| 1033 | output dec_fpldst_inst_e; // FP load or store inst |
| 1034 | output dec_ldst_dbl_e; // ldd inst |
| 1035 | output dec_pref_inst_e; // prefetch inst |
| 1036 | output dec_flush_inst_e; // flush inst |
| 1037 | output dec_memstbar_inst_e; // membar, stbar |
| 1038 | |
| 1039 | output dec_sr_inst_e; // ASR inst |
| 1040 | output dec_pr_inst_e; // priv inst |
| 1041 | output dec_hpr_inst_e; // hypervisor inst |
| 1042 | output dec_casa_inst_e; // CASA inst |
| 1043 | output dec_ldstub_inst_e; // LDSTUB inst |
| 1044 | output dec_swap_inst_e; // SWAP inst |
| 1045 | output dec_altspace_d; // Alternate space access |
| 1046 | output dec_sign_ext_e; // Sign extend lsu op |
| 1047 | output [4:0] dec_sraddr_e; // source address for ASR access |
| 1048 | output dec_imm_asi_vld_d; // immediate form of alternate access |
| 1049 | output [7:0] dec_imm_asi_d; // 8-bit ASI access |
| 1050 | output [1:0] dec_ldst_sz_e; // size of the ldst operation |
| 1051 | |
| 1052 | |
| 1053 | output dec_ld_inst_d; // load inst decoded |
| 1054 | |
| 1055 | output [1:0] dec_lsu_tid0_d; // tid for lsu operation |
| 1056 | output [1:0] dec_lsu_tid1_d; // tid for lsu operation |
| 1057 | output dec_lsu_tg_d; // tid for lsu operation |
| 1058 | output [4:0] dec_lsu_rd_e; // RD destination of lsu operation |
| 1059 | |
| 1060 | output del_test0_sel_p; // mux selects for IRF read port rs3 |
| 1061 | output del_twocycle0_std_p; |
| 1062 | output del_twocycle0_rs2_p; |
| 1063 | output del_default0_sel_p; |
| 1064 | |
| 1065 | output del_test1_sel_p; |
| 1066 | output del_twocycle1_std_p; |
| 1067 | output del_twocycle1_rs2_p; |
| 1068 | output del_default1_sel_p; |
| 1069 | |
| 1070 | output [4:0] del_test_addr0_p; // address to read for exu test access |
| 1071 | output [4:0] del_test_addr1_p; |
| 1072 | |
| 1073 | output [9:0] dec_instr0_type_d; // pmu stuff thread group 0 |
| 1074 | output [9:0] dec_instr1_type_d; // pmu stuff thread group 1 |
| 1075 | |
| 1076 | output [1:0] dec_exu_clken; // clk enable signals to the exu |
| 1077 | |
| 1078 | output [1:0] del_tg_clken; // clk enables for thread groups |
| 1079 | |
| 1080 | output scan_out; |
| 1081 | |
| 1082 | output [1:0] dec_true_valid_e; // take illegals and other exceptions into account |
| 1083 | |
| 1084 | output [1:0] dec_load_flush_w; |
| 1085 | |
| 1086 | output dec_lsu_sel0_d; // to the pmu to decide which tid to use for lsu at d stage |
| 1087 | |
| 1088 | output [7:0] dec_raw_pick_p; |
| 1089 | |
| 1090 | output [1:0] dec_ierr_d; // tell pku that an inst error has occurred: illegal, parity error or ifetch error |
| 1091 | |
| 1092 | output [7:0] dec_block_store_stall; // prevent window ops from coming too early after a block store |
| 1093 | |
| 1094 | dec_del_ctl_l1clkhdr_ctl_macro clkgen ( |
| 1095 | .l2clk(l2clk), |
| 1096 | .l1en (1'b1 ), |
| 1097 | .l1clk(l1clk), |
| 1098 | .pce_ov(pce_ov), |
| 1099 | .stop(stop), |
| 1100 | .se(se)); |
| 1101 | |
| 1102 | dec_del_ctl_spare_ctl_macro__flops_0__num_6 spares ( |
| 1103 | ); |
| 1104 | |
| 1105 | // bit 0 maps to spare0_flop |
| 1106 | dec_del_ctl_msff_ctl_macro__scanreverse_1__width_6 spare_5_0_lat ( |
| 1107 | .scan_in(spares_scanin), |
| 1108 | .scan_out(spares_scanout), |
| 1109 | .l1clk (l1clk), |
| 1110 | .din ({{3{1'b0}},pmu_valid_d[0],1'b0,pmu_valid_d[1]}), |
| 1111 | .dout ({spare_5_0_lat_unused[3:1],pmu_valid_e[0],spare_5_0_lat_unused[0],pmu_valid_e[1]}), |
| 1112 | .siclk(siclk), |
| 1113 | .soclk(soclk) |
| 1114 | ); |
| 1115 | |
| 1116 | // scan renames |
| 1117 | assign pce_ov = tcu_pce_ov; |
| 1118 | assign stop = 1'b0; |
| 1119 | assign siclk = spc_aclk; |
| 1120 | assign soclk = spc_bclk; |
| 1121 | assign se = tcu_scan_en; |
| 1122 | // end scan |
| 1123 | |
| 1124 | |
| 1125 | assign dec_load_flush_w[1:0] = { |pku_load_flush_w[7:4], |pku_load_flush_w[3:0] }; |
| 1126 | |
| 1127 | assign callinst0_d = dcd_callclass_d[0] & ~dec_inst0_b31; |
| 1128 | assign callinst1_d = dcd_callclass_d[1] & ~dec_inst1_b31; |
| 1129 | |
| 1130 | // for save/restore invert oddwin since rd is in the new window |
| 1131 | assign dec_inst0_rd_d[4] = (dec_inst0_raw_rd_d[4] & ~callinst0_d) ^ ((dec_inst0_raw_rd_d[3] | callinst0_d) & (ded_oddwin0_d ^ dcd_save_restore_d[0])); |
| 1132 | assign dec_inst0_rd_d[3:0] = dec_inst0_raw_rd_d[3:0] | {4{callinst0_d}}; |
| 1133 | |
| 1134 | assign dec_inst1_rd_d[4] = (dec_inst1_raw_rd_d[4] & ~callinst1_d) ^ ((dec_inst1_raw_rd_d[3] | callinst1_d) & (ded_oddwin1_d ^ dcd_save_restore_d[1])); |
| 1135 | assign dec_inst1_rd_d[3:0] = dec_inst1_raw_rd_d[3:0] | {4{callinst1_d}}; |
| 1136 | |
| 1137 | // predecodes for timing (make dec_decode* fast) |
| 1138 | |
| 1139 | // make sure twocycle is lsu to deal with illegal instructions (partial decodes) |
| 1140 | assign pdecode0_in[6:0] = { pku_idest_p[0],pku_fdest_p[0],pku_fsrc_rd_p[0],pku_lsu_p[0],pku_fgu_p[0], |
| 1141 | pku_pdist_p[0],pku_twocycle_p[0] & pku_lsu_p[0] }; |
| 1142 | |
| 1143 | assign pdecode1_in[6:0] = { pku_idest_p[1],pku_fdest_p[1],pku_fsrc_rd_p[1],pku_lsu_p[1],pku_fgu_p[1], |
| 1144 | pku_pdist_p[1],pku_twocycle_p[1] & pku_lsu_p[1] }; |
| 1145 | |
| 1146 | assign pdecode2_in[6:0] = { pku_idest_p[2],pku_fdest_p[2],pku_fsrc_rd_p[2],pku_lsu_p[2],pku_fgu_p[2], |
| 1147 | pku_pdist_p[2],pku_twocycle_p[2] & pku_lsu_p[2] }; |
| 1148 | |
| 1149 | assign pdecode3_in[6:0] = { pku_idest_p[3],pku_fdest_p[3],pku_fsrc_rd_p[3],pku_lsu_p[3],pku_fgu_p[3], |
| 1150 | pku_pdist_p[3],pku_twocycle_p[3] & pku_lsu_p[3] }; |
| 1151 | |
| 1152 | |
| 1153 | assign pdec0_in[6:0] = ({7{del_noshift0_d}} & pdecode0_d[6:0]) | |
| 1154 | ({7{~del_noshift0_d & pku_raw_pick0_p[0] & ded_legal_p[0] & ~ded_perr_p[0] & ~ded_ferr_p[0]}} & pdecode0_in[6:0]) | |
| 1155 | ({7{~del_noshift0_d & pku_raw_pick0_p[1] & ded_legal_p[0] & ~ded_perr_p[0] & ~ded_ferr_p[0]}} & pdecode1_in[6:0]) | |
| 1156 | ({7{~del_noshift0_d & pku_raw_pick0_p[2] & ded_legal_p[0] & ~ded_perr_p[0] & ~ded_ferr_p[0]}} & pdecode2_in[6:0]) | |
| 1157 | ({7{~del_noshift0_d & pku_raw_pick0_p[3] & ded_legal_p[0] & ~ded_perr_p[0] & ~ded_ferr_p[0]}} & pdecode3_in[6:0]); |
| 1158 | |
| 1159 | |
| 1160 | dec_del_ctl_msff_ctl_macro__width_7 pdecode0f ( |
| 1161 | .scan_in(pdecode0f_scanin), |
| 1162 | .scan_out(pdecode0f_scanout), |
| 1163 | .din(pdec0_in[6:0]), |
| 1164 | .dout(pdecode0_d[6:0]), |
| 1165 | .l1clk(l1clk), |
| 1166 | .siclk(siclk), |
| 1167 | .soclk(soclk) |
| 1168 | ); |
| 1169 | |
| 1170 | |
| 1171 | assign { idest0_d, fdest0_d, fsrc0_rd_d, lsu0_d, fgu0_d, pdist0_d, twocycle0_d } = pdecode0_d[6:0]; |
| 1172 | |
| 1173 | // make sure twocycle is lsu to deal with illegal instructions (partial decodes) |
| 1174 | assign pdecode4_in[6:0] = { pku_idest_p[4],pku_fdest_p[4],pku_fsrc_rd_p[4],pku_lsu_p[4],pku_fgu_p[4], |
| 1175 | pku_pdist_p[4],pku_twocycle_p[4] & pku_lsu_p[4] }; |
| 1176 | |
| 1177 | assign pdecode5_in[6:0] = { pku_idest_p[5],pku_fdest_p[5],pku_fsrc_rd_p[5],pku_lsu_p[5],pku_fgu_p[5], |
| 1178 | pku_pdist_p[5],pku_twocycle_p[5] & pku_lsu_p[5] }; |
| 1179 | |
| 1180 | assign pdecode6_in[6:0] = { pku_idest_p[6],pku_fdest_p[6],pku_fsrc_rd_p[6],pku_lsu_p[6],pku_fgu_p[6], |
| 1181 | pku_pdist_p[6],pku_twocycle_p[6] & pku_lsu_p[6] }; |
| 1182 | |
| 1183 | assign pdecode7_in[6:0] = { pku_idest_p[7],pku_fdest_p[7],pku_fsrc_rd_p[7],pku_lsu_p[7],pku_fgu_p[7], |
| 1184 | pku_pdist_p[7],pku_twocycle_p[7] & pku_lsu_p[7] }; |
| 1185 | |
| 1186 | assign pdec1_in[6:0] = ({7{del_noshift1_d}} & pdecode1_d[6:0]) | |
| 1187 | ({7{~del_noshift1_d & pku_raw_pick1_p[4] & ded_legal_p[1] & ~ded_perr_p[1] & ~ded_ferr_p[1]}} & pdecode4_in[6:0]) | |
| 1188 | ({7{~del_noshift1_d & pku_raw_pick1_p[5] & ded_legal_p[1] & ~ded_perr_p[1] & ~ded_ferr_p[1]}} & pdecode5_in[6:0]) | |
| 1189 | ({7{~del_noshift1_d & pku_raw_pick1_p[6] & ded_legal_p[1] & ~ded_perr_p[1] & ~ded_ferr_p[1]}} & pdecode6_in[6:0]) | |
| 1190 | ({7{~del_noshift1_d & pku_raw_pick1_p[7] & ded_legal_p[1] & ~ded_perr_p[1] & ~ded_ferr_p[1]}} & pdecode7_in[6:0]); |
| 1191 | |
| 1192 | |
| 1193 | dec_del_ctl_msff_ctl_macro__width_7 pdecode1f ( |
| 1194 | .scan_in(pdecode1f_scanin), |
| 1195 | .scan_out(pdecode1f_scanout), |
| 1196 | .din(pdec1_in[6:0]), |
| 1197 | .dout(pdecode1_d[6:0]), |
| 1198 | .l1clk(l1clk), |
| 1199 | .siclk(siclk), |
| 1200 | .soclk(soclk) |
| 1201 | ); |
| 1202 | |
| 1203 | |
| 1204 | assign { idest1_d, fdest1_d, fsrc1_rd_d, lsu1_d, fgu1_d, pdist1_d, twocycle1_d } = pdecode1_d[6:0]; |
| 1205 | |
| 1206 | |
| 1207 | |
| 1208 | assign final_pick_p[3:0] = pku_base_pick_p[3:0] & {4{~(dec_valid0_d & ~dec_decode0_d)}}; |
| 1209 | assign final_pick_p[7:4] = pku_base_pick_p[7:4] & {4{~(dec_valid1_d & ~dec_decode1_d)}}; |
| 1210 | |
| 1211 | |
| 1212 | assign shift0_d = ~del_noshift0_d; |
| 1213 | |
| 1214 | assign raw_pick0_in[3:0] = ({4{shift0_d}} & pku_raw_pick0_p[3:0]) | |
| 1215 | ({4{~shift0_d}} & pick0_d[3:0]); |
| 1216 | |
| 1217 | assign pick0_in[3:0] = ({4{shift0_d}} & final_pick_p[3:0]) | |
| 1218 | ({4{~shift0_d}} & pick0_d[3:0]); |
| 1219 | |
| 1220 | dec_del_ctl_msff_ctl_macro__width_4 pick0f ( |
| 1221 | .scan_in(pick0f_scanin), |
| 1222 | .scan_out(pick0f_scanout), |
| 1223 | .l1clk(l1clk), |
| 1224 | .din (pick0_in[3:0]), |
| 1225 | .dout (pick0_d[3:0]), |
| 1226 | .siclk(siclk), |
| 1227 | .soclk(soclk) |
| 1228 | ); |
| 1229 | |
| 1230 | assign shift1_d = ~del_noshift1_d; |
| 1231 | |
| 1232 | assign raw_pick1_in[3:0] = ({4{shift1_d}} & pku_raw_pick1_p[7:4]) | |
| 1233 | ({4{~shift1_d}} & pick1_d[3:0]); |
| 1234 | |
| 1235 | assign pick1_in[3:0] = ({4{shift1_d}} & final_pick_p[7:4]) | |
| 1236 | ({4{~shift1_d}} & pick1_d[3:0]); |
| 1237 | |
| 1238 | dec_del_ctl_msff_ctl_macro__width_4 pick1f ( |
| 1239 | .scan_in(pick1f_scanin), |
| 1240 | .scan_out(pick1f_scanout), |
| 1241 | .l1clk(l1clk), |
| 1242 | .din (pick1_in[3:0]), |
| 1243 | .dout (pick1_d[3:0]), |
| 1244 | .siclk(siclk), |
| 1245 | .soclk(soclk) |
| 1246 | ); |
| 1247 | |
| 1248 | assign dec_raw_pick_p[7:0] = {raw_pick1_in[3:0], raw_pick0_in[3:0]}; |
| 1249 | |
| 1250 | dec_del_ctl_msff_ctl_macro__width_16 privstatef ( |
| 1251 | .scan_in(privstatef_scanin), |
| 1252 | .scan_out(privstatef_scanout), |
| 1253 | .l1clk(l1clk), |
| 1254 | .din ({tlu_dec_pstate_priv[7:0],tlu_dec_hpstate_hpriv[7:0]}), |
| 1255 | .dout ({tlu_priv[7:0],tlu_hpriv[7:0]}), |
| 1256 | .siclk(siclk), |
| 1257 | .soclk(soclk) |
| 1258 | ); |
| 1259 | |
| 1260 | dec_del_ctl_msff_ctl_macro__width_16 fef ( |
| 1261 | .scan_in(fef_scanin), |
| 1262 | .scan_out(fef_scanout), |
| 1263 | .l1clk(l1clk), |
| 1264 | .din ({tlu_dec_pstate_pef[7:0],fgu_fprs_fef[7:0]}), |
| 1265 | .dout ({tlu_pef[7:0],fgu_fef[7:0]}), |
| 1266 | .siclk(siclk), |
| 1267 | .soclk(soclk) |
| 1268 | ); |
| 1269 | |
| 1270 | // priv bits from the tlu |
| 1271 | assign priv_d[0] = |(pick0_d[3:0] & tlu_priv[3:0]); |
| 1272 | assign hpriv_d[0] = |(pick0_d[3:0] & tlu_hpriv[3:0]); |
| 1273 | assign fpdis_d[0] = |(pick0_d[3:0] & ~(tlu_pef[3:0] & fgu_fef[3:0])); |
| 1274 | |
| 1275 | assign priv_d[1] = |(pick1_d[3:0] & tlu_priv[7:4]); |
| 1276 | assign hpriv_d[1] = |(pick1_d[3:0] & tlu_hpriv[7:4]); |
| 1277 | assign fpdis_d[1] = |(pick1_d[3:0] & ~(tlu_pef[7:4] & fgu_fef[7:4])); |
| 1278 | |
| 1279 | assign del_pick_d[3:0] = pick0_d[3:0]; |
| 1280 | assign del_pick_d[7:4] = pick1_d[3:0]; |
| 1281 | |
| 1282 | |
| 1283 | |
| 1284 | assign inst0_cnt_brtaken0[1:0] = ({2{raw_pick0_in[3]}} & pku_inst_cnt_brtaken03[1:0]) | |
| 1285 | ({2{raw_pick0_in[2]}} & pku_inst_cnt_brtaken02[1:0]) | |
| 1286 | ({2{raw_pick0_in[1]}} & pku_inst_cnt_brtaken01[1:0]) | |
| 1287 | ({2{raw_pick0_in[0]}} & pku_inst_cnt_brtaken00[1:0]); |
| 1288 | |
| 1289 | assign inst0_cnt_brtaken1[1:0] = ({2{raw_pick0_in[3]}} & pku_inst_cnt_brtaken13[1:0]) | |
| 1290 | ({2{raw_pick0_in[2]}} & pku_inst_cnt_brtaken12[1:0]) | |
| 1291 | ({2{raw_pick0_in[1]}} & pku_inst_cnt_brtaken11[1:0]) | |
| 1292 | ({2{raw_pick0_in[0]}} & pku_inst_cnt_brtaken10[1:0]); |
| 1293 | |
| 1294 | assign inst1_cnt_brtaken0[1:0] = ({2{raw_pick1_in[3]}} & pku_inst_cnt_brtaken07[1:0]) | |
| 1295 | ({2{raw_pick1_in[2]}} & pku_inst_cnt_brtaken06[1:0]) | |
| 1296 | ({2{raw_pick1_in[1]}} & pku_inst_cnt_brtaken05[1:0]) | |
| 1297 | ({2{raw_pick1_in[0]}} & pku_inst_cnt_brtaken04[1:0]); |
| 1298 | |
| 1299 | assign inst1_cnt_brtaken1[1:0] = ({2{raw_pick1_in[3]}} & pku_inst_cnt_brtaken17[1:0]) | |
| 1300 | ({2{raw_pick1_in[2]}} & pku_inst_cnt_brtaken16[1:0]) | |
| 1301 | ({2{raw_pick1_in[1]}} & pku_inst_cnt_brtaken15[1:0]) | |
| 1302 | ({2{raw_pick1_in[0]}} & pku_inst_cnt_brtaken14[1:0]); |
| 1303 | |
| 1304 | assign br_taken_e[1:0] = dec_br_taken_e1[1:0] & dec_valid_e[1:0] & ~ifetch_err_e[1:0]; |
| 1305 | |
| 1306 | assign inst0_cnt[1:0] = ({2{~br_taken_e[0]}} & inst0_cnt_brtaken0[1:0]) | |
| 1307 | ({2{ br_taken_e[0]}} & inst0_cnt_brtaken1[1:0]); |
| 1308 | |
| 1309 | assign inst1_cnt[1:0] = ({2{~br_taken_e[1]}} & inst1_cnt_brtaken0[1:0]) | |
| 1310 | ({2{ br_taken_e[1]}} & inst1_cnt_brtaken1[1:0]); |
| 1311 | |
| 1312 | |
| 1313 | // send inst cnt directly off flop to tlu |
| 1314 | dec_del_ctl_msff_ctl_macro__width_4 instcntf ( |
| 1315 | .scan_in(instcntf_scanin), |
| 1316 | .scan_out(instcntf_scanout), |
| 1317 | .l1clk(l1clk), |
| 1318 | .din ({inst0_cnt[1:0],inst1_cnt[1:0]}), |
| 1319 | .dout ({dec_inst0_cnt[1:0],dec_inst1_cnt[1:0]}), |
| 1320 | .siclk(siclk), |
| 1321 | .soclk(soclk) |
| 1322 | ); |
| 1323 | |
| 1324 | dec_del_ctl_msff_ctl_macro__width_16 exutestf ( |
| 1325 | .scan_in(exutestf_scanin), |
| 1326 | .scan_out(exutestf_scanout), |
| 1327 | .l1clk(l1clk), |
| 1328 | .din ({exu_test_tid0[1:0],exu_test_tid1[1:0],exu_test_addr0[4:0],exu_test_addr1[4:0],exu_test_valid0,exu_test_valid1}), |
| 1329 | .dout ({ttid0_p[1:0],ttid1_p[1:0],del_test_addr0_p[4:0],del_test_addr1_p[4:0],test_stall0_in,test_stall1_in}), |
| 1330 | .siclk(siclk), |
| 1331 | .soclk(soclk) |
| 1332 | ); |
| 1333 | |
| 1334 | dec_del_ctl_msff_ctl_macro__width_2 teststallf ( |
| 1335 | .scan_in(teststallf_scanin), |
| 1336 | .scan_out(teststallf_scanout), |
| 1337 | .l1clk(l1clk), |
| 1338 | .din ({test_stall0_in,test_stall1_in}), |
| 1339 | .dout ({test_stall0,test_stall1}), |
| 1340 | .siclk(siclk), |
| 1341 | .soclk(soclk) |
| 1342 | ); |
| 1343 | |
| 1344 | // DEC must select the correct register to send to LSU in the second cycle of a twocycle op. |
| 1345 | // For STD, the register is Rs3+1 |
| 1346 | // For CASA, the register is Rs2 |
| 1347 | assign del_test0_sel_p = test_stall0_in; |
| 1348 | assign del_twocycle0_std_p = twocycle_p[0] & ~dec_inst0_op3_d[3] & ~test_stall0_in; |
| 1349 | assign del_twocycle0_rs2_p = twocycle_p[0] & dec_inst0_op3_d[3] & ~test_stall0_in; |
| 1350 | assign twocycle0_sel_p = twocycle_p[0] & ~test_stall0_in; |
| 1351 | assign del_default0_sel_p = ~test_stall0_in & ~twocycle_p[0]; |
| 1352 | |
| 1353 | assign del_test1_sel_p = test_stall1_in; |
| 1354 | assign del_twocycle1_std_p = twocycle_p[1] & ~dec_inst1_op3_d[3] & ~test_stall1_in; |
| 1355 | assign del_twocycle1_rs2_p = twocycle_p[1] & dec_inst1_op3_d[3] & ~test_stall1_in; |
| 1356 | assign twocycle1_sel_p = twocycle_p[1] & ~test_stall1_in; |
| 1357 | assign del_default1_sel_p = ~test_stall1_in & ~twocycle_p[1]; |
| 1358 | |
| 1359 | // generate tid's to the EXU |
| 1360 | assign tid0_p[1] = ~raw_pick0_in[1] & ~raw_pick0_in[0]; |
| 1361 | assign tid0_p[0] = ~raw_pick0_in[2] & ~raw_pick0_in[0]; |
| 1362 | |
| 1363 | assign tid1_p[1] = ~raw_pick1_in[1] & ~raw_pick1_in[0]; |
| 1364 | assign tid1_p[0] = ~raw_pick1_in[2] & ~raw_pick1_in[0]; |
| 1365 | |
| 1366 | // force the same tid for twocycle operations (std,casa,pst) |
| 1367 | assign dec_tid0_p[1:0] = ({2{del_default0_sel_p}} & tid0_p[1:0]) | |
| 1368 | ({2{twocycle0_sel_p}} & tid0_d[1:0]) | |
| 1369 | ({2{del_test0_sel_p}} & ttid0_p[1:0]); |
| 1370 | |
| 1371 | assign dec_tid1_p[1:0] = ({2{del_default1_sel_p}} & tid1_p[1:0]) | |
| 1372 | ({2{twocycle1_sel_p}} & tid1_d[1:0]) | |
| 1373 | ({2{del_test1_sel_p}} & ttid1_p[1:0]); |
| 1374 | |
| 1375 | // technically we dont need to clear the valid_d's for br_mispredict, trap flush or load flush |
| 1376 | // we will never get a dec_valid_e for these cases |
| 1377 | // clear it anyway |
| 1378 | |
| 1379 | // flop tlu_flush_ifu if it don't make timing |
| 1380 | assign valid_d_in[3:0] = (pku_base_pick_p[3:0] | (valid_d[3:0] & ~{4{dec_decode0_d}})) & ~tlu_flush_ifu[3:0] & ~pku_load_flush_w[3:0]; |
| 1381 | assign valid_d_in[7:4] = (pku_base_pick_p[7:4] | (valid_d[7:4] & ~{4{dec_decode1_d}})) & ~tlu_flush_ifu[7:4] & ~pku_load_flush_w[7:4]; |
| 1382 | |
| 1383 | dec_del_ctl_msff_ctl_macro__width_8 val_df ( |
| 1384 | .scan_in(val_df_scanin), |
| 1385 | .scan_out(val_df_scanout), |
| 1386 | .l1clk(l1clk), |
| 1387 | .din (valid_d_in[7:0]), |
| 1388 | .dout (valid_d[7:0]), |
| 1389 | .siclk(siclk), |
| 1390 | .soclk(soclk) |
| 1391 | ); |
| 1392 | |
| 1393 | // for speed, have dec_valid0,1_d come off flop |
| 1394 | assign valid0_d_in = |valid_d_in[3:0]; |
| 1395 | assign valid1_d_in = |valid_d_in[7:4]; |
| 1396 | |
| 1397 | dec_del_ctl_msff_ctl_macro__width_2 valid_df ( |
| 1398 | .scan_in(valid_df_scanin), |
| 1399 | .scan_out(valid_df_scanout), |
| 1400 | .l1clk(l1clk), |
| 1401 | .din ({valid0_d_in,valid1_d_in}), |
| 1402 | .dout ({valid0_d,valid1_d}), |
| 1403 | .siclk(siclk), |
| 1404 | .soclk(soclk) |
| 1405 | ); |
| 1406 | |
| 1407 | assign dec_valid0_d = valid0_d; |
| 1408 | assign dec_valid1_d = valid1_d; |
| 1409 | |
| 1410 | dec_del_ctl_msff_ctl_macro__width_2 dtlb_reloadf ( |
| 1411 | .scan_in(dtlb_reloadf_scanin), |
| 1412 | .scan_out(dtlb_reloadf_scanout), |
| 1413 | .l1clk(l1clk), |
| 1414 | .din ({tlu_dtlb_reload_stall,dtlb_reload[1]}), |
| 1415 | .dout (dtlb_reload[1:0]), |
| 1416 | .siclk(siclk), |
| 1417 | .soclk(soclk) |
| 1418 | ); |
| 1419 | |
| 1420 | assign dtlb_reload_stall = |dtlb_reload[1:0]; |
| 1421 | |
| 1422 | |
| 1423 | // we delay 1 cycle to give time to any STD's or PDIST's that might be going on |
| 1424 | dec_del_ctl_msff_ctl_macro__width_1 block_store0f ( |
| 1425 | .scan_in(block_store0f_scanin), |
| 1426 | .scan_out(block_store0f_scanout), |
| 1427 | .l1clk(l1clk), |
| 1428 | .din (lsu_block_store_stall), |
| 1429 | .dout (pre_block_store_stall), |
| 1430 | .siclk(siclk), |
| 1431 | .soclk(soclk) |
| 1432 | ); |
| 1433 | |
| 1434 | |
| 1435 | assign block_store_stall_in = (block_store_stall | pre_block_store_stall) & ~reset_block_store_stall; |
| 1436 | |
| 1437 | dec_del_ctl_msff_ctl_macro__width_1 block_storef ( |
| 1438 | .scan_in(block_storef_scanin), |
| 1439 | .scan_out(block_storef_scanout), |
| 1440 | .l1clk(l1clk), |
| 1441 | .din (block_store_stall_in), |
| 1442 | .dout (block_store_stall), |
| 1443 | .siclk(siclk), |
| 1444 | .soclk(soclk) |
| 1445 | ); |
| 1446 | |
| 1447 | assign block_store_rd_in[4:3] = ({2{lsu_block_store_stall}} & lsu_block_store_rd[4:3]) | |
| 1448 | ({2{~lsu_block_store_stall}} & block_store_rd[4:3]); |
| 1449 | |
| 1450 | dec_del_ctl_msff_ctl_macro__width_2 block_store_rdhif ( |
| 1451 | .scan_in(block_store_rdhif_scanin), |
| 1452 | .scan_out(block_store_rdhif_scanout), |
| 1453 | .l1clk(l1clk), |
| 1454 | .din (block_store_rd_in[4:3]), |
| 1455 | .dout (block_store_rd[4:3]), |
| 1456 | .siclk(siclk), |
| 1457 | .soclk(soclk) |
| 1458 | ); |
| 1459 | |
| 1460 | // pre_block_store_stall must reset the count for the case where the sequence is restarted |
| 1461 | assign block_store_rd_in[2:0] = ({3{block_store_stall}} & (block_store_rd[2:0]+3'b001)) & |
| 1462 | ({3{~pre_block_store_stall}}); |
| 1463 | |
| 1464 | dec_del_ctl_msff_ctl_macro__width_3 block_store_rdlof ( |
| 1465 | .scan_in(block_store_rdlof_scanin), |
| 1466 | .scan_out(block_store_rdlof_scanout), |
| 1467 | .l1clk(l1clk), |
| 1468 | .din (block_store_rd_in[2:0]), |
| 1469 | .dout (block_store_rd[2:0]), |
| 1470 | .siclk(siclk), |
| 1471 | .soclk(soclk) |
| 1472 | ); |
| 1473 | |
| 1474 | assign block_store_tid_in[2:0] = ({3{lsu_block_store_stall}} & lsu_block_store_tid[2:0]) | |
| 1475 | ({3{~lsu_block_store_stall}} & block_store_tid[2:0]); |
| 1476 | |
| 1477 | dec_del_ctl_msff_ctl_macro__width_3 block_store_tidf ( |
| 1478 | .scan_in(block_store_tidf_scanin), |
| 1479 | .scan_out(block_store_tidf_scanout), |
| 1480 | .l1clk(l1clk), |
| 1481 | .din (block_store_tid_in[2:0]), |
| 1482 | .dout (block_store_tid[2:0]), |
| 1483 | .siclk(siclk), |
| 1484 | .soclk(soclk) |
| 1485 | ); |
| 1486 | |
| 1487 | assign block_store_stall0 = (block_store_stall | pre_block_store_stall) & ~block_store_tid[2]; |
| 1488 | |
| 1489 | assign block_store_stall1 = (block_store_stall | pre_block_store_stall) & block_store_tid[2]; |
| 1490 | |
| 1491 | // prevent window ops from coming too early after a block store |
| 1492 | // it is possible for the 8th beat to have an ecc exception |
| 1493 | // for this type of exception, tlu may take an extra cycle before signalling flush |
| 1494 | |
| 1495 | // must reset the dec_block_store_stall with pre_block_store_stall in case the sequence is restarted |
| 1496 | assign dec_block_store_stall[7:0] = {8{block_store_stall}} & {block_store_tid[2:0] == 3'b111, |
| 1497 | block_store_tid[2:0] == 3'b110, |
| 1498 | block_store_tid[2:0] == 3'b101, |
| 1499 | block_store_tid[2:0] == 3'b100, |
| 1500 | block_store_tid[2:0] == 3'b011, |
| 1501 | block_store_tid[2:0] == 3'b010, |
| 1502 | block_store_tid[2:0] == 3'b001, |
| 1503 | block_store_tid[2:0] == 3'b000} & {8{~pre_block_store_stall}}; |
| 1504 | |
| 1505 | |
| 1506 | assign cpq_stall_in = lsu_cpq_stall; |
| 1507 | |
| 1508 | dec_del_ctl_msff_ctl_macro__width_1 cpq_stallf ( |
| 1509 | .scan_in(cpq_stallf_scanin), |
| 1510 | .scan_out(cpq_stallf_scanout), |
| 1511 | .l1clk(l1clk), |
| 1512 | .din (cpq_stall_in), |
| 1513 | .dout (cpq_stall), |
| 1514 | .siclk(siclk), |
| 1515 | .soclk(soclk) |
| 1516 | ); |
| 1517 | |
| 1518 | assign fecc_stall_in = fgu_ecc_asi_stall; |
| 1519 | |
| 1520 | dec_del_ctl_msff_ctl_macro__width_1 fecc_stallf ( |
| 1521 | .scan_in(fecc_stallf_scanin), |
| 1522 | .scan_out(fecc_stallf_scanout), |
| 1523 | .l1clk(l1clk), |
| 1524 | .din (fecc_stall_in), |
| 1525 | .dout (fecc_stall), |
| 1526 | .siclk(siclk), |
| 1527 | .soclk(soclk) |
| 1528 | ); |
| 1529 | |
| 1530 | // no need to make this flushable because it is not speculative ... |
| 1531 | // we always wait 1 cycle before starting the block store to allow prior twocycle operations |
| 1532 | dec_del_ctl_msff_ctl_macro__width_3 block_resetf ( |
| 1533 | .scan_in(block_resetf_scanin), |
| 1534 | .scan_out(block_resetf_scanout), |
| 1535 | .l1clk(l1clk), |
| 1536 | .din (block_rst_cnt_in[2:0]), |
| 1537 | .dout (block_rst_cnt[2:0]), |
| 1538 | .siclk(siclk), |
| 1539 | .soclk(soclk) |
| 1540 | ); |
| 1541 | |
| 1542 | // pre_block_store_stall must reset the count for the case where the sequence is restarted |
| 1543 | assign block_rst_cnt_in[2:0] = ({3{block_store_stall}} & (block_rst_cnt[2:0]+3'b001)) & |
| 1544 | ({3{~pre_block_store_stall}}); |
| 1545 | assign reset_block_store_stall = &(block_rst_cnt[2:0]); |
| 1546 | |
| 1547 | // generate dec_block_store_b[7:0] to tlu to reduce routes |
| 1548 | |
| 1549 | dec_del_ctl_msff_ctl_macro__width_4 block_store_e ( |
| 1550 | .scan_in(block_store_e_scanin), |
| 1551 | .scan_out(block_store_e_scanout), |
| 1552 | .l1clk(l1clk), |
| 1553 | .din ({block_store_stall,block_store_tid[2:0]}), |
| 1554 | .dout ({block_store_stall_e,block_store_tid_e[2:0]}), |
| 1555 | .siclk(siclk), |
| 1556 | .soclk(soclk) |
| 1557 | ); |
| 1558 | |
| 1559 | dec_del_ctl_msff_ctl_macro__width_4 block_store_m ( |
| 1560 | .scan_in(block_store_m_scanin), |
| 1561 | .scan_out(block_store_m_scanout), |
| 1562 | .l1clk(l1clk), |
| 1563 | .din ({block_store_stall_e,block_store_tid_e[2:0]}), |
| 1564 | .dout ({block_store_stall_m,block_store_tid_m[2:0]}), |
| 1565 | .siclk(siclk), |
| 1566 | .soclk(soclk) |
| 1567 | ); |
| 1568 | |
| 1569 | dec_del_ctl_msff_ctl_macro__width_4 block_store_b ( |
| 1570 | .scan_in(block_store_b_scanin), |
| 1571 | .scan_out(block_store_b_scanout), |
| 1572 | .l1clk(l1clk), |
| 1573 | .din ({block_store_stall_m,block_store_tid_m[2:0]}), |
| 1574 | .dout ({block_store_stall_b,block_store_tid_b[2:0]}), |
| 1575 | .siclk(siclk), |
| 1576 | .soclk(soclk) |
| 1577 | ); |
| 1578 | |
| 1579 | assign dec_block_store_b[0] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b000); |
| 1580 | assign dec_block_store_b[1] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b001); |
| 1581 | assign dec_block_store_b[2] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b010); |
| 1582 | assign dec_block_store_b[3] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b011); |
| 1583 | assign dec_block_store_b[4] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b100); |
| 1584 | assign dec_block_store_b[5] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b101); |
| 1585 | assign dec_block_store_b[6] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b110); |
| 1586 | assign dec_block_store_b[7] = block_store_stall_b && (block_store_tid_b[2:0] == 3'b111); |
| 1587 | |
| 1588 | |
| 1589 | |
| 1590 | |
| 1591 | // favor bits: only toggle when the relevant conflict is decided one way or the other |
| 1592 | |
| 1593 | // load favor bit (which load to favor in case of two loads) |
| 1594 | // harden illegals |
| 1595 | assign set_lfavor = (dec_decode0_d & lsusel0_d & lsu0_d & lsu1_d & dec_valid1_d & ~(fgu0_d & fgu1_d)); |
| 1596 | assign reset_lfavor = (dec_decode1_d & ~lsusel0_d & lsu0_d & lsu1_d & dec_valid0_d & ~(fgu0_d & fgu1_d)); |
| 1597 | |
| 1598 | assign lfavor_in = (lfavor | set_lfavor) & ~reset_lfavor; |
| 1599 | dec_del_ctl_msff_ctl_macro__width_1 lfavorf ( |
| 1600 | .scan_in(lfavorf_scanin), |
| 1601 | .scan_out(lfavorf_scanout), |
| 1602 | .l1clk(l1clk), |
| 1603 | .din (lfavor_in), |
| 1604 | .dout (lfavor), |
| 1605 | .siclk(siclk), |
| 1606 | .soclk(soclk) |
| 1607 | ); |
| 1608 | |
| 1609 | // fpu favor bit (which fpu to favor in case of two fpus) |
| 1610 | // harden illegals |
| 1611 | assign set_ffavor = (dec_decode0_d & fgusel0_d & fgu0_d & fgu1_d & dec_valid1_d & ~(lsu0_d & lsu1_d)); |
| 1612 | assign reset_ffavor = (dec_decode1_d & ~fgusel0_d & fgu0_d & fgu1_d & dec_valid0_d & ~(lsu0_d & lsu1_d)); |
| 1613 | |
| 1614 | assign ffavor_in = (ffavor | set_ffavor) & ~reset_ffavor; |
| 1615 | dec_del_ctl_msff_ctl_macro__width_1 ffavorf ( |
| 1616 | .scan_in(ffavorf_scanin), |
| 1617 | .scan_out(ffavorf_scanout), |
| 1618 | .l1clk(l1clk), |
| 1619 | .din (ffavor_in), |
| 1620 | .dout (ffavor), |
| 1621 | .siclk(siclk), |
| 1622 | .soclk(soclk) |
| 1623 | ); |
| 1624 | |
| 1625 | // store-float favor bit (which store-float to favor in case of two store-floats) |
| 1626 | assign set_sffavor = (dec_decode0_d & lsu_float_case & dec_valid1_d); |
| 1627 | assign reset_sffavor = (dec_decode1_d & lsu_float_case & dec_valid0_d); |
| 1628 | |
| 1629 | assign sffavor_in = (sffavor | set_sffavor) & ~reset_sffavor; |
| 1630 | dec_del_ctl_msff_ctl_macro__width_1 sffavorf ( |
| 1631 | .scan_in(sffavorf_scanin), |
| 1632 | .scan_out(sffavorf_scanout), |
| 1633 | .l1clk(l1clk), |
| 1634 | .din (sffavor_in), |
| 1635 | .dout (sffavor), |
| 1636 | .siclk(siclk), |
| 1637 | .soclk(soclk) |
| 1638 | ); |
| 1639 | |
| 1640 | // remember mult request; not flushable |
| 1641 | assign mult_request_in = (spu_mult_request & (~mult_request | (mult_request & dec_spu_grant_d))) | |
| 1642 | (mult_request & ~dec_spu_grant_d); |
| 1643 | |
| 1644 | dec_del_ctl_msff_ctl_macro__width_1 mulrequestf ( |
| 1645 | .scan_in(mulrequestf_scanin), |
| 1646 | .scan_out(mulrequestf_scanout), |
| 1647 | .l1clk(l1clk), |
| 1648 | .din (mult_request_in), |
| 1649 | .dout (mult_request), |
| 1650 | .siclk(siclk), |
| 1651 | .soclk(soclk) |
| 1652 | ); |
| 1653 | |
| 1654 | // if you have crypto mult case and crypto mult is not favored; it must wait for cmfavor bit to toggle |
| 1655 | |
| 1656 | // harden for illegals |
| 1657 | assign crypto_mult_case0 = (mult_request & fgusel0_d & fgu0_d & dec_valid0_d); |
| 1658 | assign crypto_mult_case1 = (mult_request & ~fgusel0_d & fgu1_d & dec_valid1_d); |
| 1659 | |
| 1660 | // if the core wins; favor the crypto multiply next time |
| 1661 | assign set_cmfavor = (dec_decode0_d & crypto_mult_case0) | |
| 1662 | (dec_decode1_d & crypto_mult_case1); |
| 1663 | |
| 1664 | // reset the cmfavor bit if you win it clean |
| 1665 | assign reset_cmfavor = (cmfavor & cmfavor_grant_d & (crypto_mult_case0 | crypto_mult_case1)); |
| 1666 | |
| 1667 | // grant the mult_request if you are favored or ~favored but nothing else wants the fgu |
| 1668 | // have we covered all things that want the fgu ???? |
| 1669 | // never grant spu if second cycle of a pdist |
| 1670 | // never grant spu if we are doing a block store |
| 1671 | // dont give spu_grant if fgu has created an idiv hole in the pipe |
| 1672 | |
| 1673 | assign idiv_hole_d = |idiv_stall_d[1:0]; |
| 1674 | |
| 1675 | assign cmfavor_grant_d = mult_request & ~idiv_hole_d & ~pdistblock_d & |
| 1676 | ~(block_store_stall | pre_block_store_stall); |
| 1677 | |
| 1678 | assign dec_spu_grant_d = (cmfavor & cmfavor_grant_d) | |
| 1679 | (~cmfavor & mult_request & ~idiv_hole_d & ~crypto_mult_case0 & |
| 1680 | ~crypto_mult_case1 & ~pdistblock_d & |
| 1681 | ~(block_store_stall | pre_block_store_stall)); |
| 1682 | |
| 1683 | assign dec_spu_grant_fgu_d = dec_spu_grant_d; // clone copy to fgu |
| 1684 | |
| 1685 | assign cmfavor_in = (cmfavor | set_cmfavor) & ~reset_cmfavor; |
| 1686 | |
| 1687 | dec_del_ctl_msff_ctl_macro__width_1 cmfavorf ( |
| 1688 | .scan_in(cmfavorf_scanin), |
| 1689 | .scan_out(cmfavorf_scanout), |
| 1690 | .l1clk(l1clk), |
| 1691 | .din (cmfavor_in), |
| 1692 | .dout (cmfavor), |
| 1693 | .siclk(siclk), |
| 1694 | .soclk(soclk) |
| 1695 | ); |
| 1696 | |
| 1697 | // harden for illegals |
| 1698 | assign pdistblock_in[1:0] = { (pdist1_d & ~fgusel0_d & dec_decode1_d), |
| 1699 | (pdist0_d & fgusel0_d & dec_decode0_d) }; |
| 1700 | |
| 1701 | dec_del_ctl_msff_ctl_macro__width_2 pdistblockf ( |
| 1702 | .scan_in(pdistblockf_scanin), |
| 1703 | .scan_out(pdistblockf_scanout), |
| 1704 | .l1clk(l1clk), |
| 1705 | .din (pdistblock_in[1:0]), |
| 1706 | .dout (pdistblock[1:0]), |
| 1707 | .siclk(siclk), |
| 1708 | .soclk(soclk) |
| 1709 | ); |
| 1710 | |
| 1711 | // pdist from either thread group |
| 1712 | assign pdistblock_d = |pdistblock[1:0]; |
| 1713 | |
| 1714 | // remember the rd of the pdist |
| 1715 | dec_del_ctl_msff_ctl_macro__width_5 pdistrdf ( |
| 1716 | .scan_in(pdistrdf_scanin), |
| 1717 | .scan_out(pdistrdf_scanout), |
| 1718 | .l1clk(l1clk), |
| 1719 | .din (dec_frf_w_addr_d[4:0]), |
| 1720 | .dout (pdist_rd[4:0]), |
| 1721 | .siclk(siclk), |
| 1722 | .soclk(soclk) |
| 1723 | ); |
| 1724 | |
| 1725 | dec_del_ctl_msff_ctl_macro__width_3 pdisttidf ( |
| 1726 | .scan_in(pdisttidf_scanin), |
| 1727 | .scan_out(pdisttidf_scanout), |
| 1728 | .l1clk(l1clk), |
| 1729 | .din (dec_fgu_tid_d[2:0]), |
| 1730 | .dout (pdist_tid[2:0]), |
| 1731 | .siclk(siclk), |
| 1732 | .soclk(soclk) |
| 1733 | ); |
| 1734 | |
| 1735 | // STD blocks on the second cycle |
| 1736 | // STD is atomic; both reads are back-to-back |
| 1737 | assign twocycle0_d_in = (twocycle0_d & dec_decode0_d); |
| 1738 | |
| 1739 | dec_del_ctl_msff_ctl_macro__width_1 twocycle0_df ( |
| 1740 | .scan_in(twocycle0_df_scanin), |
| 1741 | .scan_out(twocycle0_df_scanout), |
| 1742 | .l1clk(l1clk), |
| 1743 | .din (twocycle0_d_in), |
| 1744 | .dout (twocycle0_stall), |
| 1745 | .siclk(siclk), |
| 1746 | .soclk(soclk) |
| 1747 | ); |
| 1748 | |
| 1749 | assign twocycle1_d_in = (twocycle1_d & dec_decode1_d); |
| 1750 | |
| 1751 | dec_del_ctl_msff_ctl_macro__width_1 twocycle1_df ( |
| 1752 | .scan_in(twocycle1_df_scanin), |
| 1753 | .scan_out(twocycle1_df_scanout), |
| 1754 | .l1clk(l1clk), |
| 1755 | .din (twocycle1_d_in), |
| 1756 | .dout (twocycle1_stall), |
| 1757 | .siclk(siclk), |
| 1758 | .soclk(soclk) |
| 1759 | ); |
| 1760 | |
| 1761 | // 0in assert -var (~(twocycle0_stall & twocycle1_stall)) -message "twocycle0_stall and twocycle1_stall must be mutually exclusive" |
| 1762 | |
| 1763 | assign twocycle_p[1:0] = { twocycle1_d_in, twocycle0_d_in }; |
| 1764 | |
| 1765 | // create a "hole" for integer ops executed by the fgu |
| 1766 | assign int_hole0_in = (fgu0_d & idest0_d & dec_decode0_d) | idiv_stall_d[0]; |
| 1767 | |
| 1768 | dec_del_ctl_msff_ctl_macro__width_3 inthole0_df ( |
| 1769 | .scan_in(inthole0_df_scanin), |
| 1770 | .scan_out(inthole0_df_scanout), |
| 1771 | .l1clk(l1clk), |
| 1772 | .din ({int_hole0_in,int_hole0_stall[2:1]}), |
| 1773 | .dout (int_hole0_stall[2:0]), |
| 1774 | .siclk(siclk), |
| 1775 | .soclk(soclk) |
| 1776 | ); |
| 1777 | |
| 1778 | assign int_hole1_in = (fgu1_d & idest1_d & dec_decode1_d) | idiv_stall_d[1]; |
| 1779 | |
| 1780 | dec_del_ctl_msff_ctl_macro__width_3 inthole1_df ( |
| 1781 | .scan_in(inthole1_df_scanin), |
| 1782 | .scan_out(inthole1_df_scanout), |
| 1783 | .l1clk(l1clk), |
| 1784 | .din ({int_hole1_in,int_hole1_stall[2:1]}), |
| 1785 | .dout (int_hole1_stall[2:0]), |
| 1786 | .siclk(siclk), |
| 1787 | .soclk(soclk) |
| 1788 | ); |
| 1789 | |
| 1790 | dec_del_ctl_msff_ctl_macro__width_3 divstall_df ( |
| 1791 | .scan_in(divstall_df_scanin), |
| 1792 | .scan_out(divstall_df_scanout), |
| 1793 | .l1clk(l1clk), |
| 1794 | .din ({fgu_idiv_stall[1:0],fgu_fdiv_stall}), |
| 1795 | .dout ({idiv_stall_d[1:0],fdiv_stall_d}), |
| 1796 | .siclk(siclk), |
| 1797 | .soclk(soclk) |
| 1798 | ); |
| 1799 | |
| 1800 | assign window_stall_in[1:0] = { exu1_window_block | tlu_window_block[1], |
| 1801 | exu0_window_block | tlu_window_block[0] }; |
| 1802 | dec_del_ctl_msff_ctl_macro__width_2 windowstall_df ( |
| 1803 | .scan_in(windowstall_df_scanin), |
| 1804 | .scan_out(windowstall_df_scanout), |
| 1805 | .l1clk(l1clk), |
| 1806 | .din (window_stall_in[1:0]), |
| 1807 | .dout (window_stall_d[1:0]), |
| 1808 | .siclk(siclk), |
| 1809 | .soclk(soclk) |
| 1810 | ); |
| 1811 | |
| 1812 | // clken signals for the exu |
| 1813 | // not sure about window_stall; leave it out for now |
| 1814 | |
| 1815 | assign exu_clken_in[1:0] = { valid1_d_in | test_stall1_in | twocycle1_d_in | ~lsu_exu_pmen, |
| 1816 | valid0_d_in | test_stall0_in | twocycle0_d_in | ~lsu_exu_pmen}; |
| 1817 | |
| 1818 | dec_del_ctl_msff_ctl_macro__width_2 exu_clkenf ( |
| 1819 | .scan_in(exu_clkenf_scanin), |
| 1820 | .scan_out(exu_clkenf_scanout), |
| 1821 | .l1clk(l1clk), |
| 1822 | .din (exu_clken_in[1:0]), |
| 1823 | .dout (dec_exu_clken[1:0]), |
| 1824 | .siclk(siclk), |
| 1825 | .soclk(soclk) |
| 1826 | ); |
| 1827 | |
| 1828 | |
| 1829 | // |
| 1830 | // for legal insts, this can only happen for stores |
| 1831 | // |
| 1832 | assign lsu_float_case = fgu0_d & lsu0_d & fgu1_d & lsu1_d; |
| 1833 | |
| 1834 | // pdist bug |
| 1835 | // second beat of a pdist can cause an ECC exception; can't let any other op for that TG down the pipe; |
| 1836 | // use pdistblock[] to make this happen |
| 1837 | // for second beat of a pdist, no fgu op can go from either TG; use pdistblock_d to make this happen |
| 1838 | |
| 1839 | |
| 1840 | // two STDs can come the same cycle but never do we have twocycle0_stall and twocycle1_stall at the same time |
| 1841 | // better block0 would be twocycle0_stall | (twocycle1_stall & twocycle0_d) |
| 1842 | |
| 1843 | // only a block if the other one is valid |
| 1844 | assign block0 = (dec_valid1_d & lsu0_d & lsu1_d & lfavor & ~lsu_float_case) | |
| 1845 | (dec_valid1_d & fgu0_d & fgu1_d & ffavor & ~lsu_float_case) | |
| 1846 | (dec_valid1_d & lsu_float_case & sffavor) | |
| 1847 | (fgu0_d & (pdistblock_d | (cmfavor & mult_request) | fecc_stall)) | |
| 1848 | (lsu0_d & (cpq_stall | dtlb_reload_stall)) | |
| 1849 | (block_store_stall0 | (block_store_stall1 & (lsu0_d | fgu0_d))) | |
| 1850 | (twocycle0_stall | (twocycle1_stall & lsu0_d)) | // twocycles can appear at decode0,1 at the same time |
| 1851 | pdistblock[0] | |
| 1852 | ((|idiv_stall_d[1:0]) & fgu0_d & idest0_d) | // hole for common fgu result bus |
| 1853 | int_hole0_stall[0] | // hole for int ops executed by fgu (irf write port) |
| 1854 | (fdiv_stall_d & lsu0_d & fdest0_d) | // hole for frf write port (no load-float) |
| 1855 | window_stall_d[0] | |
| 1856 | power_stall[0] | |
| 1857 | test_stall0; |
| 1858 | |
| 1859 | |
| 1860 | assign dec_decode0_d = dec_valid0_d & ~block0; |
| 1861 | |
| 1862 | assign del_noshift0_d = dec_valid0_d & ~dec_decode0_d; |
| 1863 | |
| 1864 | assign block1 = (dec_valid0_d & lsu0_d & lsu1_d & ~lfavor & ~lsu_float_case) | |
| 1865 | (dec_valid0_d & fgu0_d & fgu1_d & ~ffavor & ~lsu_float_case) | |
| 1866 | (dec_valid0_d & lsu_float_case & ~sffavor) | |
| 1867 | (fgu1_d & (pdistblock_d | (cmfavor & mult_request) | fecc_stall)) | |
| 1868 | (lsu1_d & (cpq_stall | dtlb_reload_stall)) | |
| 1869 | (block_store_stall1 | (block_store_stall0 & (lsu1_d | fgu1_d))) | |
| 1870 | (twocycle1_stall | (twocycle0_stall & lsu1_d)) | |
| 1871 | pdistblock[1] | |
| 1872 | ((|idiv_stall_d[1:0]) & fgu1_d & idest1_d) | // hole for common fgu result bus |
| 1873 | int_hole1_stall[0] | // hole for int ops executed by fgu (irf write port) |
| 1874 | (fdiv_stall_d & lsu1_d & fdest1_d) | // hole for frf write port (no load-float) |
| 1875 | window_stall_d[1] | |
| 1876 | power_stall[0] | |
| 1877 | test_stall1; |
| 1878 | |
| 1879 | |
| 1880 | assign dec_decode1_d = dec_valid1_d & ~block1; |
| 1881 | |
| 1882 | assign del_noshift1_d = dec_valid1_d & ~dec_decode1_d; |
| 1883 | |
| 1884 | dec_del_ctl_msff_ctl_macro__width_2 legal_f ( |
| 1885 | .scan_in(legal_f_scanin), |
| 1886 | .scan_out(legal_f_scanout), |
| 1887 | .l1clk(l1clk), |
| 1888 | .din (ded_legal_p[1:0]), |
| 1889 | .dout (legal_d[1:0]), |
| 1890 | .siclk(siclk), |
| 1891 | .soclk(soclk) |
| 1892 | ); |
| 1893 | |
| 1894 | |
| 1895 | // 0in assert -var (~(idest0_d & fdest0_d & dec_valid0_d & dec_decode0_d)) -message "idest0_d and fdest0_d should be mutually exclusive" |
| 1896 | // 0in assert -var (~(idest1_d & fdest1_d & dec_valid1_d & dec_decode1_d)) -message "idest1_d and fdest1_d should be mutually exclusive" |
| 1897 | |
| 1898 | |
| 1899 | assign illegal0_d = (~legal_d[0] | (dcd_wrtick_d[0] & ~hpriv_d[0])) & ~ifetch_err_d[0]; |
| 1900 | assign illegal1_d = (~legal_d[1] | (dcd_wrtick_d[1] & ~hpriv_d[1])) & ~ifetch_err_d[1]; |
| 1901 | |
| 1902 | |
| 1903 | assign dec_ierr_d[1:0] = { ~legal_d[1] | perr_d[1] | ifetch_err_d[1], |
| 1904 | ~legal_d[0] | perr_d[0] | ifetch_err_d[0] }; |
| 1905 | |
| 1906 | |
| 1907 | // write tick in priv mode then it is illegal_instruction trap |
| 1908 | assign illegal_d[1:0] = {dec_decode1_d & illegal1_d, |
| 1909 | dec_decode0_d & illegal0_d}; |
| 1910 | |
| 1911 | dec_del_ctl_msff_ctl_macro__width_2 illegal_f ( |
| 1912 | .scan_in(illegal_f_scanin), |
| 1913 | .scan_out(illegal_f_scanout), |
| 1914 | .l1clk(l1clk), |
| 1915 | .din (illegal_d[1:0]), |
| 1916 | .dout (illegal_e[1:0]), |
| 1917 | .siclk(siclk), |
| 1918 | .soclk(soclk) |
| 1919 | ); |
| 1920 | |
| 1921 | assign fpdisable_exc_d[1:0] = {dec_decode1_d & ~ifetch_err_d[1] & dcd_fpdisable_d[1] & fpdis_d[1], |
| 1922 | dec_decode0_d & ~ifetch_err_d[0] & dcd_fpdisable_d[0] & fpdis_d[0]}; |
| 1923 | |
| 1924 | dec_del_ctl_msff_ctl_macro__width_2 fpdisable_exc_f ( |
| 1925 | .scan_in(fpdisable_exc_f_scanin), |
| 1926 | .scan_out(fpdisable_exc_f_scanout), |
| 1927 | .l1clk(l1clk), |
| 1928 | .din (fpdisable_exc_d[1:0]), |
| 1929 | .dout (fpdisable_exc_e[1:0]), |
| 1930 | .siclk(siclk), |
| 1931 | .soclk(soclk) |
| 1932 | ); |
| 1933 | |
| 1934 | // only a priv exception if not hypervisor |
| 1935 | // 00 user |
| 1936 | // 01 priv |
| 1937 | // 1- hyper |
| 1938 | |
| 1939 | // write tick in user mode then its a privileged_opcode trap |
| 1940 | // there was a bug in dcd_wrtick_d in the presence of an illegal - can it happen now? |
| 1941 | assign priv_exc_d[1:0] = {dec_decode1_d & ~ifetch_err_d[1] & ((dcd_priv_d[1] & ~priv_d[1] & ~hpriv_d[1]) | (dcd_wrtick_d[1] & ~priv_d[1] & ~hpriv_d[1])), |
| 1942 | dec_decode0_d & ~ifetch_err_d[0] & ((dcd_priv_d[0] & ~priv_d[0] & ~hpriv_d[0]) | (dcd_wrtick_d[0] & ~priv_d[0] & ~hpriv_d[0]))}; |
| 1943 | |
| 1944 | assign hpriv_exc_d[1:0] = {dec_decode1_d & ~ifetch_err_d[1] & dcd_hpr_d[1] & ~hpriv_d[1], |
| 1945 | dec_decode0_d & ~ifetch_err_d[0] & dcd_hpr_d[0] & ~hpriv_d[0]}; |
| 1946 | |
| 1947 | |
| 1948 | |
| 1949 | dec_del_ctl_msff_ctl_macro__width_2 parity_err_f ( |
| 1950 | .scan_in(parity_err_f_scanin), |
| 1951 | .scan_out(parity_err_f_scanout), |
| 1952 | .l1clk(l1clk), |
| 1953 | .din (ded_perr_p[1:0]), |
| 1954 | .dout (perr_d[1:0]), |
| 1955 | .siclk(siclk), |
| 1956 | .soclk(soclk) |
| 1957 | ); |
| 1958 | |
| 1959 | assign icdp_perr_d[1:0] = {dec_decode1_d & perr_d[1], |
| 1960 | dec_decode0_d & perr_d[0] }; |
| 1961 | |
| 1962 | dec_del_ctl_msff_ctl_macro__width_6 exc_f ( |
| 1963 | .scan_in(exc_f_scanin), |
| 1964 | .scan_out(exc_f_scanout), |
| 1965 | .l1clk(l1clk), |
| 1966 | .din ({priv_exc_d[1:0],hpriv_exc_d[1:0],icdp_perr_d[1:0]}), |
| 1967 | .dout ({priv_exc_e[1:0],hpriv_exc_e[1:0],icdp_perr_e[1:0]}), |
| 1968 | .siclk(siclk), |
| 1969 | .soclk(soclk) |
| 1970 | ); |
| 1971 | |
| 1972 | |
| 1973 | assign ffavor_real = (~lsu_float_case & ffavor) | (lsu_float_case & sffavor); |
| 1974 | assign lfavor_real = (~lsu_float_case & lfavor) | (lsu_float_case & sffavor); |
| 1975 | |
| 1976 | assign fgusel0_d = ~ffavor_real & fgu0_d & dec_valid0_d | (ffavor_real & ~(fgu1_d & dec_valid1_d)); |
| 1977 | |
| 1978 | assign fguselect_d[0] = fgusel0_d & dec_fgu_decode_d; |
| 1979 | assign fguselect_d[1] = ~fgusel0_d & dec_fgu_decode_d; |
| 1980 | |
| 1981 | // force this select to the right value for each STD in TG0 or 1 |
| 1982 | assign lsusel0_d = ((~lfavor_real & lsu0_d & dec_valid0_d | (lfavor_real & ~(lsu1_d & dec_valid1_d))) & ~twocycle1_stall) | twocycle0_stall; |
| 1983 | |
| 1984 | // to the pmu to decide which tid to use for lsu at d stage |
| 1985 | assign dec_lsu_sel0_d = lsusel0_d; |
| 1986 | |
| 1987 | dec_del_ctl_msff_ctl_macro__width_4 tgsel_f ( |
| 1988 | .scan_in(tgsel_f_scanin), |
| 1989 | .scan_out(tgsel_f_scanout), |
| 1990 | .l1clk(l1clk), |
| 1991 | .din ({fguselect_d[1:0],twocycle0_stall,twocycle1_stall}), |
| 1992 | .dout ({dec_fgu_sel_e[1:0],twocycle0_stall_e,twocycle1_stall_e}), |
| 1993 | .siclk(siclk), |
| 1994 | .soclk(soclk) |
| 1995 | ); |
| 1996 | |
| 1997 | |
| 1998 | // 0in value -var {dec_lsu_sel0_e,dec_lsu_sel1_e} -val 0 1 2 -message "{dec_lsu_sel0_e,dec_lsu_sel1_e} are mutually exclusive" |
| 1999 | |
| 2000 | // can be off a flop if needed for timing |
| 2001 | assign dec_lsu_sel0_e = decode_lsu0_e | twocycle0_stall_e; |
| 2002 | assign dec_lsu_sel1_e = decode_lsu1_e | twocycle1_stall_e; |
| 2003 | |
| 2004 | // put a little logic on the pstate_am signals (more flops if it doesn't make timing) |
| 2005 | assign pstate_am_in[1:0] = { |(tlu_pstate_am[7:4] & pick1_d[3:0]), |(tlu_pstate_am[3:0] & pick0_d[3:0]) }; |
| 2006 | |
| 2007 | |
| 2008 | assign rs1_addr0_d = decode_lsu0_d & casa_or_pst_d; |
| 2009 | assign rs1_addr1_d = decode_lsu1_d & casa_or_pst_d; |
| 2010 | |
| 2011 | assign lsu_sel0_lower_d = decode_lsu0_d & ~casa_or_pst_d; |
| 2012 | assign lsu_sel1_lower_d = decode_lsu1_d & ~casa_or_pst_d; |
| 2013 | |
| 2014 | |
| 2015 | // quiet down these selects by using decode_lsu |
| 2016 | |
| 2017 | assign lsu_sel0_upper_d = decode_lsu0_d & ~casa_or_pst_d & ~pstate_am_in[0]; |
| 2018 | assign lsu_sel1_upper_d = decode_lsu1_d & ~casa_or_pst_d & ~pstate_am_in[1]; |
| 2019 | |
| 2020 | assign rs1_addr0_upper_d = decode_lsu0_d & casa_or_pst_d & ~pstate_am_in[0]; |
| 2021 | assign rs1_addr1_upper_d = decode_lsu1_d & casa_or_pst_d & ~pstate_am_in[1]; |
| 2022 | |
| 2023 | |
| 2024 | // flop the selects to the exu for timing |
| 2025 | |
| 2026 | dec_del_ctl_msff_ctl_macro__width_8 exuself ( |
| 2027 | .scan_in(exuself_scanin), |
| 2028 | .scan_out(exuself_scanout), |
| 2029 | .l1clk(l1clk), |
| 2030 | .din ({ rs1_addr0_d, rs1_addr1_d, lsu_sel0_lower_d, lsu_sel1_lower_d, |
| 2031 | lsu_sel0_upper_d, lsu_sel1_upper_d, rs1_addr0_upper_d, rs1_addr1_upper_d}), |
| 2032 | |
| 2033 | .dout ({ dec_rs1_addr0_e, dec_rs1_addr1_e, dec_lsu_sel0_lower_e, dec_lsu_sel1_lower_e, |
| 2034 | dec_lsu_sel0_upper_e, dec_lsu_sel1_upper_e, dec_rs1_addr0_upper_e, dec_rs1_addr1_upper_e}), |
| 2035 | .siclk(siclk), |
| 2036 | .soclk(soclk) |
| 2037 | ); |
| 2038 | |
| 2039 | |
| 2040 | // next 4 must be mutually exclusive (but not 1-hot) |
| 2041 | |
| 2042 | // 0in value -var {dec_rs1_addr0_e,dec_rs1_addr1_e,dec_lsu_sel0_lower_e,dec_lsu_sel1_lower_e} -val 0 1 2 4 8 -message "{dec_rs1_addr0_e,dec_rs1_addr1_e,dec_lsu_sel0_lower_e,dec_lsu_sel1_lower_e} are mutually exclusive" |
| 2043 | |
| 2044 | // next 4 are mutually exclusive (but not 1-hot) |
| 2045 | |
| 2046 | // 0in value -var {dec_lsu_sel0_upper_e,dec_lsu_sel1_upper_e,dec_rs1_addr0_upper_e,dec_rs1_addr1_upper_e} -val 0 1 2 4 8 -message "{dec_lsu_sel0_upper_e,dec_lsu_sel1_upper_e,dec_rs1_addr0_upper_e,dec_rs1_addr1_upper_e} are mutually exclusive" |
| 2047 | |
| 2048 | |
| 2049 | |
| 2050 | dec_del_ctl_msff_ctl_macro__width_2 tgselm_f ( |
| 2051 | .scan_in(tgselm_f_scanin), |
| 2052 | .scan_out(tgselm_f_scanout), |
| 2053 | .l1clk(l1clk), |
| 2054 | .din (dec_fgu_sel_e[1:0]), |
| 2055 | .dout (dec_fgu_sel_m[1:0]), |
| 2056 | .siclk(siclk), |
| 2057 | .soclk(soclk) |
| 2058 | ); |
| 2059 | |
| 2060 | // generate interface needed by the fgu |
| 2061 | |
| 2062 | assign store_float[0] = fsrc0_rd_d & fgu0_d; |
| 2063 | assign store_float[1] = fsrc1_rd_d & fgu1_d; |
| 2064 | |
| 2065 | // remap the integer destinations |
| 2066 | |
| 2067 | assign i0_rd[4:0] = dec_inst0_raw_rd_d[4:0]; |
| 2068 | assign i1_rd[4:0] = dec_inst1_raw_rd_d[4:0]; |
| 2069 | |
| 2070 | assign i0_rd_remap_d[4:0] = ({5{idest0_d}} & {i0_rd[4] ^ (i0_rd[3] & (ded_oddwin0_d ^ dcd_save_restore_d[0])), i0_rd[3:0]}) | |
| 2071 | ({5{~idest0_d}} & i0_rd[4:0]); |
| 2072 | |
| 2073 | assign i1_rd_remap_d[4:0] = ({5{idest1_d}} & {i1_rd[4] ^ (i1_rd[3] & (ded_oddwin1_d ^ dcd_save_restore_d[1])), i1_rd[3:0]}) | |
| 2074 | ({5{~idest1_d}} & i1_rd[4:0]); |
| 2075 | |
| 2076 | assign dec_irf_w_addr_d[4:0] = ({5{fgusel0_d}} & i0_rd_remap_d[4:0]) | |
| 2077 | ({5{~fgusel0_d}} & i1_rd_remap_d[4:0]); |
| 2078 | |
| 2079 | // munge the address to always be double precision for fgu sources, dest |
| 2080 | assign f0_rs1[4:0] = ({5{dcd_fp_rs1_single_d[0]}} & {1'b0,dec_inst0_rs1_d[4:1]}) | |
| 2081 | ({5{~dcd_fp_rs1_single_d[0]}} & {dec_inst0_rs1_d[0],dec_inst0_rs1_d[4:1]}); |
| 2082 | |
| 2083 | assign f0_rs2[4:0] = ({5{dcd_fp_rs2_single_d[0]}} & {1'b0,dec_inst0_rs2_d[4:1]}) | |
| 2084 | ({5{~dcd_fp_rs2_single_d[0]}} & {dec_inst0_rs2_d[0],dec_inst0_rs2_d[4:1]}); |
| 2085 | |
| 2086 | assign f0_rd[4:0] = ({5{dcd_fpdest_single_d[0]}} & {1'b0,dec_inst0_raw_rd_d[4:1]}) | |
| 2087 | ({5{~dcd_fpdest_single_d[0]}} & {dec_inst0_raw_rd_d[0],dec_inst0_raw_rd_d[4:1]}); |
| 2088 | |
| 2089 | assign f1_rs1[4:0] = ({5{dcd_fp_rs1_single_d[1]}} & {1'b0,dec_inst1_rs1_d[4:1]}) | |
| 2090 | ({5{~dcd_fp_rs1_single_d[1]}} & {dec_inst1_rs1_d[0],dec_inst1_rs1_d[4:1]}); |
| 2091 | |
| 2092 | assign f1_rs2[4:0] = ({5{dcd_fp_rs2_single_d[1]}} & {1'b0,dec_inst1_rs2_d[4:1]}) | |
| 2093 | ({5{~dcd_fp_rs2_single_d[1]}} & {dec_inst1_rs2_d[0],dec_inst1_rs2_d[4:1]}); |
| 2094 | |
| 2095 | assign f1_rd[4:0] = ({5{dcd_fpdest_single_d[1]}} & {1'b0,dec_inst1_raw_rd_d[4:1]}) | |
| 2096 | ({5{~dcd_fpdest_single_d[1]}} & {dec_inst1_raw_rd_d[0],dec_inst1_raw_rd_d[4:1]}); |
| 2097 | |
| 2098 | |
| 2099 | |
| 2100 | assign dec_frf_r1_addr_d[4:0] = ({5{fgusel0_d}} & f0_rs1[4:0]) | |
| 2101 | ({5{~fgusel0_d}} & f1_rs1[4:0]); |
| 2102 | |
| 2103 | assign inst0_rs2[4:0] = ({5{store_float[0]}} & f0_rd[4:0]) | |
| 2104 | ({5{~store_float[0]}} & f0_rs2[4:0]); |
| 2105 | |
| 2106 | assign inst1_rs2[4:0] = ({5{store_float[1]}} & f1_rd[4:0]) | |
| 2107 | ({5{~store_float[1]}} & f1_rs2[4:0]); |
| 2108 | |
| 2109 | assign dec_frf_r2_addr_d[4:0] = ({5{block_store_stall}} & block_store_rd[4:0]) | |
| 2110 | ({5{~block_store_stall & pdistblock_d}} & pdist_rd[4:0]) | |
| 2111 | ({5{~block_store_stall & fgusel0_d & ~pdistblock_d}} & inst0_rs2[4:0]) | |
| 2112 | ({5{~block_store_stall & ~fgusel0_d & ~pdistblock_d}} & inst1_rs2[4:0]); |
| 2113 | |
| 2114 | // Flop for LSU |
| 2115 | dec_del_ctl_msff_ctl_macro__width_2 frf_r2addre_f ( |
| 2116 | .scan_in(frf_r2addre_f_scanin), |
| 2117 | .scan_out(frf_r2addre_f_scanout), |
| 2118 | .l1clk(l1clk), |
| 2119 | .din (dec_frf_r2_addr_d[4:3]), |
| 2120 | .dout (dec_frf_r2_addr_e[4:3]), |
| 2121 | .siclk(siclk), |
| 2122 | .soclk(soclk) |
| 2123 | ); |
| 2124 | |
| 2125 | assign dec_frf_w_addr_d[4:0] = ({5{ fgusel0_d}} & f0_rd[4:0]) | |
| 2126 | ({5{~fgusel0_d}} & f1_rd[4:0]); |
| 2127 | |
| 2128 | assign dec_frf_r1_vld_d = ((fgu0_d & dec_decode0_d & fgusel0_d & dcd_fsrc_rs1_d[0]) | |
| 2129 | (fgu1_d & dec_decode1_d & ~fgusel0_d & dcd_fsrc_rs1_d[1])) & ~pdistblock_d & ~block_store_stall; |
| 2130 | |
| 2131 | assign dec_frf_r2_vld_d = (fgu0_d & dec_decode0_d & fgusel0_d & (dcd_fsrc_rs2_d[0] | store_float[0])) | |
| 2132 | (fgu1_d & dec_decode1_d & ~fgusel0_d & (dcd_fsrc_rs2_d[1] | store_float[1])) | |
| 2133 | pdistblock_d | block_store_stall; |
| 2134 | |
| 2135 | assign dec_frf_w_vld_d = ( fgusel0_d & (fdest0_d & ~pdistblock_d)) | |
| 2136 | (~fgusel0_d & (fdest1_d & ~pdistblock_d)); |
| 2137 | |
| 2138 | assign dec_frf_r1_32b_d = ( fgusel0_d & dcd_fp_rs1_single_d[0]) | |
| 2139 | (~fgusel0_d & dcd_fp_rs1_single_d[1]); |
| 2140 | |
| 2141 | assign dec_frf_r2_32b_d = ( fgusel0_d & dcd_fp_rs2_single_d[0] & ~pdistblock_d & ~block_store_stall) | |
| 2142 | (~fgusel0_d & dcd_fp_rs2_single_d[1] & ~pdistblock_d & ~block_store_stall); |
| 2143 | |
| 2144 | assign dec_frf_r1_odd32b_d = ( fgusel0_d & dcd_fp_rs1_single_d[0] & dec_inst0_rs1_d[0]) | |
| 2145 | (~fgusel0_d & dcd_fp_rs1_single_d[1] & dec_inst1_rs1_d[0]); |
| 2146 | |
| 2147 | // before the munge |
| 2148 | assign inst0_rs2_raw_bit0 = (store_float[0] & dec_inst0_raw_rd_d[0]) | |
| 2149 | (~store_float[0] & dec_inst0_rs2_d[0]); |
| 2150 | |
| 2151 | assign inst1_rs2_raw_bit0 = (store_float[1] & dec_inst1_raw_rd_d[0]) | |
| 2152 | (~store_float[1] & dec_inst1_rs2_d[0]); |
| 2153 | |
| 2154 | assign dec_frf_r2_odd32b_d = (fgusel0_d & dcd_fp_rs2_single_d[0] & inst0_rs2_raw_bit0 & ~pdistblock_d & ~block_store_stall) | |
| 2155 | (~fgusel0_d & dcd_fp_rs2_single_d[1] & inst1_rs2_raw_bit0 & ~pdistblock_d & ~block_store_stall); |
| 2156 | |
| 2157 | assign dec_frf_w_32b_d = (fgusel0_d & dcd_fpdest_single_d[0]) | |
| 2158 | (~fgusel0_d & dcd_fpdest_single_d[1]); |
| 2159 | |
| 2160 | assign dec_frf_w_odd32b_d = (fgusel0_d & dcd_fpdest_single_d[0] & dec_inst0_raw_rd_d[0]) | |
| 2161 | (~fgusel0_d & dcd_fpdest_single_d[1] & dec_inst1_raw_rd_d[0]); |
| 2162 | |
| 2163 | assign dec_exu_src_vld_d = (fgusel0_d & dcd_exu_src_d[0] & ~pdistblock_d & ~block_store_stall) | |
| 2164 | (~fgusel0_d & dcd_exu_src_d[1] & ~pdistblock_d & ~block_store_stall); |
| 2165 | |
| 2166 | assign dec_frf_store_d = (fgusel0_d & store_float[0] & ~pdistblock_d) | |
| 2167 | (~fgusel0_d & store_float[1] & ~pdistblock_d) | |
| 2168 | block_store_stall; |
| 2169 | |
| 2170 | assign fsr_store0 = dcd_store_d[0] & dcd_fsrsync_d[0]; |
| 2171 | assign fsr_store1 = dcd_store_d[1] & dcd_fsrsync_d[1]; |
| 2172 | |
| 2173 | assign dec_fsr_store_d = (fgusel0_d & fsr_store0 & ~pdistblock_d & ~block_store_stall) | |
| 2174 | (~fgusel0_d & fsr_store1 & ~pdistblock_d & ~block_store_stall); |
| 2175 | |
| 2176 | |
| 2177 | assign dec_fgu_op3_d[5:0] = ({6{fgusel0_d}} & dec_inst0_op3_d[5:0]) | |
| 2178 | ({6{~fgusel0_d}} & dec_inst1_op3_d[5:0]); |
| 2179 | |
| 2180 | assign dec_fgu_opf_d[7:0] = ({8{fgusel0_d}} & dec_inst0_opf_d[7:0]) | |
| 2181 | ({8{~fgusel0_d}} & dec_inst1_opf_d[7:0]); |
| 2182 | |
| 2183 | |
| 2184 | // dont fire if a lsu op unless it is a store-float (including stfsr) |
| 2185 | // harden for illegals |
| 2186 | assign dec_fgu_decode_d = (dec_decode0_d & fgusel0_d & fgu0_d & ~(lsu0_d & ~fgu0_d)) | |
| 2187 | (dec_decode1_d & ~fgusel0_d & fgu1_d & ~(lsu1_d & ~fgu1_d)) | |
| 2188 | block_store_stall; |
| 2189 | // .i 4 |
| 2190 | // .o 2 |
| 2191 | // .ilb p[3] p[2] p[1] p[0] |
| 2192 | // .ob tid[1] tid[0] |
| 2193 | // .type fr |
| 2194 | // 0001 00 |
| 2195 | // 0010 01 |
| 2196 | // 0100 10 |
| 2197 | // 1000 11 |
| 2198 | |
| 2199 | assign tid0_d[1] = ~pick0_d[1] & ~pick0_d[0]; |
| 2200 | assign tid0_d[0] = ~pick0_d[2] & ~pick0_d[0]; |
| 2201 | |
| 2202 | assign tid1_d[1] = ~pick1_d[1] & ~pick1_d[0]; |
| 2203 | assign tid1_d[0] = ~pick1_d[2] & ~pick1_d[0]; |
| 2204 | |
| 2205 | assign dec_tid0_d[1:0] = tid0_d[1:0]; |
| 2206 | assign dec_tid1_d[1:0] = tid1_d[1:0]; |
| 2207 | |
| 2208 | assign dec_fgu_tid_d[2:0] = ({3{block_store_stall}} & block_store_tid[2:0]) | |
| 2209 | ({3{~block_store_stall & pdistblock_d}} & pdist_tid[2:0]) | |
| 2210 | ({3{~block_store_stall & fgusel0_d & ~pdistblock_d}} & {1'b0,tid0_d[1:0]}) | |
| 2211 | ({3{~block_store_stall & ~fgusel0_d & ~pdistblock_d}} & {1'b1,tid1_d[1:0]}); |
| 2212 | |
| 2213 | // 0in value -var pku_flush_f1[7:0] -val 0 1 2 4 8 16 32 64 128 |
| 2214 | // 0in value -var pku_flush_f2[7:0] -val 0 1 2 4 8 16 32 64 128 |
| 2215 | // 0in value -var pku_flush_lm[7:0] -val 0 1 2 4 8 16 32 64 128 |
| 2216 | // 0in value -var pku_flush_lb[7:0] -val 0 1 2 4 8 16 32 64 128 |
| 2217 | |
| 2218 | assign dec_flush_f1 = |pku_flush_f1[7:0]; |
| 2219 | assign dec_flush_f2 = |pku_flush_f2[7:0]; |
| 2220 | |
| 2221 | // Must flush lsu instructions which cause fp_disabled or priv or hpriv exc |
| 2222 | assign dec_flush_lm = (|pku_flush_lm[7:0]) | flush_lexc_m; |
| 2223 | assign dec_flush_lb = |pku_flush_lb[7:0]; |
| 2224 | |
| 2225 | // 0in value -var pku_flush_m[7:4] -val 0 1 2 4 8 |
| 2226 | // 0in value -var pku_flush_m[3:0] -val 0 1 2 4 8 |
| 2227 | |
| 2228 | assign dec_flush_m[1] = |pku_flush_m[7:4]; |
| 2229 | assign dec_flush_m[0] = |pku_flush_m[3:0]; |
| 2230 | |
| 2231 | // 0in value -var pku_flush_b[7:4] -val 0 1 2 4 8 |
| 2232 | // 0in value -var pku_flush_b[3:0] -val 0 1 2 4 8 |
| 2233 | |
| 2234 | assign dec_flush_b[1] = |pku_flush_b[7:4]; |
| 2235 | assign dec_flush_b[0] = |pku_flush_b[3:0]; |
| 2236 | |
| 2237 | |
| 2238 | dec_del_ctl_msff_ctl_macro__width_2 ifetch_err_f ( |
| 2239 | .scan_in(ifetch_err_f_scanin), |
| 2240 | .scan_out(ifetch_err_f_scanout), |
| 2241 | .l1clk(l1clk), |
| 2242 | .din (ded_ferr_p[1:0]), |
| 2243 | .dout (ifetch_err_d[1:0]), |
| 2244 | .siclk(siclk), |
| 2245 | .soclk(soclk) |
| 2246 | ); |
| 2247 | |
| 2248 | dec_del_ctl_msff_ctl_macro__width_2 ifetcherr_f ( |
| 2249 | .scan_in(ifetcherr_f_scanin), |
| 2250 | .scan_out(ifetcherr_f_scanout), |
| 2251 | .l1clk(l1clk), |
| 2252 | .din (ifetch_err_d[1:0]), |
| 2253 | .dout (ifetch_err_e[1:0]), |
| 2254 | .siclk(siclk), |
| 2255 | .soclk(soclk) |
| 2256 | ); |
| 2257 | |
| 2258 | |
| 2259 | assign true_valid_d[0] = ~illegal_d[0] & ~priv_exc_d[0] & ~hpriv_exc_d[0] & ~fpdisable_exc_d[0] & ~icdp_perr_d[0] & ~ifetch_err_d[0]; |
| 2260 | assign true_valid_d[1] = ~illegal_d[1] & ~priv_exc_d[1] & ~hpriv_exc_d[1] & ~fpdisable_exc_d[1] & ~icdp_perr_d[1] & ~ifetch_err_d[1]; |
| 2261 | |
| 2262 | // don't let exceptions into the machine |
| 2263 | dec_del_ctl_msff_ctl_macro__width_2 truevalid_f ( |
| 2264 | .scan_in(truevalid_f_scanin), |
| 2265 | .scan_out(truevalid_f_scanout), |
| 2266 | .l1clk(l1clk), |
| 2267 | .din (true_valid_d[1:0]), |
| 2268 | .dout (dec_true_valid_e[1:0]), |
| 2269 | .siclk(siclk), |
| 2270 | .soclk(soclk) |
| 2271 | ); |
| 2272 | |
| 2273 | // pmu eco; dont qualify valids with ifetch_err[1:0] so itlb misses will be counted |
| 2274 | assign illegal0_pmu_d = (~legal_d[0] | (dcd_wrtick_d[0] & ~hpriv_d[0])) & ~ifetch_err_d[0]; // add this to gates, missing |
| 2275 | assign illegal1_pmu_d = (~legal_d[1] | (dcd_wrtick_d[1] & ~hpriv_d[1])) & ~ifetch_err_d[1]; |
| 2276 | |
| 2277 | |
| 2278 | // write tick in priv mode then it is illegal_instruction trap |
| 2279 | assign illegal_pmu_d[1:0] = {dec_decode1_d & illegal1_pmu_d, |
| 2280 | dec_decode0_d & illegal0_pmu_d}; |
| 2281 | |
| 2282 | assign priv_exc_pmu_d[1:0] = {dec_decode1_d & ~ifetch_err_d[1] & ((dcd_priv_d[1] & ~priv_d[1] & ~hpriv_d[1]) | (dcd_wrtick_d[1] & ~priv_d[1] & ~hpriv_d[1])), |
| 2283 | dec_decode0_d & ~ifetch_err_d[0] & ((dcd_priv_d[0] & ~priv_d[0] & ~hpriv_d[0]) | (dcd_wrtick_d[0] & ~priv_d[0] & ~hpriv_d[0]))}; |
| 2284 | |
| 2285 | assign hpriv_exc_pmu_d[1:0] = {dec_decode1_d & dcd_hpr_d[1] & ~hpriv_d[1], |
| 2286 | dec_decode0_d & dcd_hpr_d[0] & ~hpriv_d[0]}; |
| 2287 | |
| 2288 | |
| 2289 | assign fpdisable_exc_pmu_d[1:0] = {dec_decode1_d & dcd_fpdisable_d[1] & fpdis_d[1], |
| 2290 | dec_decode0_d & dcd_fpdisable_d[0] & fpdis_d[0]}; |
| 2291 | |
| 2292 | assign pmu_valid_d[0] = ~illegal_pmu_d[0] & ~priv_exc_pmu_d[0] & ~hpriv_exc_pmu_d[0] & ~fpdisable_exc_pmu_d[0] & ~icdp_perr_d[0]; |
| 2293 | |
| 2294 | assign pmu_valid_d[1] = ~illegal_pmu_d[1] & ~priv_exc_pmu_d[1] & ~hpriv_exc_pmu_d[1] & ~fpdisable_exc_pmu_d[1] & ~icdp_perr_d[1]; |
| 2295 | |
| 2296 | // use spare flops (see above) |
| 2297 | |
| 2298 | assign dec_pmu_valid_e[0] = valid_e[0] & pmu_valid_e[0]; |
| 2299 | assign dec_pmu_valid_e[1] = valid_e[1] & pmu_valid_e[1]; |
| 2300 | // end pmu eco |
| 2301 | |
| 2302 | // 0in value -var pku_valid_e[7:4] -val 0 1 2 4 8 |
| 2303 | // 0in value -var pku_valid_e[3:0] -val 0 1 2 4 8 |
| 2304 | |
| 2305 | assign valid_e[0] = |pku_valid_e[3:0]; |
| 2306 | assign valid_e[1] = |pku_valid_e[7:4]; |
| 2307 | |
| 2308 | assign dec_valid_e[0] = valid_e[0] & dec_true_valid_e[0]; |
| 2309 | assign dec_valid_e[1] = valid_e[1] & dec_true_valid_e[1]; |
| 2310 | |
| 2311 | // Must send lsu_valid even when fpdisabled or priv or hpriv excs |
| 2312 | assign ls_valid_e[0] = valid_e[0] & ~illegal_e[0] & ~icdp_perr_e[0] & ~ifetch_err_e[0]; |
| 2313 | assign ls_valid_e[1] = valid_e[1] & ~illegal_e[1] & ~icdp_perr_e[1] & ~ifetch_err_e[1]; |
| 2314 | |
| 2315 | // never fire dec_fgu_valid_e for a lsu operation |
| 2316 | |
| 2317 | // harden for illegals |
| 2318 | assign decode_fgu0_d = dec_decode0_d & fgusel0_d & fgu0_d & ~lsu0_d & ~dcd_killfgu_d[0]; |
| 2319 | assign decode_fgu1_d = dec_decode1_d & ~fgusel0_d & fgu1_d & ~lsu1_d & ~dcd_killfgu_d[1]; |
| 2320 | |
| 2321 | dec_del_ctl_msff_ctl_macro__width_2 fgudec_f ( |
| 2322 | .scan_in(fgudec_f_scanin), |
| 2323 | .scan_out(fgudec_f_scanout), |
| 2324 | .l1clk(l1clk), |
| 2325 | .din ({decode_fgu0_d,decode_fgu1_d}), |
| 2326 | .dout ({decode_fgu0_e,decode_fgu1_e}), |
| 2327 | .siclk(siclk), |
| 2328 | .soclk(soclk) |
| 2329 | ); |
| 2330 | |
| 2331 | // fgu operation at e and it is not a lsu operation |
| 2332 | assign dec_fgu_valid_e = (decode_fgu0_e & dec_valid_e[0]) | |
| 2333 | (decode_fgu1_e & dec_valid_e[1]); |
| 2334 | |
| 2335 | // harden for illegals |
| 2336 | assign decode_lsu0_d = dec_decode0_d & lsusel0_d & lsu0_d; |
| 2337 | assign decode_lsu1_d = dec_decode1_d & ~lsusel0_d & lsu1_d; |
| 2338 | |
| 2339 | dec_del_ctl_msff_ctl_macro__width_2 lsudec_f ( |
| 2340 | .scan_in(lsudec_f_scanin), |
| 2341 | .scan_out(lsudec_f_scanout), |
| 2342 | .l1clk(l1clk), |
| 2343 | .din ({decode_lsu0_d,decode_lsu1_d}), |
| 2344 | .dout ({decode_lsu0_e,decode_lsu1_e}), |
| 2345 | .siclk(siclk), |
| 2346 | .soclk(soclk) |
| 2347 | ); |
| 2348 | |
| 2349 | |
| 2350 | // lsu interface |
| 2351 | |
| 2352 | // this bug is no longer valid since we gate off all decodes for an illegal instruction |
| 2353 | // wrong! if a parity error is present it can appear to be illegal ... harden the logic |
| 2354 | |
| 2355 | // bug fix |
| 2356 | // if illegal is in TG0 and a valid load is in TG1, then ld_inst_d can fire for TG0 and be misinterpreted by TG1 |
| 2357 | // this case is for different threads and both decode same cycle |
| 2358 | // add lsusel0_d to eliminate this case |
| 2359 | |
| 2360 | assign dec_ld_inst_d = (dec_decode0_d & lsusel0_d & dcd_load_d[0]) | |
| 2361 | (dec_decode1_d & ~lsusel0_d & dcd_load_d[1]); |
| 2362 | |
| 2363 | |
| 2364 | assign st_inst_d = (lsusel0_d & dcd_store_d[0]) | |
| 2365 | (~lsusel0_d & dcd_store_d[1]); |
| 2366 | |
| 2367 | assign fsr_ldst_d = (lsusel0_d & dcd_fsrsync_d[0]) | |
| 2368 | (~lsusel0_d & dcd_fsrsync_d[1]); |
| 2369 | |
| 2370 | |
| 2371 | dec_del_ctl_msff_ctl_macro__width_3 ldste_f ( |
| 2372 | .scan_in(ldste_f_scanin), |
| 2373 | .scan_out(ldste_f_scanout), |
| 2374 | .l1clk(l1clk), |
| 2375 | .din ({dec_ld_inst_d,st_inst_d,fsr_ldst_d}), |
| 2376 | .dout ({ld_inst_e,st_inst_e,fsr_ldst_e}), |
| 2377 | .siclk(siclk), |
| 2378 | .soclk(soclk) |
| 2379 | ); |
| 2380 | |
| 2381 | assign dec_ld_inst_e = ld_inst_e & lsu_valid_e; |
| 2382 | assign dec_st_inst_e = st_inst_e & lsu_valid_e; |
| 2383 | assign dec_fsr_ldst_e = fsr_ldst_e; |
| 2384 | |
| 2385 | assign fpldst_d = (lsusel0_d & (load_float0_d | store_float0_d)) | |
| 2386 | (~lsusel0_d & (load_float1_d | store_float1_d)); |
| 2387 | |
| 2388 | assign lsdouble_d = (lsusel0_d & (dcd_load_d[0] | dcd_store_d[0]) & dcd_lsdouble_d[0]) | |
| 2389 | (~lsusel0_d & (dcd_load_d[1] | dcd_store_d[1]) & dcd_lsdouble_d[1]); |
| 2390 | |
| 2391 | assign prefetch_d = (lsusel0_d & dcd_prefetch_d[0]) | |
| 2392 | (~lsusel0_d & dcd_prefetch_d[1]); |
| 2393 | |
| 2394 | assign flush_d = (lsusel0_d & dcd_flush_d[0]) | |
| 2395 | (~lsusel0_d & dcd_flush_d[1]); |
| 2396 | |
| 2397 | assign memstbar_d = (lsusel0_d & dcd_memstbar_d[0]) | |
| 2398 | (~lsusel0_d & dcd_memstbar_d[1]); |
| 2399 | |
| 2400 | assign pr_d = (lsusel0_d & dcd_pr_d[0]) | |
| 2401 | (~lsusel0_d & dcd_pr_d[1]); |
| 2402 | |
| 2403 | assign hpr_d = (lsusel0_d & dcd_hpr_d[0]) | |
| 2404 | (~lsusel0_d & dcd_hpr_d[1]); |
| 2405 | |
| 2406 | assign sr_d = (lsusel0_d & dcd_sr_d[0]) | |
| 2407 | (~lsusel0_d & dcd_sr_d[1]); |
| 2408 | |
| 2409 | // finish the decode of partial store |
| 2410 | assign pst_d = (lsusel0_d & dcd_stdfa_d[0] & (dec_inst0_opf_d[7:4]==4'b1100) & (dec_inst0_opf_d[2:1] != 2'b11)) | |
| 2411 | (~lsusel0_d & dcd_stdfa_d[1] & (dec_inst1_opf_d[7:4]==4'b1100) & (dec_inst1_opf_d[2:1] != 2'b11)); |
| 2412 | |
| 2413 | assign casa_d = (lsusel0_d & dcd_casa_d[0]) | |
| 2414 | (~lsusel0_d & dcd_casa_d[1]); |
| 2415 | |
| 2416 | assign ldstub_d = (lsusel0_d & dcd_ldstub_d[0]) | |
| 2417 | (~lsusel0_d & dcd_ldstub_d[1]); |
| 2418 | |
| 2419 | assign swap_d = (lsusel0_d & dcd_swap_d[0]) | |
| 2420 | (~lsusel0_d & dcd_swap_d[1]); |
| 2421 | |
| 2422 | // how to code 0in to find potential issues with illegals |
| 2423 | |
| 2424 | // 0in assert -var (~(lsusel0_d & ~(dcd_alt_d[0] | dcd_alti_d[0]) & dec_altspace_d)) -message "unexpected dec_altspace_d for TG0" |
| 2425 | |
| 2426 | // 0in assert -var (~(~lsusel0_d & ~(dcd_alt_d[1] | dcd_alti_d[1]) & dec_altspace_d)) -message "unexpected dec_altspace_d for TG1" |
| 2427 | |
| 2428 | // add lsusel0_d for illegal case |
| 2429 | assign dec_altspace_d = (dec_decode0_d & lsusel0_d & (dcd_alt_d[0] | dcd_alti_d[0])) | |
| 2430 | (dec_decode1_d & ~lsusel0_d & (dcd_alt_d[1] | dcd_alti_d[1])); |
| 2431 | |
| 2432 | assign altspacei_d = (lsusel0_d & dcd_alt_d[0]) | |
| 2433 | (~lsusel0_d & dcd_alt_d[1]); |
| 2434 | |
| 2435 | assign sign_ext_d = (lsusel0_d & dcd_lsu_sign_ext_d[0]) | |
| 2436 | (~lsusel0_d & dcd_lsu_sign_ext_d[1]); |
| 2437 | |
| 2438 | assign lsize_d[1:0] = ({2{lsusel0_d}} & dcd_lsize0_d[1:0]) | |
| 2439 | ({2{~lsusel0_d}} & dcd_lsize1_d[1:0]); |
| 2440 | |
| 2441 | |
| 2442 | |
| 2443 | assign dec_imm_asi_vld_d = altspacei_d; |
| 2444 | |
| 2445 | assign casa_or_pst_d = (casa_d | pst_d); |
| 2446 | |
| 2447 | dec_del_ctl_msff_ctl_macro__width_14 ldme_f ( |
| 2448 | .scan_in(ldme_f_scanin), |
| 2449 | .scan_out(ldme_f_scanout), |
| 2450 | .l1clk(l1clk), |
| 2451 | .din ({ fpldst_d, lsdouble_d, prefetch_d, flush_d, |
| 2452 | memstbar_d, hpr_d, pr_d, sr_d, casa_d, ldstub_d, |
| 2453 | swap_d, sign_ext_d, lsize_d[1:0] |
| 2454 | }), |
| 2455 | .dout ({ fpldst_e, lsdouble_e, prefetch_e, flush_e, |
| 2456 | memstbar_e, hpr_e, pr_e, sr_e, casa_e, ldstub_e, |
| 2457 | swap_e, sign_ext_e, lsize_e[1:0] |
| 2458 | }), |
| 2459 | .siclk(siclk), |
| 2460 | .soclk(soclk) |
| 2461 | ); |
| 2462 | |
| 2463 | // These don't need to be qualified. They'll be used to qualify |
| 2464 | // a valid load or store. ML 10-26-04 |
| 2465 | assign dec_hpr_inst_e = hpr_e; |
| 2466 | assign dec_pr_inst_e = pr_e; |
| 2467 | assign dec_sr_inst_e = sr_e; |
| 2468 | assign dec_ldst_sz_e[1:0] = lsize_e[1:0]; |
| 2469 | assign dec_ldst_dbl_e = lsdouble_e; |
| 2470 | assign dec_casa_inst_e = casa_e; |
| 2471 | assign dec_ldstub_inst_e = ldstub_e; |
| 2472 | assign dec_swap_inst_e = swap_e; |
| 2473 | assign dec_sign_ext_e = sign_ext_e; |
| 2474 | assign dec_pref_inst_e = prefetch_e; |
| 2475 | |
| 2476 | assign dec_fpldst_inst_e = fpldst_e & lsu_valid_e; |
| 2477 | assign dec_flush_inst_e = flush_e & lsu_valid_e; |
| 2478 | assign dec_memstbar_inst_e = memstbar_e & lsu_valid_e; |
| 2479 | |
| 2480 | assign dec_imm_asi_d[7:0] = ({8{lsusel0_d}} & dec_inst0_opf_d[7:0]) | |
| 2481 | ({8{~lsusel0_d}} & dec_inst1_opf_d[7:0]); |
| 2482 | |
| 2483 | assign sraddr_d[4:0] = ({5{lsusel0_d}} & dec_inst0_rs1_d[4:0]) | |
| 2484 | ({5{~lsusel0_d}} & dec_inst1_rs1_d[4:0]); |
| 2485 | |
| 2486 | dec_del_ctl_msff_ctl_macro__width_5 sraddr_f ( |
| 2487 | .scan_in(sraddr_f_scanin), |
| 2488 | .scan_out(sraddr_f_scanout), |
| 2489 | .l1clk(l1clk), |
| 2490 | .din (sraddr_d[4:0]), |
| 2491 | .dout (sraddr_e[4:0]), |
| 2492 | .siclk(siclk), |
| 2493 | .soclk(soclk) |
| 2494 | ); |
| 2495 | |
| 2496 | assign dec_sraddr_e[4:0] = sraddr_e[4:0]; |
| 2497 | |
| 2498 | |
| 2499 | // lsu has valid operation at e stage (take annul into account) |
| 2500 | assign dec_lsu_tid0_d[1:0] = tid0_d[1:0]; |
| 2501 | assign dec_lsu_tid1_d[1:0] = tid1_d[1:0]; |
| 2502 | assign dec_lsu_tg_d = ~(~lfavor_real & lsu0_d & dec_valid0_d | (lfavor_real & ~(lsu1_d & dec_valid1_d))); |
| 2503 | |
| 2504 | |
| 2505 | assign lsu_rd0_msb = (idest0_d & (dec_inst0_raw_rd_d[4] ^ (dec_inst0_raw_rd_d[3] & ded_oddwin0_d))) | |
| 2506 | (~idest0_d & dec_inst0_raw_rd_d[4]); |
| 2507 | |
| 2508 | assign lsu_rd1_msb = (idest1_d & (dec_inst1_raw_rd_d[4] ^ (dec_inst1_raw_rd_d[3] & ded_oddwin1_d))) | |
| 2509 | (~idest1_d & dec_inst1_raw_rd_d[4]); |
| 2510 | |
| 2511 | assign lsu_rd_d[4:0] = ({5{lsusel0_d}} & {lsu_rd0_msb,dec_inst0_raw_rd_d[3:0]}) | |
| 2512 | ({5{~lsusel0_d}} & {lsu_rd1_msb,dec_inst1_raw_rd_d[3:0]}); |
| 2513 | |
| 2514 | dec_del_ctl_msff_ctl_macro__width_5 lsurd_f ( |
| 2515 | .scan_in(lsurd_f_scanin), |
| 2516 | .scan_out(lsurd_f_scanout), |
| 2517 | .l1clk(l1clk), |
| 2518 | .din (lsu_rd_d[4:0]), |
| 2519 | .dout (lsu_rd_e[4:0]), |
| 2520 | .siclk(siclk), |
| 2521 | .soclk(soclk) |
| 2522 | ); |
| 2523 | |
| 2524 | // decode_lsu0_e, decode_lsu1_e are hardened for illegal cases |
| 2525 | assign lsu_valid_e = (decode_lsu0_e & ls_valid_e[0]) | |
| 2526 | (decode_lsu1_e & ls_valid_e[1]); |
| 2527 | |
| 2528 | assign dec_lsu_rd_e[4:0] = lsu_rd_e[4:0]; |
| 2529 | |
| 2530 | // end lsu interface |
| 2531 | |
| 2532 | assign ds_m_in[1:0] = { |pku_ds_e[7:4], |pku_ds_e[3:0] } & ~ifetch_err_e[1:0]; |
| 2533 | |
| 2534 | dec_del_ctl_msff_ctl_macro__width_2 ds_m ( |
| 2535 | .scan_in(ds_m_scanin), |
| 2536 | .scan_out(ds_m_scanout), |
| 2537 | .l1clk(l1clk), |
| 2538 | .din (ds_m_in[1:0]), |
| 2539 | .dout (dec_ds_m[1:0]), |
| 2540 | .siclk(siclk), |
| 2541 | .soclk(soclk) |
| 2542 | ); |
| 2543 | |
| 2544 | assign annul_ds_dcti_e[7:4] = ({4{~br_taken_e[1]}} & pku_annul_ds_dcti_brtaken0_e[7:4]) | |
| 2545 | ({4{ br_taken_e[1]}} & pku_annul_ds_dcti_brtaken1_e[7:4]); |
| 2546 | |
| 2547 | assign annul_ds_dcti_e[3:0] = ({4{~br_taken_e[0]}} & pku_annul_ds_dcti_brtaken0_e[3:0]) | |
| 2548 | ({4{ br_taken_e[0]}} & pku_annul_ds_dcti_brtaken1_e[3:0]); |
| 2549 | |
| 2550 | assign annul_ds_m_in[1:0] = { |annul_ds_dcti_e[7:4], |annul_ds_dcti_e[3:0] } & ~ifetch_err_e[1:0]; |
| 2551 | |
| 2552 | dec_del_ctl_msff_ctl_macro__width_2 annul_m ( |
| 2553 | .scan_in(annul_m_scanin), |
| 2554 | .scan_out(annul_m_scanout), |
| 2555 | .l1clk(l1clk), |
| 2556 | .din (annul_ds_m_in[1:0]), |
| 2557 | .dout (dec_annul_ds_m[1:0]), |
| 2558 | .siclk(siclk), |
| 2559 | .soclk(soclk) |
| 2560 | ); |
| 2561 | |
| 2562 | dec_del_ctl_msff_ctl_macro__width_4 tid_e ( |
| 2563 | .scan_in(tid_e_scanin), |
| 2564 | .scan_out(tid_e_scanout), |
| 2565 | .l1clk(l1clk), |
| 2566 | .din ({tid1_d[1:0],tid0_d[1:0]}), |
| 2567 | .dout ({tid1_e[1:0],tid0_e[1:0]}), |
| 2568 | .siclk(siclk), |
| 2569 | .soclk(soclk) |
| 2570 | ); |
| 2571 | |
| 2572 | dec_del_ctl_msff_ctl_macro__width_4 tid_m ( |
| 2573 | .scan_in(tid_m_scanin), |
| 2574 | .scan_out(tid_m_scanout), |
| 2575 | .l1clk(l1clk), |
| 2576 | .din ({tid1_e[1:0],tid0_e[1:0]}), |
| 2577 | .dout ({dec_tid1_m[1:0],dec_tid0_m[1:0]}), |
| 2578 | .siclk(siclk), |
| 2579 | .soclk(soclk) |
| 2580 | ); |
| 2581 | |
| 2582 | dec_del_ctl_msff_ctl_macro__width_2 dec_e ( |
| 2583 | .scan_in(dec_e_scanin), |
| 2584 | .scan_out(dec_e_scanout), |
| 2585 | .l1clk(l1clk), |
| 2586 | .din ({dec_decode1_d,dec_decode0_d}), |
| 2587 | .dout ({decode1_raw_e,decode0_raw_e}), |
| 2588 | .siclk(siclk), |
| 2589 | .soclk(soclk) |
| 2590 | ); |
| 2591 | |
| 2592 | // send illegals to trap unit |
| 2593 | assign decode1_e = decode1_raw_e & valid_e[1]; |
| 2594 | assign decode0_e = decode0_raw_e & valid_e[0]; |
| 2595 | |
| 2596 | dec_del_ctl_msff_ctl_macro__width_2 dec_m ( |
| 2597 | .scan_in(dec_m_scanin), |
| 2598 | .scan_out(dec_m_scanout), |
| 2599 | .l1clk(l1clk), |
| 2600 | .din ({decode1_e,decode0_e}), |
| 2601 | .dout (inst_valid_m[1:0]), |
| 2602 | .siclk(siclk), |
| 2603 | .soclk(soclk) |
| 2604 | ); |
| 2605 | |
| 2606 | assign dec_inst_valid_m[1:0] = { ~dec_flush_m[1] & inst_valid_m[1], |
| 2607 | ~dec_flush_m[0] & inst_valid_m[0] }; |
| 2608 | |
| 2609 | assign store_float0_d = lsu0_d & fgu0_d; // only store-floats have both lsu and fgu asserted |
| 2610 | assign load_float0_d = lsu0_d & fdest0_d; // load-float only has lsu asserted along with fdest |
| 2611 | |
| 2612 | assign store_float1_d = lsu1_d & fgu1_d; |
| 2613 | assign load_float1_d = lsu1_d & fdest1_d; |
| 2614 | |
| 2615 | // fire this for all lsu ops and store-float |
| 2616 | assign is_lsu1_d = lsu1_d & ~ifetch_err_d[1]; |
| 2617 | assign is_lsu0_d = lsu0_d & ~ifetch_err_d[0]; |
| 2618 | |
| 2619 | // fire this for all fgu ops and store-float |
| 2620 | assign is_fgu1_d = fgu1_d & ~ifetch_err_d[1]; |
| 2621 | assign is_fgu0_d = fgu0_d & ~ifetch_err_d[0]; |
| 2622 | |
| 2623 | |
| 2624 | assign cti_d[1:0] = { dcd_callclass_d[1] | dcd_tcc_d[1] | dcd_specbr_d[1], |
| 2625 | dcd_callclass_d[0] | dcd_tcc_d[0] | dcd_specbr_d[0] }; |
| 2626 | |
| 2627 | dec_del_ctl_msff_ctl_macro__width_16 inst_e ( |
| 2628 | .scan_in(inst_e_scanin), |
| 2629 | .scan_out(inst_e_scanout), |
| 2630 | .l1clk(l1clk), |
| 2631 | .din ({ded_exc1_d[4:0],ded_exc0_d[4:0],is_lsu1_d,is_lsu0_d,is_fgu1_d,is_fgu0_d,cti_d[1:0]}), |
| 2632 | .dout ({exc1_e[4:0],exc0_e[4:0],is_lsu_e[1:0],is_fgu_e[1:0],cti_e[1:0]}), |
| 2633 | .siclk(siclk), |
| 2634 | .soclk(soclk) |
| 2635 | ); |
| 2636 | |
| 2637 | dec_del_ctl_msff_ctl_macro__width_16 inst_m ( |
| 2638 | .scan_in(inst_m_scanin), |
| 2639 | .scan_out(inst_m_scanout), |
| 2640 | .l1clk(l1clk), |
| 2641 | .din ({exc1_e[4:0],exc0_e[4:0],is_lsu_e[1:0],is_fgu_e[1:0],cti_e[1:0]}), |
| 2642 | .dout ({exc1_m[4:0],exc0_m[4:0],dec_lsu_inst_m[1:0],dec_fgu_inst_m[1:0],dec_cti_inst_m[1:0]}), |
| 2643 | .siclk(siclk), |
| 2644 | .soclk(soclk) |
| 2645 | ); |
| 2646 | |
| 2647 | assign dec_exc0_m[4:0] = exc0_m[4:0]; |
| 2648 | assign dec_exc1_m[4:0] = exc1_m[4:0]; |
| 2649 | |
| 2650 | |
| 2651 | assign flush_lexc_e= |((fpdisable_exc_e[1:0] | priv_exc_e[1:0] | hpriv_exc_e[1:0]) & is_lsu_e[1:0]); |
| 2652 | |
| 2653 | dec_del_ctl_msff_ctl_macro__width_1 flush_lexc_f ( |
| 2654 | .scan_in(flush_lexc_f_scanin), |
| 2655 | .scan_out(flush_lexc_f_scanout), |
| 2656 | .l1clk(l1clk), |
| 2657 | .din (flush_lexc_e), |
| 2658 | .dout (flush_lexc_m), |
| 2659 | .siclk(siclk), |
| 2660 | .soclk(soclk) |
| 2661 | ); |
| 2662 | |
| 2663 | dec_del_ctl_msff_ctl_macro__width_12 illegal_priv_m ( |
| 2664 | .scan_in(illegal_priv_m_scanin), |
| 2665 | .scan_out(illegal_priv_m_scanout), |
| 2666 | .l1clk(l1clk), |
| 2667 | .din ({illegal_e[1:0],priv_exc_e[1:0],hpriv_exc_e[1:0],fpdisable_exc_e[1:0],br_taken_e[1:0],icdp_perr_e[1:0]}), |
| 2668 | .dout ({illegal_inst_m[1:0],priv_exc_m[1:0],hpriv_exc_m[1:0],fpdisable_exc_m[1:0],br_taken_m[1:0],icdp_perr_m[1:0]}), |
| 2669 | .siclk(siclk), |
| 2670 | .soclk(soclk) |
| 2671 | ); |
| 2672 | |
| 2673 | assign dec_illegal_inst_m[1:0] = { ~dec_flush_m[1] & illegal_inst_m[1], |
| 2674 | ~dec_flush_m[0] & illegal_inst_m[0] }; |
| 2675 | |
| 2676 | assign dec_icache_perr_m[1:0] = { ~dec_flush_m[1] & icdp_perr_m[1], |
| 2677 | ~dec_flush_m[0] & icdp_perr_m[0] }; |
| 2678 | |
| 2679 | assign dec_priv_exc_m[1:0] = { ~dec_flush_m[1] & priv_exc_m[1], |
| 2680 | ~dec_flush_m[0] & priv_exc_m[0] }; |
| 2681 | |
| 2682 | assign dec_hpriv_exc_m[1:0] = { ~dec_flush_m[1] & hpriv_exc_m[1], |
| 2683 | ~dec_flush_m[0] & hpriv_exc_m[0] }; |
| 2684 | |
| 2685 | assign dec_fpdisable_exc_m[1:0] = { ~dec_flush_m[1] & fpdisable_exc_m[1], |
| 2686 | ~dec_flush_m[0] & fpdisable_exc_m[0] }; |
| 2687 | |
| 2688 | assign dec_br_taken_m[1:0] = { ~dec_flush_m[1] & br_taken_m[1], |
| 2689 | ~dec_flush_m[0] & br_taken_m[0] }; |
| 2690 | |
| 2691 | |
| 2692 | assign done_d[1:0] = dcd_done_d[1:0] & ~ifetch_err_d[1:0]; |
| 2693 | assign retry_d[1:0] = dcd_retry_d[1:0] & ~ifetch_err_d[1:0]; |
| 2694 | assign sir_d[1:0] = dcd_sir_d[1:0] & ~ifetch_err_d[1:0]; |
| 2695 | |
| 2696 | dec_del_ctl_msff_ctl_macro__width_6 done_retry_e ( |
| 2697 | .scan_in(done_retry_e_scanin), |
| 2698 | .scan_out(done_retry_e_scanout), |
| 2699 | .l1clk(l1clk), |
| 2700 | .din ({done_d[1:0],retry_d[1:0],sir_d[1:0]}), |
| 2701 | .dout ({done_e[1:0],retry_e[1:0],sir_e[1:0]}), |
| 2702 | .siclk(siclk), |
| 2703 | .soclk(soclk) |
| 2704 | ); |
| 2705 | |
| 2706 | dec_del_ctl_msff_ctl_macro__width_6 done_retry_m ( |
| 2707 | .scan_in(done_retry_m_scanin), |
| 2708 | .scan_out(done_retry_m_scanout), |
| 2709 | .l1clk(l1clk), |
| 2710 | .din ({done_e[1:0],retry_e[1:0],sir_e[1:0]}), |
| 2711 | .dout ({done_inst_m[1:0],retry_inst_m[1:0],sir_inst_m[1:0]}), |
| 2712 | .siclk(siclk), |
| 2713 | .soclk(soclk) |
| 2714 | ); |
| 2715 | |
| 2716 | assign dec_done_inst_m[1:0] = { ~dec_flush_m[1] & done_inst_m[1], |
| 2717 | ~dec_flush_m[0] & done_inst_m[0] }; |
| 2718 | |
| 2719 | assign dec_retry_inst_m[1:0] = { ~dec_flush_m[1] & retry_inst_m[1], |
| 2720 | ~dec_flush_m[0] & retry_inst_m[0] }; |
| 2721 | |
| 2722 | assign dec_sir_inst_m[1:0] = { ~dec_flush_m[1] & sir_inst_m[1], |
| 2723 | ~dec_flush_m[0] & sir_inst_m[0] }; |
| 2724 | |
| 2725 | // encodings for ded_exc0_d[4:0], ded_exc1_d[4:0] |
| 2726 | |
| 2727 | ///////////////////////////////////////////////////////////////// |
| 2728 | // no exception = 00000 // |
| 2729 | // tlb_miss (non-real) = 00001 E // |
| 2730 | // tlb_access_violation = 00010 E // |
| 2731 | // VA hole exception = 00011 E // |
| 2732 | // tlb real miss = 00100 E // |
| 2733 | // L2 MISS (for PMU) = 00101 // |
| 2734 | // IC MISS (for PMU) = 00110 // |
| 2735 | // ITLB tag parity error = 00111 E // |
| 2736 | // ITLB data parity error = 11111 E // |
| 2737 | // ITLB multiple hit = 01001 E // |
| 2738 | // icache valid (parity error) = 01010 E // |
| 2739 | // icache tag parity error = 01011 E // |
| 2740 | // icache tag multiple hit = 01100 E // |
| 2741 | // icache data parity error = 01101 E // |
| 2742 | // icache L2 correctable error = 01110 // |
| 2743 | // icache L2 uncorrectable error = 01111 E // |
| 2744 | // icache L2 NotData error = 10000 E // |
| 2745 | // ITLB NFO excp = 10001 E // |
| 2746 | // Real VA hole exception = 10011 E // |
| 2747 | |
| 2748 | ///////////////////////////////////////////////////////////////// |
| 2749 | // New codes added for fetching from I/O space that is not // |
| 2750 | // boot-rom area. Also added code points for l2_miss and errors// |
| 2751 | // together to more accurately count l2_miss in PMU. // |
| 2752 | // The new codes were chosen in such a way to minimize // |
| 2753 | // changes to existing testbenches and testcases. // |
| 2754 | |
| 2755 | // L2 miss and correctable error = 11110 // |
| 2756 | // L2 miss and uncorrectable err = 10111 E // |
| 2757 | // L2 miss and Notdata error = 11000 E // |
| 2758 | ///////////////////////////////////////////////////////////////// |
| 2759 | |
| 2760 | |
| 2761 | // pmu stuff |
| 2762 | // {12 - valid; 11:10 - tid; 9:0 - {atomic, l2imiss, itmiss, icmiss, other, %sethi, store, load, FGU, branch}} |
| 2763 | |
| 2764 | // pmu will use dec_valid_e[1:0] to qualify instructions; eliminate illegals |
| 2765 | |
| 2766 | assign atomic_d[0] = dcd_casa_d[0] | dcd_ldstub_d[0] | dcd_swap_d[0]; |
| 2767 | assign atomic_d[1] = dcd_casa_d[1] | dcd_ldstub_d[1] | dcd_swap_d[1]; |
| 2768 | |
| 2769 | assign l2miss0_d = (ded_exc0_d[4:0] == 5'b00101) | // l2miss |
| 2770 | (ded_exc0_d[4:0] == 5'b11110) | // l2 miss correctable error |
| 2771 | (ded_exc0_d[4:0] == 5'b10111) | // l2 miss uncorrectable error |
| 2772 | (ded_exc0_d[4:0] == 5'b11000); // l2 miss not data error |
| 2773 | |
| 2774 | assign l2miss1_d = (ded_exc1_d[4:0] == 5'b00101) | // l2miss |
| 2775 | (ded_exc1_d[4:0] == 5'b11110) | // l2 miss correctable error |
| 2776 | (ded_exc1_d[4:0] == 5'b10111) | // l2 miss uncorrectable error |
| 2777 | (ded_exc1_d[4:0] == 5'b11000); // l2 miss not data error |
| 2778 | |
| 2779 | |
| 2780 | assign itlbmiss0_d = (ded_exc0_d[4:0] == 5'b00001) | // tlb miss non-real |
| 2781 | (ded_exc0_d[4:0] == 5'b00100); // tlb miss real |
| 2782 | |
| 2783 | assign itlbmiss1_d = (ded_exc1_d[4:0] == 5'b00001) | // tlb miss non-real |
| 2784 | (ded_exc1_d[4:0] == 5'b00100); // tlb miss real |
| 2785 | |
| 2786 | assign icmiss0_d = (ded_exc0_d[4:0] == 5'b00110) | // ic miss |
| 2787 | (ded_exc0_d[4:0] == 5'b01110) | // l2 correctable error |
| 2788 | (ded_exc0_d[4:0] == 5'b01111) | // l2 uncorrectable error |
| 2789 | (ded_exc0_d[4:0] == 5'b10000) | // l2 not data error |
| 2790 | (ded_exc0_d[4:0] == 5'b11110) | // l2 miss correctable error |
| 2791 | (ded_exc0_d[4:0] == 5'b10111) | // l2 miss uncorrectable error |
| 2792 | (ded_exc0_d[4:0] == 5'b11000) | // l2 miss notdata error |
| 2793 | (ded_exc0_d[4:0] == 5'b00101); // l2 miss |
| 2794 | |
| 2795 | assign icmiss1_d = (ded_exc1_d[4:0] == 5'b00110) | // ic miss |
| 2796 | (ded_exc1_d[4:0] == 5'b01110) | // l2 correctable error |
| 2797 | (ded_exc1_d[4:0] == 5'b01111) | // l2 uncorrectable error |
| 2798 | (ded_exc1_d[4:0] == 5'b10000) | // l2 not data error |
| 2799 | (ded_exc1_d[4:0] == 5'b11110) | // l2 miss correctable error |
| 2800 | (ded_exc1_d[4:0] == 5'b10111) | // l2 miss uncorrectable error |
| 2801 | (ded_exc1_d[4:0] == 5'b11000) | // l2 miss notdata error |
| 2802 | (ded_exc1_d[4:0] == 5'b00101); // l2 miss |
| 2803 | |
| 2804 | |
| 2805 | |
| 2806 | assign other0_d = ~(dcd_sethi_d[0] | dcd_store_d[0] | dcd_load_d[0] | dcd_specfp_d[0] | branch0_d); |
| 2807 | assign other1_d = ~(dcd_sethi_d[1] | dcd_store_d[1] | dcd_load_d[1] | dcd_specfp_d[1] | branch1_d); |
| 2808 | |
| 2809 | assign branch0_d = dcd_specbr_d[0] | dcd_callclass_d[0]; |
| 2810 | assign branch1_d = dcd_specbr_d[1] | dcd_callclass_d[1]; |
| 2811 | |
| 2812 | assign dec_instr0_type_d[9:0] = { atomic_d[0], l2miss0_d, itlbmiss0_d, icmiss0_d, other0_d, dcd_sethi_d[0], dcd_store_d[0], |
| 2813 | dcd_load_d[0], dcd_specfp_d[0], branch0_d }; |
| 2814 | |
| 2815 | assign dec_instr1_type_d[9:0] = { atomic_d[1], l2miss1_d, itlbmiss1_d, icmiss1_d, other1_d, dcd_sethi_d[1], dcd_store_d[1], |
| 2816 | dcd_load_d[1], dcd_specfp_d[1], branch1_d }; |
| 2817 | |
| 2818 | // power throttle |
| 2819 | |
| 2820 | // por state is all all zeroes |
| 2821 | |
| 2822 | dec_del_ctl_msff_ctl_macro__width_8 power_stall1f ( |
| 2823 | .scan_in(power_stall1f_scanin), |
| 2824 | .scan_out(power_stall1f_scanout), |
| 2825 | .l1clk(l1clk), |
| 2826 | .din (power_stall_in[7:0]), |
| 2827 | .dout (power_stall[7:0]), |
| 2828 | .siclk(siclk), |
| 2829 | .soclk(soclk) |
| 2830 | ); |
| 2831 | |
| 2832 | |
| 2833 | dec_del_ctl_msff_ctl_macro__width_8 thread_activef ( |
| 2834 | .scan_in(thread_activef_scanin), |
| 2835 | .scan_out(thread_activef_scanout), |
| 2836 | .l1clk(l1clk), |
| 2837 | .din (spc_core_running_status[7:0]), |
| 2838 | .dout (thread_active[7:0]), |
| 2839 | .siclk(siclk), |
| 2840 | .soclk(soclk) |
| 2841 | ); |
| 2842 | |
| 2843 | assign del_tg_clken[1:0] = { (|thread_active[7:4]) | ~lsu_dec_pmen, (|thread_active[3:0]) | ~lsu_dec_pmen }; |
| 2844 | |
| 2845 | dec_del_ctl_msff_ctl_macro__width_3 power_throttle1f ( |
| 2846 | .scan_in(power_throttle1f_scanin), |
| 2847 | .scan_out(power_throttle1f_scanout), |
| 2848 | .l1clk(l1clk), |
| 2849 | .din (power_throt0[2:0]), |
| 2850 | .dout (power_throttle1[2:0]), |
| 2851 | .siclk(siclk), |
| 2852 | .soclk(soclk) |
| 2853 | ); |
| 2854 | |
| 2855 | |
| 2856 | // special synchronizer for taking in primary inputs to chip |
| 2857 | cl_sc1_clksyncff_4x power_throttle02_f ( |
| 2858 | .l1clk(l1clk), |
| 2859 | .si(power_throttle02_f_scanin), |
| 2860 | .so(power_throttle02_f_scanout), |
| 2861 | .d(power_throttle[2]), |
| 2862 | .q(power_throttle0[2]), |
| 2863 | .siclk(siclk), |
| 2864 | .soclk(soclk) |
| 2865 | ); |
| 2866 | |
| 2867 | cl_sc1_clksyncff_4x power_throttle01_f ( |
| 2868 | .l1clk(l1clk), |
| 2869 | .si(power_throttle01_f_scanin), |
| 2870 | .so(power_throttle01_f_scanout), |
| 2871 | .d(power_throttle[1]), |
| 2872 | .q(power_throttle0[1]), |
| 2873 | .siclk(siclk), |
| 2874 | .soclk(soclk) |
| 2875 | ); |
| 2876 | |
| 2877 | cl_sc1_clksyncff_4x power_throttle00_f ( |
| 2878 | .l1clk(l1clk), |
| 2879 | .si(power_throttle00_f_scanin), |
| 2880 | .so(power_throttle00_f_scanout), |
| 2881 | .d(power_throttle[0]), |
| 2882 | .q(power_throttle0[0]), |
| 2883 | .siclk(siclk), |
| 2884 | .soclk(soclk) |
| 2885 | ); |
| 2886 | |
| 2887 | assign power_throt0[2:0] = ~{3 {lb_lbist_running}} & power_throttle0[2:0]; |
| 2888 | |
| 2889 | //// dont use power_throttle_unsafe[]; avoid metastable issue |
| 2890 | //msff_ctl_macro power_throttle_unsafef (width=3) ( |
| 2891 | // .scan_in(power_throttle_unsafef_scanin), |
| 2892 | // .scan_out(power_throttle_unsafef_scanout), |
| 2893 | // .l1clk(l1clk), |
| 2894 | // .din (power_throttle[2:0]), |
| 2895 | // .dout (power_throttle_unsafe[2:0]) |
| 2896 | //); |
| 2897 | // |
| 2898 | //msff_ctl_macro power_throttle0f (width=3) ( |
| 2899 | // .scan_in(power_throttle0f_scanin), |
| 2900 | // .scan_out(power_throttle0f_scanout), |
| 2901 | // .l1clk(l1clk), |
| 2902 | // .din (power_throttle_unsafe[2:0]), |
| 2903 | // .dout (power_throttle0[2:0]) |
| 2904 | //); |
| 2905 | |
| 2906 | |
| 2907 | |
| 2908 | assign change_power_stall = (power_throt0[2:0] != power_throttle1[2:0]); |
| 2909 | |
| 2910 | assign new_power_stall[7:0] = ( ({8{power_throt0[2:0]==3'b000}} & 8'b00000000) | |
| 2911 | ({8{power_throt0[2:0]==3'b001}} & 8'b00000001) | |
| 2912 | ({8{power_throt0[2:0]==3'b010}} & 8'b00010001) | |
| 2913 | ({8{power_throt0[2:0]==3'b011}} & 8'b00100101) | |
| 2914 | ({8{power_throt0[2:0]==3'b100}} & 8'b01010101) | |
| 2915 | ({8{power_throt0[2:0]==3'b101}} & 8'b11011010) | |
| 2916 | ({8{power_throt0[2:0]==3'b110}} & 8'b11101110) | |
| 2917 | ({8{power_throt0[2:0]==3'b111}} & 8'b11111110) ); |
| 2918 | |
| 2919 | assign power_stall_in[7:0] = ({8{change_power_stall}} & new_power_stall[7:0]) | |
| 2920 | ({8{~change_power_stall}} & {power_stall[6:0],power_stall[7]}); |
| 2921 | |
| 2922 | |
| 2923 | supply0 vss; |
| 2924 | supply1 vdd; |
| 2925 | |
| 2926 | // fixscan start: |
| 2927 | assign spares_scanin = scan_in ; |
| 2928 | assign pdecode0f_scanin = spares_scanout ; |
| 2929 | assign pdecode1f_scanin = pdecode0f_scanout ; |
| 2930 | assign pick0f_scanin = pdecode1f_scanout ; |
| 2931 | assign pick1f_scanin = pick0f_scanout ; |
| 2932 | assign privstatef_scanin = pick1f_scanout ; |
| 2933 | assign fef_scanin = privstatef_scanout ; |
| 2934 | assign instcntf_scanin = fef_scanout ; |
| 2935 | assign exutestf_scanin = instcntf_scanout ; |
| 2936 | assign teststallf_scanin = exutestf_scanout ; |
| 2937 | assign val_df_scanin = teststallf_scanout ; |
| 2938 | assign valid_df_scanin = val_df_scanout ; |
| 2939 | assign dtlb_reloadf_scanin = valid_df_scanout ; |
| 2940 | assign block_store0f_scanin = dtlb_reloadf_scanout ; |
| 2941 | assign block_storef_scanin = block_store0f_scanout ; |
| 2942 | assign block_store_rdhif_scanin = block_storef_scanout ; |
| 2943 | assign block_store_rdlof_scanin = block_store_rdhif_scanout; |
| 2944 | assign block_store_tidf_scanin = block_store_rdlof_scanout; |
| 2945 | assign cpq_stallf_scanin = block_store_tidf_scanout ; |
| 2946 | assign fecc_stallf_scanin = cpq_stallf_scanout ; |
| 2947 | assign block_resetf_scanin = fecc_stallf_scanout ; |
| 2948 | assign block_store_e_scanin = block_resetf_scanout ; |
| 2949 | assign block_store_m_scanin = block_store_e_scanout ; |
| 2950 | assign block_store_b_scanin = block_store_m_scanout ; |
| 2951 | assign lfavorf_scanin = block_store_b_scanout ; |
| 2952 | assign ffavorf_scanin = lfavorf_scanout ; |
| 2953 | assign sffavorf_scanin = ffavorf_scanout ; |
| 2954 | assign mulrequestf_scanin = sffavorf_scanout ; |
| 2955 | assign cmfavorf_scanin = mulrequestf_scanout ; |
| 2956 | assign pdistblockf_scanin = cmfavorf_scanout ; |
| 2957 | assign pdistrdf_scanin = pdistblockf_scanout ; |
| 2958 | assign pdisttidf_scanin = pdistrdf_scanout ; |
| 2959 | assign twocycle0_df_scanin = pdisttidf_scanout ; |
| 2960 | assign twocycle1_df_scanin = twocycle0_df_scanout ; |
| 2961 | assign inthole0_df_scanin = twocycle1_df_scanout ; |
| 2962 | assign inthole1_df_scanin = inthole0_df_scanout ; |
| 2963 | assign divstall_df_scanin = inthole1_df_scanout ; |
| 2964 | assign windowstall_df_scanin = divstall_df_scanout ; |
| 2965 | assign exu_clkenf_scanin = windowstall_df_scanout ; |
| 2966 | assign legal_f_scanin = exu_clkenf_scanout ; |
| 2967 | assign illegal_f_scanin = legal_f_scanout ; |
| 2968 | assign fpdisable_exc_f_scanin = illegal_f_scanout ; |
| 2969 | assign parity_err_f_scanin = fpdisable_exc_f_scanout ; |
| 2970 | assign exc_f_scanin = parity_err_f_scanout ; |
| 2971 | assign tgsel_f_scanin = exc_f_scanout ; |
| 2972 | assign exuself_scanin = tgsel_f_scanout ; |
| 2973 | assign tgselm_f_scanin = exuself_scanout ; |
| 2974 | assign frf_r2addre_f_scanin = tgselm_f_scanout ; |
| 2975 | assign ifetch_err_f_scanin = frf_r2addre_f_scanout ; |
| 2976 | assign ifetcherr_f_scanin = ifetch_err_f_scanout ; |
| 2977 | assign truevalid_f_scanin = ifetcherr_f_scanout ; |
| 2978 | assign fgudec_f_scanin = truevalid_f_scanout ; |
| 2979 | assign lsudec_f_scanin = fgudec_f_scanout ; |
| 2980 | assign ldste_f_scanin = lsudec_f_scanout ; |
| 2981 | assign ldme_f_scanin = ldste_f_scanout ; |
| 2982 | assign sraddr_f_scanin = ldme_f_scanout ; |
| 2983 | assign lsurd_f_scanin = sraddr_f_scanout ; |
| 2984 | assign ds_m_scanin = lsurd_f_scanout ; |
| 2985 | assign annul_m_scanin = ds_m_scanout ; |
| 2986 | assign tid_e_scanin = annul_m_scanout ; |
| 2987 | assign tid_m_scanin = tid_e_scanout ; |
| 2988 | assign dec_e_scanin = tid_m_scanout ; |
| 2989 | assign dec_m_scanin = dec_e_scanout ; |
| 2990 | assign inst_e_scanin = dec_m_scanout ; |
| 2991 | assign inst_m_scanin = inst_e_scanout ; |
| 2992 | assign flush_lexc_f_scanin = inst_m_scanout ; |
| 2993 | assign illegal_priv_m_scanin = flush_lexc_f_scanout ; |
| 2994 | assign done_retry_e_scanin = illegal_priv_m_scanout ; |
| 2995 | assign done_retry_m_scanin = done_retry_e_scanout ; |
| 2996 | assign power_stall1f_scanin = done_retry_m_scanout ; |
| 2997 | assign thread_activef_scanin = power_stall1f_scanout ; |
| 2998 | assign power_throttle1f_scanin = thread_activef_scanout ; |
| 2999 | assign power_throttle02_f_scanin = power_throttle1f_scanout ; |
| 3000 | assign power_throttle01_f_scanin = power_throttle02_f_scanout ; // these connections must be done by hand |
| 3001 | assign power_throttle00_f_scanin = power_throttle01_f_scanout ; |
| 3002 | assign scan_out = power_throttle00_f_scanout ; |
| 3003 | // fixscan end: |
| 3004 | endmodule |
| 3005 | |
| 3006 | |
| 3007 | |
| 3008 | |
| 3009 | |
| 3010 | |
| 3011 | // any PARAMS parms go into naming of macro |
| 3012 | |
| 3013 | module dec_del_ctl_l1clkhdr_ctl_macro ( |
| 3014 | l2clk, |
| 3015 | l1en, |
| 3016 | pce_ov, |
| 3017 | stop, |
| 3018 | se, |
| 3019 | l1clk); |
| 3020 | |
| 3021 | |
| 3022 | input l2clk; |
| 3023 | input l1en; |
| 3024 | input pce_ov; |
| 3025 | input stop; |
| 3026 | input se; |
| 3027 | output l1clk; |
| 3028 | |
| 3029 | |
| 3030 | |
| 3031 | |
| 3032 | |
| 3033 | cl_sc1_l1hdr_8x c_0 ( |
| 3034 | |
| 3035 | |
| 3036 | .l2clk(l2clk), |
| 3037 | .pce(l1en), |
| 3038 | .l1clk(l1clk), |
| 3039 | .se(se), |
| 3040 | .pce_ov(pce_ov), |
| 3041 | .stop(stop) |
| 3042 | ); |
| 3043 | |
| 3044 | |
| 3045 | |
| 3046 | endmodule |
| 3047 | |
| 3048 | |
| 3049 | |
| 3050 | |
| 3051 | |
| 3052 | |
| 3053 | |
| 3054 | |
| 3055 | |
| 3056 | // Description: Spare gate macro for control blocks |
| 3057 | // |
| 3058 | // Param num controls the number of times the macro is added |
| 3059 | // flops=0 can be used to use only combination spare logic |
| 3060 | |
| 3061 | |
| 3062 | module dec_del_ctl_spare_ctl_macro__flops_0__num_6; |
| 3063 | wire spare0_buf_32x_unused; |
| 3064 | wire spare0_nand3_8x_unused; |
| 3065 | wire spare0_inv_8x_unused; |
| 3066 | wire spare0_aoi22_4x_unused; |
| 3067 | wire spare0_buf_8x_unused; |
| 3068 | wire spare0_oai22_4x_unused; |
| 3069 | wire spare0_inv_16x_unused; |
| 3070 | wire spare0_nand2_16x_unused; |
| 3071 | wire spare0_nor3_4x_unused; |
| 3072 | wire spare0_nand2_8x_unused; |
| 3073 | wire spare0_buf_16x_unused; |
| 3074 | wire spare0_nor2_16x_unused; |
| 3075 | wire spare0_inv_32x_unused; |
| 3076 | wire spare1_buf_32x_unused; |
| 3077 | wire spare1_nand3_8x_unused; |
| 3078 | wire spare1_inv_8x_unused; |
| 3079 | wire spare1_aoi22_4x_unused; |
| 3080 | wire spare1_buf_8x_unused; |
| 3081 | wire spare1_oai22_4x_unused; |
| 3082 | wire spare1_inv_16x_unused; |
| 3083 | wire spare1_nand2_16x_unused; |
| 3084 | wire spare1_nor3_4x_unused; |
| 3085 | wire spare1_nand2_8x_unused; |
| 3086 | wire spare1_buf_16x_unused; |
| 3087 | wire spare1_nor2_16x_unused; |
| 3088 | wire spare1_inv_32x_unused; |
| 3089 | wire spare2_buf_32x_unused; |
| 3090 | wire spare2_nand3_8x_unused; |
| 3091 | wire spare2_inv_8x_unused; |
| 3092 | wire spare2_aoi22_4x_unused; |
| 3093 | wire spare2_buf_8x_unused; |
| 3094 | wire spare2_oai22_4x_unused; |
| 3095 | wire spare2_inv_16x_unused; |
| 3096 | wire spare2_nand2_16x_unused; |
| 3097 | wire spare2_nor3_4x_unused; |
| 3098 | wire spare2_nand2_8x_unused; |
| 3099 | wire spare2_buf_16x_unused; |
| 3100 | wire spare2_nor2_16x_unused; |
| 3101 | wire spare2_inv_32x_unused; |
| 3102 | wire spare3_buf_32x_unused; |
| 3103 | wire spare3_nand3_8x_unused; |
| 3104 | wire spare3_inv_8x_unused; |
| 3105 | wire spare3_aoi22_4x_unused; |
| 3106 | wire spare3_buf_8x_unused; |
| 3107 | wire spare3_oai22_4x_unused; |
| 3108 | wire spare3_inv_16x_unused; |
| 3109 | wire spare3_nand2_16x_unused; |
| 3110 | wire spare3_nor3_4x_unused; |
| 3111 | wire spare3_nand2_8x_unused; |
| 3112 | wire spare3_buf_16x_unused; |
| 3113 | wire spare3_nor2_16x_unused; |
| 3114 | wire spare3_inv_32x_unused; |
| 3115 | wire spare4_buf_32x_unused; |
| 3116 | wire spare4_nand3_8x_unused; |
| 3117 | wire spare4_inv_8x_unused; |
| 3118 | wire spare4_aoi22_4x_unused; |
| 3119 | wire spare4_buf_8x_unused; |
| 3120 | wire spare4_oai22_4x_unused; |
| 3121 | wire spare4_inv_16x_unused; |
| 3122 | wire spare4_nand2_16x_unused; |
| 3123 | wire spare4_nor3_4x_unused; |
| 3124 | wire spare4_nand2_8x_unused; |
| 3125 | wire spare4_buf_16x_unused; |
| 3126 | wire spare4_nor2_16x_unused; |
| 3127 | wire spare4_inv_32x_unused; |
| 3128 | wire spare5_buf_32x_unused; |
| 3129 | wire spare5_nand3_8x_unused; |
| 3130 | wire spare5_inv_8x_unused; |
| 3131 | wire spare5_aoi22_4x_unused; |
| 3132 | wire spare5_buf_8x_unused; |
| 3133 | wire spare5_oai22_4x_unused; |
| 3134 | wire spare5_inv_16x_unused; |
| 3135 | wire spare5_nand2_16x_unused; |
| 3136 | wire spare5_nor3_4x_unused; |
| 3137 | wire spare5_nand2_8x_unused; |
| 3138 | wire spare5_buf_16x_unused; |
| 3139 | wire spare5_nor2_16x_unused; |
| 3140 | wire spare5_inv_32x_unused; |
| 3141 | |
| 3142 | |
| 3143 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 3144 | .out(spare0_buf_32x_unused)); |
| 3145 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 3146 | .in1(1'b1), |
| 3147 | .in2(1'b1), |
| 3148 | .out(spare0_nand3_8x_unused)); |
| 3149 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 3150 | .out(spare0_inv_8x_unused)); |
| 3151 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 3152 | .in01(1'b1), |
| 3153 | .in10(1'b1), |
| 3154 | .in11(1'b1), |
| 3155 | .out(spare0_aoi22_4x_unused)); |
| 3156 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 3157 | .out(spare0_buf_8x_unused)); |
| 3158 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 3159 | .in01(1'b1), |
| 3160 | .in10(1'b1), |
| 3161 | .in11(1'b1), |
| 3162 | .out(spare0_oai22_4x_unused)); |
| 3163 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 3164 | .out(spare0_inv_16x_unused)); |
| 3165 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 3166 | .in1(1'b1), |
| 3167 | .out(spare0_nand2_16x_unused)); |
| 3168 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 3169 | .in1(1'b0), |
| 3170 | .in2(1'b0), |
| 3171 | .out(spare0_nor3_4x_unused)); |
| 3172 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 3173 | .in1(1'b1), |
| 3174 | .out(spare0_nand2_8x_unused)); |
| 3175 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 3176 | .out(spare0_buf_16x_unused)); |
| 3177 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 3178 | .in1(1'b0), |
| 3179 | .out(spare0_nor2_16x_unused)); |
| 3180 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 3181 | .out(spare0_inv_32x_unused)); |
| 3182 | |
| 3183 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 3184 | .out(spare1_buf_32x_unused)); |
| 3185 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 3186 | .in1(1'b1), |
| 3187 | .in2(1'b1), |
| 3188 | .out(spare1_nand3_8x_unused)); |
| 3189 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 3190 | .out(spare1_inv_8x_unused)); |
| 3191 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 3192 | .in01(1'b1), |
| 3193 | .in10(1'b1), |
| 3194 | .in11(1'b1), |
| 3195 | .out(spare1_aoi22_4x_unused)); |
| 3196 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 3197 | .out(spare1_buf_8x_unused)); |
| 3198 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 3199 | .in01(1'b1), |
| 3200 | .in10(1'b1), |
| 3201 | .in11(1'b1), |
| 3202 | .out(spare1_oai22_4x_unused)); |
| 3203 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 3204 | .out(spare1_inv_16x_unused)); |
| 3205 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 3206 | .in1(1'b1), |
| 3207 | .out(spare1_nand2_16x_unused)); |
| 3208 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 3209 | .in1(1'b0), |
| 3210 | .in2(1'b0), |
| 3211 | .out(spare1_nor3_4x_unused)); |
| 3212 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 3213 | .in1(1'b1), |
| 3214 | .out(spare1_nand2_8x_unused)); |
| 3215 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 3216 | .out(spare1_buf_16x_unused)); |
| 3217 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 3218 | .in1(1'b0), |
| 3219 | .out(spare1_nor2_16x_unused)); |
| 3220 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 3221 | .out(spare1_inv_32x_unused)); |
| 3222 | |
| 3223 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 3224 | .out(spare2_buf_32x_unused)); |
| 3225 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 3226 | .in1(1'b1), |
| 3227 | .in2(1'b1), |
| 3228 | .out(spare2_nand3_8x_unused)); |
| 3229 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 3230 | .out(spare2_inv_8x_unused)); |
| 3231 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 3232 | .in01(1'b1), |
| 3233 | .in10(1'b1), |
| 3234 | .in11(1'b1), |
| 3235 | .out(spare2_aoi22_4x_unused)); |
| 3236 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 3237 | .out(spare2_buf_8x_unused)); |
| 3238 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 3239 | .in01(1'b1), |
| 3240 | .in10(1'b1), |
| 3241 | .in11(1'b1), |
| 3242 | .out(spare2_oai22_4x_unused)); |
| 3243 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 3244 | .out(spare2_inv_16x_unused)); |
| 3245 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 3246 | .in1(1'b1), |
| 3247 | .out(spare2_nand2_16x_unused)); |
| 3248 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 3249 | .in1(1'b0), |
| 3250 | .in2(1'b0), |
| 3251 | .out(spare2_nor3_4x_unused)); |
| 3252 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 3253 | .in1(1'b1), |
| 3254 | .out(spare2_nand2_8x_unused)); |
| 3255 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 3256 | .out(spare2_buf_16x_unused)); |
| 3257 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 3258 | .in1(1'b0), |
| 3259 | .out(spare2_nor2_16x_unused)); |
| 3260 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 3261 | .out(spare2_inv_32x_unused)); |
| 3262 | |
| 3263 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 3264 | .out(spare3_buf_32x_unused)); |
| 3265 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 3266 | .in1(1'b1), |
| 3267 | .in2(1'b1), |
| 3268 | .out(spare3_nand3_8x_unused)); |
| 3269 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 3270 | .out(spare3_inv_8x_unused)); |
| 3271 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 3272 | .in01(1'b1), |
| 3273 | .in10(1'b1), |
| 3274 | .in11(1'b1), |
| 3275 | .out(spare3_aoi22_4x_unused)); |
| 3276 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 3277 | .out(spare3_buf_8x_unused)); |
| 3278 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 3279 | .in01(1'b1), |
| 3280 | .in10(1'b1), |
| 3281 | .in11(1'b1), |
| 3282 | .out(spare3_oai22_4x_unused)); |
| 3283 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 3284 | .out(spare3_inv_16x_unused)); |
| 3285 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 3286 | .in1(1'b1), |
| 3287 | .out(spare3_nand2_16x_unused)); |
| 3288 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 3289 | .in1(1'b0), |
| 3290 | .in2(1'b0), |
| 3291 | .out(spare3_nor3_4x_unused)); |
| 3292 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 3293 | .in1(1'b1), |
| 3294 | .out(spare3_nand2_8x_unused)); |
| 3295 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 3296 | .out(spare3_buf_16x_unused)); |
| 3297 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 3298 | .in1(1'b0), |
| 3299 | .out(spare3_nor2_16x_unused)); |
| 3300 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 3301 | .out(spare3_inv_32x_unused)); |
| 3302 | |
| 3303 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), |
| 3304 | .out(spare4_buf_32x_unused)); |
| 3305 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), |
| 3306 | .in1(1'b1), |
| 3307 | .in2(1'b1), |
| 3308 | .out(spare4_nand3_8x_unused)); |
| 3309 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), |
| 3310 | .out(spare4_inv_8x_unused)); |
| 3311 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), |
| 3312 | .in01(1'b1), |
| 3313 | .in10(1'b1), |
| 3314 | .in11(1'b1), |
| 3315 | .out(spare4_aoi22_4x_unused)); |
| 3316 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), |
| 3317 | .out(spare4_buf_8x_unused)); |
| 3318 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), |
| 3319 | .in01(1'b1), |
| 3320 | .in10(1'b1), |
| 3321 | .in11(1'b1), |
| 3322 | .out(spare4_oai22_4x_unused)); |
| 3323 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), |
| 3324 | .out(spare4_inv_16x_unused)); |
| 3325 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), |
| 3326 | .in1(1'b1), |
| 3327 | .out(spare4_nand2_16x_unused)); |
| 3328 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), |
| 3329 | .in1(1'b0), |
| 3330 | .in2(1'b0), |
| 3331 | .out(spare4_nor3_4x_unused)); |
| 3332 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), |
| 3333 | .in1(1'b1), |
| 3334 | .out(spare4_nand2_8x_unused)); |
| 3335 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), |
| 3336 | .out(spare4_buf_16x_unused)); |
| 3337 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), |
| 3338 | .in1(1'b0), |
| 3339 | .out(spare4_nor2_16x_unused)); |
| 3340 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), |
| 3341 | .out(spare4_inv_32x_unused)); |
| 3342 | |
| 3343 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), |
| 3344 | .out(spare5_buf_32x_unused)); |
| 3345 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), |
| 3346 | .in1(1'b1), |
| 3347 | .in2(1'b1), |
| 3348 | .out(spare5_nand3_8x_unused)); |
| 3349 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), |
| 3350 | .out(spare5_inv_8x_unused)); |
| 3351 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), |
| 3352 | .in01(1'b1), |
| 3353 | .in10(1'b1), |
| 3354 | .in11(1'b1), |
| 3355 | .out(spare5_aoi22_4x_unused)); |
| 3356 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), |
| 3357 | .out(spare5_buf_8x_unused)); |
| 3358 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), |
| 3359 | .in01(1'b1), |
| 3360 | .in10(1'b1), |
| 3361 | .in11(1'b1), |
| 3362 | .out(spare5_oai22_4x_unused)); |
| 3363 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), |
| 3364 | .out(spare5_inv_16x_unused)); |
| 3365 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), |
| 3366 | .in1(1'b1), |
| 3367 | .out(spare5_nand2_16x_unused)); |
| 3368 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), |
| 3369 | .in1(1'b0), |
| 3370 | .in2(1'b0), |
| 3371 | .out(spare5_nor3_4x_unused)); |
| 3372 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), |
| 3373 | .in1(1'b1), |
| 3374 | .out(spare5_nand2_8x_unused)); |
| 3375 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), |
| 3376 | .out(spare5_buf_16x_unused)); |
| 3377 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), |
| 3378 | .in1(1'b0), |
| 3379 | .out(spare5_nor2_16x_unused)); |
| 3380 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), |
| 3381 | .out(spare5_inv_32x_unused)); |
| 3382 | |
| 3383 | |
| 3384 | |
| 3385 | endmodule |
| 3386 | |
| 3387 | |
| 3388 | |
| 3389 | |
| 3390 | |
| 3391 | |
| 3392 | // any PARAMS parms go into naming of macro |
| 3393 | |
| 3394 | module dec_del_ctl_msff_ctl_macro__scanreverse_1__width_6 ( |
| 3395 | din, |
| 3396 | l1clk, |
| 3397 | scan_in, |
| 3398 | siclk, |
| 3399 | soclk, |
| 3400 | dout, |
| 3401 | scan_out); |
| 3402 | wire [5:0] fdin; |
| 3403 | wire [0:4] so; |
| 3404 | |
| 3405 | input [5:0] din; |
| 3406 | input l1clk; |
| 3407 | input scan_in; |
| 3408 | |
| 3409 | |
| 3410 | input siclk; |
| 3411 | input soclk; |
| 3412 | |
| 3413 | output [5:0] dout; |
| 3414 | output scan_out; |
| 3415 | assign fdin[5:0] = din[5:0]; |
| 3416 | |
| 3417 | |
| 3418 | |
| 3419 | |
| 3420 | |
| 3421 | |
| 3422 | dff #(6) d0_0 ( |
| 3423 | .l1clk(l1clk), |
| 3424 | .siclk(siclk), |
| 3425 | .soclk(soclk), |
| 3426 | .d(fdin[5:0]), |
| 3427 | .si({so[0:4],scan_in}), |
| 3428 | .so({scan_out,so[0:4]}), |
| 3429 | .q(dout[5:0]) |
| 3430 | ); |
| 3431 | |
| 3432 | |
| 3433 | |
| 3434 | |
| 3435 | |
| 3436 | |
| 3437 | |
| 3438 | |
| 3439 | |
| 3440 | |
| 3441 | |
| 3442 | |
| 3443 | endmodule |
| 3444 | |
| 3445 | |
| 3446 | |
| 3447 | |
| 3448 | |
| 3449 | |
| 3450 | |
| 3451 | |
| 3452 | |
| 3453 | |
| 3454 | |
| 3455 | |
| 3456 | |
| 3457 | // any PARAMS parms go into naming of macro |
| 3458 | |
| 3459 | module dec_del_ctl_msff_ctl_macro__width_7 ( |
| 3460 | din, |
| 3461 | l1clk, |
| 3462 | scan_in, |
| 3463 | siclk, |
| 3464 | soclk, |
| 3465 | dout, |
| 3466 | scan_out); |
| 3467 | wire [6:0] fdin; |
| 3468 | wire [5:0] so; |
| 3469 | |
| 3470 | input [6:0] din; |
| 3471 | input l1clk; |
| 3472 | input scan_in; |
| 3473 | |
| 3474 | |
| 3475 | input siclk; |
| 3476 | input soclk; |
| 3477 | |
| 3478 | output [6:0] dout; |
| 3479 | output scan_out; |
| 3480 | assign fdin[6:0] = din[6:0]; |
| 3481 | |
| 3482 | |
| 3483 | |
| 3484 | |
| 3485 | |
| 3486 | |
| 3487 | dff #(7) d0_0 ( |
| 3488 | .l1clk(l1clk), |
| 3489 | .siclk(siclk), |
| 3490 | .soclk(soclk), |
| 3491 | .d(fdin[6:0]), |
| 3492 | .si({scan_in,so[5:0]}), |
| 3493 | .so({so[5:0],scan_out}), |
| 3494 | .q(dout[6:0]) |
| 3495 | ); |
| 3496 | |
| 3497 | |
| 3498 | |
| 3499 | |
| 3500 | |
| 3501 | |
| 3502 | |
| 3503 | |
| 3504 | |
| 3505 | |
| 3506 | |
| 3507 | |
| 3508 | endmodule |
| 3509 | |
| 3510 | |
| 3511 | |
| 3512 | |
| 3513 | |
| 3514 | |
| 3515 | |
| 3516 | |
| 3517 | |
| 3518 | |
| 3519 | |
| 3520 | |
| 3521 | |
| 3522 | // any PARAMS parms go into naming of macro |
| 3523 | |
| 3524 | module dec_del_ctl_msff_ctl_macro__width_4 ( |
| 3525 | din, |
| 3526 | l1clk, |
| 3527 | scan_in, |
| 3528 | siclk, |
| 3529 | soclk, |
| 3530 | dout, |
| 3531 | scan_out); |
| 3532 | wire [3:0] fdin; |
| 3533 | wire [2:0] so; |
| 3534 | |
| 3535 | input [3:0] din; |
| 3536 | input l1clk; |
| 3537 | input scan_in; |
| 3538 | |
| 3539 | |
| 3540 | input siclk; |
| 3541 | input soclk; |
| 3542 | |
| 3543 | output [3:0] dout; |
| 3544 | output scan_out; |
| 3545 | assign fdin[3:0] = din[3:0]; |
| 3546 | |
| 3547 | |
| 3548 | |
| 3549 | |
| 3550 | |
| 3551 | |
| 3552 | dff #(4) d0_0 ( |
| 3553 | .l1clk(l1clk), |
| 3554 | .siclk(siclk), |
| 3555 | .soclk(soclk), |
| 3556 | .d(fdin[3:0]), |
| 3557 | .si({scan_in,so[2:0]}), |
| 3558 | .so({so[2:0],scan_out}), |
| 3559 | .q(dout[3:0]) |
| 3560 | ); |
| 3561 | |
| 3562 | |
| 3563 | |
| 3564 | |
| 3565 | |
| 3566 | |
| 3567 | |
| 3568 | |
| 3569 | |
| 3570 | |
| 3571 | |
| 3572 | |
| 3573 | endmodule |
| 3574 | |
| 3575 | |
| 3576 | |
| 3577 | |
| 3578 | |
| 3579 | |
| 3580 | |
| 3581 | |
| 3582 | |
| 3583 | |
| 3584 | |
| 3585 | |
| 3586 | |
| 3587 | // any PARAMS parms go into naming of macro |
| 3588 | |
| 3589 | module dec_del_ctl_msff_ctl_macro__width_16 ( |
| 3590 | din, |
| 3591 | l1clk, |
| 3592 | scan_in, |
| 3593 | siclk, |
| 3594 | soclk, |
| 3595 | dout, |
| 3596 | scan_out); |
| 3597 | wire [15:0] fdin; |
| 3598 | wire [14:0] so; |
| 3599 | |
| 3600 | input [15:0] din; |
| 3601 | input l1clk; |
| 3602 | input scan_in; |
| 3603 | |
| 3604 | |
| 3605 | input siclk; |
| 3606 | input soclk; |
| 3607 | |
| 3608 | output [15:0] dout; |
| 3609 | output scan_out; |
| 3610 | assign fdin[15:0] = din[15:0]; |
| 3611 | |
| 3612 | |
| 3613 | |
| 3614 | |
| 3615 | |
| 3616 | |
| 3617 | dff #(16) d0_0 ( |
| 3618 | .l1clk(l1clk), |
| 3619 | .siclk(siclk), |
| 3620 | .soclk(soclk), |
| 3621 | .d(fdin[15:0]), |
| 3622 | .si({scan_in,so[14:0]}), |
| 3623 | .so({so[14:0],scan_out}), |
| 3624 | .q(dout[15:0]) |
| 3625 | ); |
| 3626 | |
| 3627 | |
| 3628 | |
| 3629 | |
| 3630 | |
| 3631 | |
| 3632 | |
| 3633 | |
| 3634 | |
| 3635 | |
| 3636 | |
| 3637 | |
| 3638 | endmodule |
| 3639 | |
| 3640 | |
| 3641 | |
| 3642 | |
| 3643 | |
| 3644 | |
| 3645 | |
| 3646 | |
| 3647 | |
| 3648 | |
| 3649 | |
| 3650 | |
| 3651 | |
| 3652 | // any PARAMS parms go into naming of macro |
| 3653 | |
| 3654 | module dec_del_ctl_msff_ctl_macro__width_2 ( |
| 3655 | din, |
| 3656 | l1clk, |
| 3657 | scan_in, |
| 3658 | siclk, |
| 3659 | soclk, |
| 3660 | dout, |
| 3661 | scan_out); |
| 3662 | wire [1:0] fdin; |
| 3663 | wire [0:0] so; |
| 3664 | |
| 3665 | input [1:0] din; |
| 3666 | input l1clk; |
| 3667 | input scan_in; |
| 3668 | |
| 3669 | |
| 3670 | input siclk; |
| 3671 | input soclk; |
| 3672 | |
| 3673 | output [1:0] dout; |
| 3674 | output scan_out; |
| 3675 | assign fdin[1:0] = din[1:0]; |
| 3676 | |
| 3677 | |
| 3678 | |
| 3679 | |
| 3680 | |
| 3681 | |
| 3682 | dff #(2) d0_0 ( |
| 3683 | .l1clk(l1clk), |
| 3684 | .siclk(siclk), |
| 3685 | .soclk(soclk), |
| 3686 | .d(fdin[1:0]), |
| 3687 | .si({scan_in,so[0:0]}), |
| 3688 | .so({so[0:0],scan_out}), |
| 3689 | .q(dout[1:0]) |
| 3690 | ); |
| 3691 | |
| 3692 | |
| 3693 | |
| 3694 | |
| 3695 | |
| 3696 | |
| 3697 | |
| 3698 | |
| 3699 | |
| 3700 | |
| 3701 | |
| 3702 | |
| 3703 | endmodule |
| 3704 | |
| 3705 | |
| 3706 | |
| 3707 | |
| 3708 | |
| 3709 | |
| 3710 | |
| 3711 | |
| 3712 | |
| 3713 | |
| 3714 | |
| 3715 | |
| 3716 | |
| 3717 | // any PARAMS parms go into naming of macro |
| 3718 | |
| 3719 | module dec_del_ctl_msff_ctl_macro__width_8 ( |
| 3720 | din, |
| 3721 | l1clk, |
| 3722 | scan_in, |
| 3723 | siclk, |
| 3724 | soclk, |
| 3725 | dout, |
| 3726 | scan_out); |
| 3727 | wire [7:0] fdin; |
| 3728 | wire [6:0] so; |
| 3729 | |
| 3730 | input [7:0] din; |
| 3731 | input l1clk; |
| 3732 | input scan_in; |
| 3733 | |
| 3734 | |
| 3735 | input siclk; |
| 3736 | input soclk; |
| 3737 | |
| 3738 | output [7:0] dout; |
| 3739 | output scan_out; |
| 3740 | assign fdin[7:0] = din[7:0]; |
| 3741 | |
| 3742 | |
| 3743 | |
| 3744 | |
| 3745 | |
| 3746 | |
| 3747 | dff #(8) d0_0 ( |
| 3748 | .l1clk(l1clk), |
| 3749 | .siclk(siclk), |
| 3750 | .soclk(soclk), |
| 3751 | .d(fdin[7:0]), |
| 3752 | .si({scan_in,so[6:0]}), |
| 3753 | .so({so[6:0],scan_out}), |
| 3754 | .q(dout[7:0]) |
| 3755 | ); |
| 3756 | |
| 3757 | |
| 3758 | |
| 3759 | |
| 3760 | |
| 3761 | |
| 3762 | |
| 3763 | |
| 3764 | |
| 3765 | |
| 3766 | |
| 3767 | |
| 3768 | endmodule |
| 3769 | |
| 3770 | |
| 3771 | |
| 3772 | |
| 3773 | |
| 3774 | |
| 3775 | |
| 3776 | |
| 3777 | |
| 3778 | |
| 3779 | |
| 3780 | |
| 3781 | |
| 3782 | // any PARAMS parms go into naming of macro |
| 3783 | |
| 3784 | module dec_del_ctl_msff_ctl_macro__width_1 ( |
| 3785 | din, |
| 3786 | l1clk, |
| 3787 | scan_in, |
| 3788 | siclk, |
| 3789 | soclk, |
| 3790 | dout, |
| 3791 | scan_out); |
| 3792 | wire [0:0] fdin; |
| 3793 | |
| 3794 | input [0:0] din; |
| 3795 | input l1clk; |
| 3796 | input scan_in; |
| 3797 | |
| 3798 | |
| 3799 | input siclk; |
| 3800 | input soclk; |
| 3801 | |
| 3802 | output [0:0] dout; |
| 3803 | output scan_out; |
| 3804 | assign fdin[0:0] = din[0:0]; |
| 3805 | |
| 3806 | |
| 3807 | |
| 3808 | |
| 3809 | |
| 3810 | |
| 3811 | dff #(1) d0_0 ( |
| 3812 | .l1clk(l1clk), |
| 3813 | .siclk(siclk), |
| 3814 | .soclk(soclk), |
| 3815 | .d(fdin[0:0]), |
| 3816 | .si(scan_in), |
| 3817 | .so(scan_out), |
| 3818 | .q(dout[0:0]) |
| 3819 | ); |
| 3820 | |
| 3821 | |
| 3822 | |
| 3823 | |
| 3824 | |
| 3825 | |
| 3826 | |
| 3827 | |
| 3828 | |
| 3829 | |
| 3830 | |
| 3831 | |
| 3832 | endmodule |
| 3833 | |
| 3834 | |
| 3835 | |
| 3836 | |
| 3837 | |
| 3838 | |
| 3839 | |
| 3840 | |
| 3841 | |
| 3842 | |
| 3843 | |
| 3844 | |
| 3845 | |
| 3846 | // any PARAMS parms go into naming of macro |
| 3847 | |
| 3848 | module dec_del_ctl_msff_ctl_macro__width_3 ( |
| 3849 | din, |
| 3850 | l1clk, |
| 3851 | scan_in, |
| 3852 | siclk, |
| 3853 | soclk, |
| 3854 | dout, |
| 3855 | scan_out); |
| 3856 | wire [2:0] fdin; |
| 3857 | wire [1:0] so; |
| 3858 | |
| 3859 | input [2:0] din; |
| 3860 | input l1clk; |
| 3861 | input scan_in; |
| 3862 | |
| 3863 | |
| 3864 | input siclk; |
| 3865 | input soclk; |
| 3866 | |
| 3867 | output [2:0] dout; |
| 3868 | output scan_out; |
| 3869 | assign fdin[2:0] = din[2:0]; |
| 3870 | |
| 3871 | |
| 3872 | |
| 3873 | |
| 3874 | |
| 3875 | |
| 3876 | dff #(3) d0_0 ( |
| 3877 | .l1clk(l1clk), |
| 3878 | .siclk(siclk), |
| 3879 | .soclk(soclk), |
| 3880 | .d(fdin[2:0]), |
| 3881 | .si({scan_in,so[1:0]}), |
| 3882 | .so({so[1:0],scan_out}), |
| 3883 | .q(dout[2:0]) |
| 3884 | ); |
| 3885 | |
| 3886 | |
| 3887 | |
| 3888 | |
| 3889 | |
| 3890 | |
| 3891 | |
| 3892 | |
| 3893 | |
| 3894 | |
| 3895 | |
| 3896 | |
| 3897 | endmodule |
| 3898 | |
| 3899 | |
| 3900 | |
| 3901 | |
| 3902 | |
| 3903 | |
| 3904 | |
| 3905 | |
| 3906 | |
| 3907 | |
| 3908 | |
| 3909 | |
| 3910 | |
| 3911 | // any PARAMS parms go into naming of macro |
| 3912 | |
| 3913 | module dec_del_ctl_msff_ctl_macro__width_5 ( |
| 3914 | din, |
| 3915 | l1clk, |
| 3916 | scan_in, |
| 3917 | siclk, |
| 3918 | soclk, |
| 3919 | dout, |
| 3920 | scan_out); |
| 3921 | wire [4:0] fdin; |
| 3922 | wire [3:0] so; |
| 3923 | |
| 3924 | input [4:0] din; |
| 3925 | input l1clk; |
| 3926 | input scan_in; |
| 3927 | |
| 3928 | |
| 3929 | input siclk; |
| 3930 | input soclk; |
| 3931 | |
| 3932 | output [4:0] dout; |
| 3933 | output scan_out; |
| 3934 | assign fdin[4:0] = din[4:0]; |
| 3935 | |
| 3936 | |
| 3937 | |
| 3938 | |
| 3939 | |
| 3940 | |
| 3941 | dff #(5) d0_0 ( |
| 3942 | .l1clk(l1clk), |
| 3943 | .siclk(siclk), |
| 3944 | .soclk(soclk), |
| 3945 | .d(fdin[4:0]), |
| 3946 | .si({scan_in,so[3:0]}), |
| 3947 | .so({so[3:0],scan_out}), |
| 3948 | .q(dout[4:0]) |
| 3949 | ); |
| 3950 | |
| 3951 | |
| 3952 | |
| 3953 | |
| 3954 | |
| 3955 | |
| 3956 | |
| 3957 | |
| 3958 | |
| 3959 | |
| 3960 | |
| 3961 | |
| 3962 | endmodule |
| 3963 | |
| 3964 | |
| 3965 | |
| 3966 | |
| 3967 | |
| 3968 | |
| 3969 | |
| 3970 | |
| 3971 | |
| 3972 | |
| 3973 | |
| 3974 | |
| 3975 | |
| 3976 | // any PARAMS parms go into naming of macro |
| 3977 | |
| 3978 | module dec_del_ctl_msff_ctl_macro__width_6 ( |
| 3979 | din, |
| 3980 | l1clk, |
| 3981 | scan_in, |
| 3982 | siclk, |
| 3983 | soclk, |
| 3984 | dout, |
| 3985 | scan_out); |
| 3986 | wire [5:0] fdin; |
| 3987 | wire [4:0] so; |
| 3988 | |
| 3989 | input [5:0] din; |
| 3990 | input l1clk; |
| 3991 | input scan_in; |
| 3992 | |
| 3993 | |
| 3994 | input siclk; |
| 3995 | input soclk; |
| 3996 | |
| 3997 | output [5:0] dout; |
| 3998 | output scan_out; |
| 3999 | assign fdin[5:0] = din[5:0]; |
| 4000 | |
| 4001 | |
| 4002 | |
| 4003 | |
| 4004 | |
| 4005 | |
| 4006 | dff #(6) d0_0 ( |
| 4007 | .l1clk(l1clk), |
| 4008 | .siclk(siclk), |
| 4009 | .soclk(soclk), |
| 4010 | .d(fdin[5:0]), |
| 4011 | .si({scan_in,so[4:0]}), |
| 4012 | .so({so[4:0],scan_out}), |
| 4013 | .q(dout[5:0]) |
| 4014 | ); |
| 4015 | |
| 4016 | |
| 4017 | |
| 4018 | |
| 4019 | |
| 4020 | |
| 4021 | |
| 4022 | |
| 4023 | |
| 4024 | |
| 4025 | |
| 4026 | |
| 4027 | endmodule |
| 4028 | |
| 4029 | |
| 4030 | |
| 4031 | |
| 4032 | |
| 4033 | |
| 4034 | |
| 4035 | |
| 4036 | |
| 4037 | |
| 4038 | |
| 4039 | |
| 4040 | |
| 4041 | // any PARAMS parms go into naming of macro |
| 4042 | |
| 4043 | module dec_del_ctl_msff_ctl_macro__width_14 ( |
| 4044 | din, |
| 4045 | l1clk, |
| 4046 | scan_in, |
| 4047 | siclk, |
| 4048 | soclk, |
| 4049 | dout, |
| 4050 | scan_out); |
| 4051 | wire [13:0] fdin; |
| 4052 | wire [12:0] so; |
| 4053 | |
| 4054 | input [13:0] din; |
| 4055 | input l1clk; |
| 4056 | input scan_in; |
| 4057 | |
| 4058 | |
| 4059 | input siclk; |
| 4060 | input soclk; |
| 4061 | |
| 4062 | output [13:0] dout; |
| 4063 | output scan_out; |
| 4064 | assign fdin[13:0] = din[13:0]; |
| 4065 | |
| 4066 | |
| 4067 | |
| 4068 | |
| 4069 | |
| 4070 | |
| 4071 | dff #(14) d0_0 ( |
| 4072 | .l1clk(l1clk), |
| 4073 | .siclk(siclk), |
| 4074 | .soclk(soclk), |
| 4075 | .d(fdin[13:0]), |
| 4076 | .si({scan_in,so[12:0]}), |
| 4077 | .so({so[12:0],scan_out}), |
| 4078 | .q(dout[13:0]) |
| 4079 | ); |
| 4080 | |
| 4081 | |
| 4082 | |
| 4083 | |
| 4084 | |
| 4085 | |
| 4086 | |
| 4087 | |
| 4088 | |
| 4089 | |
| 4090 | |
| 4091 | |
| 4092 | endmodule |
| 4093 | |
| 4094 | |
| 4095 | |
| 4096 | |
| 4097 | |
| 4098 | |
| 4099 | |
| 4100 | |
| 4101 | |
| 4102 | |
| 4103 | |
| 4104 | |
| 4105 | |
| 4106 | // any PARAMS parms go into naming of macro |
| 4107 | |
| 4108 | module dec_del_ctl_msff_ctl_macro__width_12 ( |
| 4109 | din, |
| 4110 | l1clk, |
| 4111 | scan_in, |
| 4112 | siclk, |
| 4113 | soclk, |
| 4114 | dout, |
| 4115 | scan_out); |
| 4116 | wire [11:0] fdin; |
| 4117 | wire [10:0] so; |
| 4118 | |
| 4119 | input [11:0] din; |
| 4120 | input l1clk; |
| 4121 | input scan_in; |
| 4122 | |
| 4123 | |
| 4124 | input siclk; |
| 4125 | input soclk; |
| 4126 | |
| 4127 | output [11:0] dout; |
| 4128 | output scan_out; |
| 4129 | assign fdin[11:0] = din[11:0]; |
| 4130 | |
| 4131 | |
| 4132 | |
| 4133 | |
| 4134 | |
| 4135 | |
| 4136 | dff #(12) d0_0 ( |
| 4137 | .l1clk(l1clk), |
| 4138 | .siclk(siclk), |
| 4139 | .soclk(soclk), |
| 4140 | .d(fdin[11:0]), |
| 4141 | .si({scan_in,so[10:0]}), |
| 4142 | .so({so[10:0],scan_out}), |
| 4143 | .q(dout[11:0]) |
| 4144 | ); |
| 4145 | |
| 4146 | |
| 4147 | |
| 4148 | |
| 4149 | |
| 4150 | |
| 4151 | |
| 4152 | |
| 4153 | |
| 4154 | |
| 4155 | |
| 4156 | |
| 4157 | endmodule |
| 4158 | |
| 4159 | |
| 4160 | |
| 4161 | |
| 4162 | |
| 4163 | |
| 4164 | |
| 4165 | |