| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: n2_clk_gl_cust.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | `define FLOP_STAGES_ON |
| 36 | |
| 37 | module n2_clk_gl_cust( |
| 38 | |
| 39 | cmp_gclk_c1_ccu , cmp_gclk_c2_ccx_left , cmp_gclk_c2_ccx_right , |
| 40 | cmp_gclk_c3_db0 , cmp_gclk_c1_db1 , cmp_gclk_c3_dmu , |
| 41 | cmp_gclk_c1_efu , cmp_gclk_c3_l2b0 , cmp_gclk_c3_l2b1 , |
| 42 | cmp_gclk_c3_l2b2 , cmp_gclk_c3_l2b3 , cmp_gclk_c1_l2b4 , |
| 43 | cmp_gclk_c1_l2b5 , cmp_gclk_c1_l2b6 , cmp_gclk_c1_l2b7 , |
| 44 | cmp_gclk_c3_l2d0 , cmp_gclk_c3_l2d1 , cmp_gclk_c3_l2d2 , |
| 45 | cmp_gclk_c3_l2d3 , cmp_gclk_c1_l2d4 , cmp_gclk_c1_l2d5 , |
| 46 | cmp_gclk_c1_l2d6 , cmp_gclk_c1_l2d7 , cmp_gclk_c3_l2t0 , |
| 47 | cmp_gclk_c3_l2t2 , cmp_gclk_c1_l2t4 , cmp_gclk_c1_l2t6 , |
| 48 | cmp_gclk_c2_l2t1 , cmp_gclk_c2_l2t3 , cmp_gclk_c2_l2t5 , |
| 49 | cmp_gclk_c2_l2t7 , cmp_gclk_c4_mcu0 , cmp_gclk_c4_mcu1 , |
| 50 | cmp_gclk_c0_mcu2 , cmp_gclk_c0_mcu3 , dr_gclk_c4_mcu0 , |
| 51 | dr_gclk_c4_mcu1 , dr_gclk_c0_mcu2 , dr_gclk_c0_mcu3 , |
| 52 | cmp_gclk_c1_mio , cmp_gclk_c3_mio , cmp_gclk_c2_mio_left , |
| 53 | cmp_gclk_c2_mio_right , cmp_gclk_c3_ncu , cmp_gclk_c3_peu , |
| 54 | // cmp_gclk_c1_rst , |
| 55 | cmp_gclk_c3_sii , cmp_gclk_c1_sio , |
| 56 | cmp_gclk_c3_spc0 , cmp_gclk_c3_spc2 , cmp_gclk_c1_spc4 , |
| 57 | cmp_gclk_c1_spc6 , cmp_gclk_c2_spc1 , cmp_gclk_c2_spc3 , |
| 58 | cmp_gclk_c2_spc5 , cmp_gclk_c2_spc7 , cmp_gclk_c1_tcu , |
| 59 | cmp_gclk_c1_mac , cmp_gclk_c0_rdp , cmp_gclk_c0_rtx , |
| 60 | cmp_gclk_c0_tds , cmp_gclk_c3_rng, |
| 61 | |
| 62 | dr_gclk_c4_fsr0_0 , dr_gclk_c4_fsr0_1 , dr_gclk_c4_fsr0_2 , |
| 63 | dr_gclk_c4_fsr1_0 , dr_gclk_c4_fsr1_1 , dr_gclk_c4_fsr1_2 , |
| 64 | dr_gclk_c4_fsr2_0 , dr_gclk_c4_fsr2_1 , dr_gclk_c4_fsr2_2 , |
| 65 | dr_gclk_c4_fsr3_0 , dr_gclk_c4_fsr3_1 , dr_gclk_c4_fsr3_2 , |
| 66 | dr_gclk_c0_fsr4_0 , dr_gclk_c0_fsr4_1 , dr_gclk_c0_fsr4_2 , |
| 67 | dr_gclk_c0_fsr5_0 , dr_gclk_c0_fsr5_1 , dr_gclk_c0_fsr5_2 , |
| 68 | dr_gclk_c0_fsr6_0 , dr_gclk_c0_fsr6_1 , dr_gclk_c0_fsr6_2 , |
| 69 | dr_gclk_c2_fsr7_0 , dr_gclk_c2_fsr7_1 , dr_gclk_c2_fsr7_2 , |
| 70 | pll_dr_clk , pll_cmp_clk, |
| 71 | |
| 72 | stg2_mcu0_clk_stop_in_c2t, |
| 73 | stg2_mcu1_clk_stop_in_c2t, |
| 74 | stg3_mcu0_clk_stop_out_c2t, |
| 75 | stg3_mcu1_clk_stop_out_c2t, |
| 76 | stg2_mcu0_io_clk_stop_in_c2t, |
| 77 | // stg2_mcu0_dr_clk_stop_in_c2t, |
| 78 | // stg2_mcu1_dr_clk_stop_in_c2t, |
| 79 | stg2_mcu1_io_clk_stop_in_c2t, |
| 80 | // stg3_mcu0_dr_clk_stop_out_c2t, |
| 81 | stg3_mcu0_io_clk_stop_out_c2t, |
| 82 | // stg3_mcu1_dr_clk_stop_out_c2t, |
| 83 | stg3_mcu1_io_clk_stop_out_c2t, |
| 84 | |
| 85 | stg2_io2x_sync_en_in_c2t, stg3_io2x_sync_en_out_c2t, |
| 86 | ccu_cmp_io_sync_en, ccu_dr_sync_en, ccu_io2x_out, |
| 87 | ccu_io2x_sync_en, ccu_io_cmp_sync_en, ccu_io_out, |
| 88 | ccu_vco_aligned, gclk_aligned, gl_ccu_clk_stop, |
| 89 | gl_ccu_io_clk_stop, gl_ccx_clk_stop, gl_cmp_io_sync_en_c1b, |
| 90 | gl_cmp_io_sync_en_c1m, gl_cmp_io_sync_en_c1t, gl_cmp_io_sync_en_c2b, |
| 91 | gl_cmp_io_sync_en_c2t, gl_cmp_io_sync_en_c3b, gl_cmp_io_sync_en_c3t, |
| 92 | gl_cmp_io_sync_en_c3t0, gl_db0_clk_stop, gl_db1_clk_stop, |
| 93 | gl_dmu_io_clk_stop, gl_dmu_peu_por_c3b, gl_dmu_peu_wmr_c3b, |
| 94 | gl_dr_sync_en_c1m, gl_dr_sync_en_c3t, gl_efu_clk_stop, |
| 95 | gl_efu_io_clk_stop, gl_io2x_out_c1b, gl_io2x_sync_en_c1m, |
| 96 | gl_io2x_sync_en_c3t, gl_io2x_sync_en_c3t0, gl_io2x_sync_en_c2t, |
| 97 | gl_io_cmp_sync_en_c1b, gl_io_cmp_sync_en_c1m, gl_io_cmp_sync_en_c1t, |
| 98 | gl_io_cmp_sync_en_c2b, gl_io_cmp_sync_en_c2t, gl_io_cmp_sync_en_c3b, |
| 99 | gl_io_cmp_sync_en_c3t, gl_io_cmp_sync_en_c3t0, gl_io_out_c1b, |
| 100 | gl_io_out_c1m, gl_io_out_c3b, gl_io_out_c3b0, gl_io_out_c3t, |
| 101 | gl_l2_por_c1t, gl_l2_por_c2b, gl_l2_por_c2t, gl_l2_por_c3b0, |
| 102 | gl_l2_por_c3t, gl_l2_por_c3t0, gl_l2_wmr_c1b, gl_l2_wmr_c1t, |
| 103 | gl_l2_wmr_c2b, gl_l2_wmr_c2t, gl_l2_wmr_c3b, gl_l2_wmr_c3t, |
| 104 | gl_l2_wmr_c3t0, gl_l2b0_clk_stop, gl_l2b1_clk_stop, |
| 105 | gl_l2b2_clk_stop, gl_l2b3_clk_stop, gl_l2b4_clk_stop, |
| 106 | gl_l2b5_clk_stop, gl_l2b6_clk_stop, gl_l2b7_clk_stop, |
| 107 | gl_l2d0_clk_stop, gl_l2d1_clk_stop, gl_l2d2_clk_stop, |
| 108 | gl_l2d3_clk_stop, gl_l2d4_clk_stop, gl_l2d5_clk_stop, |
| 109 | gl_l2d6_clk_stop, gl_l2d7_clk_stop, gl_l2t0_clk_stop, |
| 110 | gl_l2t1_clk_stop, gl_l2t2_clk_stop, gl_l2t3_clk_stop, |
| 111 | gl_l2t4_clk_stop, gl_l2t5_clk_stop, gl_l2t6_clk_stop, |
| 112 | gl_l2t7_clk_stop, gl_mac_io_clk_stop, gl_mcu0_clk_stop, |
| 113 | gl_mcu0_dr_clk_stop, gl_mcu0_io_clk_stop, gl_mcu1_clk_stop, |
| 114 | gl_mcu1_dr_clk_stop, gl_mcu1_io_clk_stop, gl_mcu2_clk_stop, |
| 115 | gl_mcu2_dr_clk_stop, gl_mcu2_io_clk_stop, gl_mcu3_clk_stop, |
| 116 | gl_mcu3_dr_clk_stop, gl_mcu3_io_clk_stop, gl_mio_clk_stop_c1t, |
| 117 | gl_mio_clk_stop_c2t, gl_mio_clk_stop_c3t, // gl_mio_io2x_sync_en_c1b, |
| 118 | gl_mio_io2x_sync_en_c1t, gl_ncu_clk_stop, gl_ncu_io_clk_stop, |
| 119 | gl_peu_io_clk_stop, gl_rdp_io_clk_stop, gl_rst_clk_stop, |
| 120 | gl_rst_io_clk_stop, gl_rst_l2_por_c1m, gl_rst_l2_wmr_c1m, |
| 121 | gl_rst_mac_c1b, gl_rst_niu_wmr_c1b, gl_rtx_io_clk_stop, |
| 122 | gl_sii_clk_stop, gl_sii_io_clk_stop, gl_sio_clk_stop, |
| 123 | gl_sio_io_clk_stop, gl_spc0_clk_stop, gl_spc1_clk_stop, |
| 124 | gl_spc2_clk_stop, gl_spc3_clk_stop, gl_spc4_clk_stop, |
| 125 | gl_spc5_clk_stop, gl_spc6_clk_stop, gl_spc7_clk_stop, |
| 126 | gl_tds_io_clk_stop, rst_dmu_peu_por_, rst_dmu_peu_wmr_, |
| 127 | rst_l2_por_, rst_l2_wmr_, rst_niu_mac_, |
| 128 | gl_l2_por_c1b, // for int6.1 |
| 129 | rst_niu_wmr_, stg1_ccx_clk_stop_in_c1b, stg1_ccx_clk_stop_out_c1b, |
| 130 | stg1_cmp_io_sync_en_in_c1b, stg1_cmp_io_sync_en_in_c1t, stg1_cmp_io_sync_en_out_c1b, |
| 131 | stg1_cmp_io_sync_en_out_c1t, stg1_db0_clk_stop_in_c1b, stg1_db0_clk_stop_out_c1b, |
| 132 | stg1_dmu_io_clk_stop_in_c1b, stg1_dmu_io_clk_stop_out_c1b, stg1_dmu_peu_por_in_c1b, |
| 133 | stg1_dmu_peu_por_out_c1b, stg1_dmu_peu_wmr_in_c1b, stg1_dmu_peu_wmr_out_c1b, |
| 134 | stg1_dr_sync_en_in_c1t, stg1_dr_sync_en_out_c1t, stg1_io2x_out_in_c1b, |
| 135 | stg1_io2x_out_out_c1b, stg1_io2x_sync_en_out_c1b, stg1_io2x_sync_en_out_c1t, |
| 136 | stg1_io_cmp_sync_en_in_c1b, stg1_io_cmp_sync_en_in_c1t, stg1_io_cmp_sync_en_out_c1b, |
| 137 | stg1_io_cmp_sync_en_out_c1t, stg1_io_out_in_c1b, stg1_io_out_in_c1t, |
| 138 | stg1_io_out_out_c1b, stg1_io_out_out_c1t, stg1_l2_por_in_c1b, |
| 139 | stg1_l2_por_in_c1t, stg1_l2_wmr_in_c1b, stg1_l2_wmr_in_c1t, |
| 140 | stg1_l2b0_clk_stop_in_c1t, stg1_l2b0_clk_stop_out_c1t, stg1_l2b1_clk_stop_in_c1t, |
| 141 | stg1_l2b1_clk_stop_out_c1t, stg1_l2b2_clk_stop_in_c1b, stg1_l2b2_clk_stop_out_c1b, |
| 142 | stg1_l2b3_clk_stop_in_c1b, stg1_l2b3_clk_stop_out_c1b, stg1_l2b4_clk_stop_in_c1t, |
| 143 | stg1_l2b4_clk_stop_out_c1t, stg1_l2b5_clk_stop_in_c1t, stg1_l2b5_clk_stop_out_c1t, |
| 144 | stg1_l2d0_clk_stop_in_c1t, stg1_l2d0_clk_stop_out_c1t, stg1_l2d1_clk_stop_in_c1t, |
| 145 | stg1_l2d1_clk_stop_out_c1t, stg1_l2d2_clk_stop_in_c1b, stg1_l2d2_clk_stop_out_c1b, |
| 146 | stg1_l2d3_clk_stop_in_c1b, stg1_l2d3_clk_stop_out_c1b, stg1_l2d4_clk_stop_in_c1t, |
| 147 | stg1_l2d4_clk_stop_out_c1t, stg1_l2d5_clk_stop_in_c1t, stg1_l2d5_clk_stop_out_c1t, |
| 148 | stg1_l2d7_clk_stop_in_c1b, stg1_l2d7_clk_stop_out_c1b, stg1_l2t0_clk_stop_in_c1t, |
| 149 | stg1_l2t0_clk_stop_out_c1t, stg1_l2t1_clk_stop_in_c1t, stg1_l2t1_clk_stop_out_c1t, |
| 150 | stg1_l2t2_clk_stop_in_c1b, stg1_l2t2_clk_stop_out_c1b, stg1_l2t3_clk_stop_in_c1b, |
| 151 | stg1_l2t3_clk_stop_out_c1b, stg1_l2t5_clk_stop_in_c1t, stg1_l2t5_clk_stop_out_c1t, |
| 152 | stg1_l2t7_clk_stop_in_c1b, stg1_l2t7_clk_stop_out_c1b, stg1_mac_io_clk_stop_in_c1b, |
| 153 | stg1_mac_io_clk_stop_out_c1b, stg1_mcu0_clk_stop_in_c1t, stg1_mcu0_clk_stop_out_c1t, |
| 154 | // stg1_mcu0_dr_clk_stop_in_c1t, |
| 155 | stg1_mcu0_dr_clk_stop_out_c1t, |
| 156 | stg1_mcu0_io_clk_stop_in_c1t, |
| 157 | stg1_mcu0_io_clk_stop_out_c1t, stg1_mcu1_clk_stop_in_c1t, stg1_mcu1_clk_stop_out_c1t, |
| 158 | // stg1_mcu1_dr_clk_stop_in_c1t, |
| 159 | stg1_mcu1_dr_clk_stop_out_c1t, |
| 160 | stg1_mcu1_io_clk_stop_in_c1t, |
| 161 | stg1_mcu1_io_clk_stop_out_c1t, stg1_mio_clk_stop_in_c1t, stg1_mio_clk_stop_out_c1t, |
| 162 | stg1_mio_io2x_sync_en_in_c1t, stg1_ncu_clk_stop_in_c1b, stg1_ncu_clk_stop_out_c1b, |
| 163 | stg1_ncu_io_clk_stop_in_c1b, stg1_ncu_io_clk_stop_out_c1b, stg1_peu_io_clk_stop_in_c1b, |
| 164 | stg1_peu_io_clk_stop_out_c1b, stg1_rdp_io_clk_stop_in_c1b, stg1_rdp_io_clk_stop_out_c1b, |
| 165 | stg1_rst_l2_por_out_c1b, stg1_rst_l2_por_out_c1t, stg1_rst_l2_wmr_out_c1b, |
| 166 | stg1_rst_l2_wmr_out_c1t, stg1_rst_mac_in_c1b, stg1_rst_niu_mac_out_c1b, |
| 167 | stg1_rst_niu_wmr_in_c1b, stg1_rst_niu_wmr_out_c1b, stg1_rtx_io_clk_stop_in_c1b, |
| 168 | stg1_rtx_io_clk_stop_out_c1b, stg1_sii_clk_stop_in_c1b, stg1_sii_clk_stop_out_c1b, |
| 169 | stg1_sii_io_clk_stop_in_c1b, stg1_sii_io_clk_stop_out_c1b, stg1_spc0_clk_stop_in_c1t, |
| 170 | stg1_spc0_clk_stop_out_c1t, stg1_spc1_clk_stop_in_c1t, stg1_spc1_clk_stop_out_c1t, |
| 171 | stg1_spc2_clk_stop_in_c1b, stg1_spc2_clk_stop_out_c1b, stg1_spc3_clk_stop_in_c1b, |
| 172 | stg1_spc3_clk_stop_out_c1b, stg1_spc4_clk_stop_in_c1t, stg1_spc4_clk_stop_out_c1t, |
| 173 | stg1_spc5_clk_stop_in_c1t, stg1_spc5_clk_stop_out_c1t, stg1_spc6_clk_stop_in_c1b, |
| 174 | stg1_spc6_clk_stop_out_c1b, stg1_spc7_clk_stop_in_c1b, stg1_spc7_clk_stop_out_c1b, |
| 175 | stg1_tds_io_clk_stop_in_c1b, stg1_tds_io_clk_stop_out_c1b, stg2_ccx_clk_stop_in_c2b, |
| 176 | stg2_ccx_clk_stop_out_c1b, stg2_cmp_io_sync_en_in_c2b, stg2_cmp_io_sync_en_in_c2t, |
| 177 | stg2_cmp_io_sync_en_out_c1b, stg2_cmp_io_sync_en_out_c1t, stg2_db0_clk_stop_in_c2b, |
| 178 | stg2_db0_clk_stop_out_c1b, stg2_dmu_io_clk_stop_in_c2b, stg2_dmu_io_clk_stop_out_c1b, |
| 179 | stg2_dmu_peu_por_in_c2b, stg2_dmu_peu_por_out_c1b, stg2_dmu_peu_wmr_in_c2b, |
| 180 | stg2_dmu_peu_wmr_out_c1b, stg2_dr_sync_en_in_c2t, stg2_dr_sync_en_out_c1t, |
| 181 | stg2_io_cmp_sync_en_in_c2b, stg2_io_cmp_sync_en_in_c2t, stg2_io_cmp_sync_en_out_c1b, |
| 182 | stg2_io_cmp_sync_en_out_c1t, stg2_io_out_in_c2t, stg2_io_out_out_c1t, |
| 183 | stg2_l2_por_in_c2b, stg2_l2_por_in_c2t, stg2_l2_por_out_c1b, |
| 184 | stg2_l2_por_out_c1t, stg2_l2_wmr_in_c2b, stg2_l2_wmr_in_c2t, |
| 185 | stg2_l2_wmr_out_c1b, stg2_l2_wmr_out_c1t, stg2_l2b0_clk_stop_in_c2t, |
| 186 | stg2_l2b0_clk_stop_out_c1t, stg2_l2b1_clk_stop_in_c2t, stg2_l2b1_clk_stop_out_c1t, |
| 187 | stg2_l2b2_clk_stop_in_c2b, stg2_l2b2_clk_stop_out_c1b, stg2_l2b3_clk_stop_in_c2b, |
| 188 | stg2_l2b3_clk_stop_out_c1b, stg2_l2d0_clk_stop_in_c2t, stg2_l2d0_clk_stop_out_c1t, |
| 189 | stg2_l2d1_clk_stop_in_c2t, stg2_l2d1_clk_stop_out_c1t, stg2_l2d2_clk_stop_in_c2b, |
| 190 | stg2_l2d2_clk_stop_out_c1b, stg2_l2d3_clk_stop_in_c2b, stg2_l2d3_clk_stop_out_c1b, |
| 191 | stg2_l2t0_clk_stop_in_c2t, stg2_l2t0_clk_stop_out_c1t, stg2_l2t1_clk_stop_in_c2t, |
| 192 | stg2_l2t1_clk_stop_out_c1t, stg2_l2t2_clk_stop_in_c2b, stg2_l2t2_clk_stop_out_c1b, |
| 193 | stg2_l2t3_clk_stop_in_c2bz, stg2_l2t3_clk_stop_out_c1b, stg2_l2t5_clk_stop_in_c2t, |
| 194 | stg2_l2t5_clk_stop_out_c1t, stg2_l2t7_clk_stop_in_c2b, stg2_l2t7_clk_stop_out_c1b, |
| 195 | stg2_mcu0_clk_stop_out_c1t, // stg2_mcu0_dr_clk_stop_out_c1t, |
| 196 | stg2_mcu0_io_clk_stop_out_c1t, |
| 197 | stg2_mcu1_clk_stop_out_c1t, // stg2_mcu1_dr_clk_stop_out_c1t, |
| 198 | stg2_mcu1_io_clk_stop_out_c1t, |
| 199 | stg2_io_out_out_c1b, |
| 200 | stg2_mio_clk_stop_in_c2t, stg2_mio_clk_stop_out_c1t, stg2_mio_io2x_sync_en_in_c2t, |
| 201 | stg2_mio_io2x_sync_en_out_c1t, stg2_ncu_clk_stop_in_c2b, stg2_ncu_clk_stop_out_c1b, |
| 202 | stg2_ncu_io_clk_stop_in_c2b, stg2_ncu_io_clk_stop_out_c1b, stg2_peu_io_clk_stop_in_c2b, |
| 203 | stg2_peu_io_clk_stop_out_c1b, stg2_sii_clk_stop_in_c2b, stg2_sii_clk_stop_out_c1b, |
| 204 | stg2_sii_io_clk_stop_in_c2b, stg2_sii_io_clk_stop_out_c1b, stg2_spc0_clk_stop_in_c2t, |
| 205 | stg2_spc0_clk_stop_out_c1t, stg2_spc1_clk_stop_in_c2t, stg2_spc1_clk_stop_out_c1t, |
| 206 | stg2_spc2_clk_stop_in_c2b, stg2_spc2_clk_stop_out_c1b, stg2_spc3_clk_stop_in_c2b, |
| 207 | stg2_spc3_clk_stop_out_c1b, stg2_spc5_clk_stop_in_c2t, stg2_spc5_clk_stop_out_c1t, |
| 208 | stg2_spc7_clk_stop_in_c2b, stg2_spc7_clk_stop_out_c1b, stg3_ccx_clk_stop_in_c2b, |
| 209 | stg3_ccx_clk_stop_out_c2b, stg3_cmp_io_sync_en_in_c2b, stg3_cmp_io_sync_en_in_c2t, |
| 210 | stg3_cmp_io_sync_en_in_c3b, stg3_cmp_io_sync_en_in_c3t, stg3_cmp_io_sync_en_out_c2b, |
| 211 | stg3_cmp_io_sync_en_out_c2t, stg3_db0_clk_stop_in_c3b, stg3_db0_clk_stop_out_c2b, |
| 212 | stg3_dmu_io_clk_stop_in_c3b, stg3_dmu_io_clk_stop_out_c2b, stg3_dmu_peu_por_in_c3b, |
| 213 | stg3_dmu_peu_por_out_c2b, stg3_dmu_peu_wmr_in_c3b, stg3_dmu_peu_wmr_out_c2b, |
| 214 | stg3_dr_sync_en_in_c3t, stg3_dr_sync_en_out_c2t, stg3_io2x_sync_en_in_c2t, |
| 215 | stg3_io_cmp_sync_en_in_c2b, stg3_io_cmp_sync_en_in_c2t, stg3_io_cmp_sync_en_in_c3b, |
| 216 | stg3_io_cmp_sync_en_in_c3t, stg3_io_cmp_sync_en_out_c2b, stg3_io_cmp_sync_en_out_c2t, |
| 217 | stg3_io_out_in_c3b, stg3_io_out_in_c3t, stg3_io_out_out_c2t, |
| 218 | stg3_l2_por_in_c2b, stg3_l2_por_in_c2t, stg3_l2_por_in_c3b, |
| 219 | stg3_l2_por_in_c3t, stg3_l2_por_out_c2b, stg3_l2_por_out_c2t, |
| 220 | stg3_l2_wmr_in_c2b, stg3_l2_wmr_in_c2t, stg3_l2_wmr_in_c3b, |
| 221 | stg3_l2_wmr_in_c3t, stg3_l2_wmr_out_c2b, stg3_l2_wmr_out_c2t, |
| 222 | stg3_l2b0_clk_stop_in_c3t, stg3_l2b0_clk_stop_out_c2t, stg3_l2b1_clk_stop_in_c3t, |
| 223 | stg3_l2b1_clk_stop_out_c2t, stg3_l2b2_clk_stop_in_c3b, stg3_l2b2_clk_stop_out_c2b, |
| 224 | stg3_l2b3_clk_stop_in_c3b, stg3_l2b3_clk_stop_out_c2b, stg3_l2d0_clk_stop_in_c3t, |
| 225 | stg3_l2d0_clk_stop_out_c2t, stg3_l2d1_clk_stop_in_c3t, stg3_l2d1_clk_stop_out_c2t, |
| 226 | stg3_l2d2_clk_stop_in_c3b, stg3_l2d2_clk_stop_out_c2b, stg3_l2d3_clk_stop_in_c3b, |
| 227 | stg3_l2d3_clk_stop_out_c2b, stg3_l2t0_clk_stop_in_c3t, stg3_l2t0_clk_stop_out_c2t, |
| 228 | stg3_l2t1_clk_stop_in_c2t, stg3_l2t1_clk_stop_out_c2t, stg3_l2t2_clk_stop_in_c3b, |
| 229 | stg3_l2t2_clk_stop_out_c2b, stg3_l2t3_clk_stop_in_c2b, stg3_l2t3_clk_stop_out_c2b, |
| 230 | stg3_l2t5_clk_stop_in_c2t, stg3_l2t5_clk_stop_out_c2t, stg3_l2t7_clk_stop_in_c2b, |
| 231 | stg3_l2t7_clk_stop_out_c2b, stg3_mcu0_clk_stop_in_c3t, //stg3_mcu0_dr_clk_stop_in_c3t, |
| 232 | stg3_mcu0_io_clk_stop_in_c3t, stg3_mcu1_clk_stop_in_c3t, //stg3_mcu1_dr_clk_stop_in_c3t, |
| 233 | stg3_mcu1_io_clk_stop_in_c3t, stg3_mio_clk_stop_in_c2t, stg3_mio_clk_stop_in_c3t, |
| 234 | stg3_mio_clk_stop_out_c2t, stg3_mio_io2x_sync_en_in_c3t, stg3_mio_io2x_sync_en_out_c2t, |
| 235 | stg3_ncu_clk_stop_in_c3b, stg3_ncu_clk_stop_out_c2b, stg3_ncu_io_clk_stop_in_c3b, |
| 236 | stg3_ncu_io_clk_stop_out_c2b, stg3_peu_io_clk_stop_in_c3b, |
| 237 | stg3_peu_io_clk_stop_out_c2b, stg3_sii_clk_stop_in_c3b, stg3_sii_clk_stop_out_c2b, |
| 238 | stg3_sii_io_clk_stop_in_c3b, stg3_sii_io_clk_stop_out_c2b, stg3_spc0_clk_stop_in_c3t, |
| 239 | stg3_spc0_clk_stop_out_c2t, stg3_spc1_clk_stop_in_c2t, |
| 240 | stg3_spc1_clk_stop_out_c2t, |
| 241 | stg3_spc2_clk_stop_in_c3b, stg3_spc2_clk_stop_out_c2b, stg3_spc3_clk_stop_in_c2b, |
| 242 | stg3_spc3_clk_stop_out_c2b, stg3_spc5_clk_stop_in_c2t, stg3_spc5_clk_stop_out_c2t, |
| 243 | stg3_spc7_clk_stop_in_c2b, stg3_spc7_clk_stop_out_c2b, stg4_cmp_io_sync_en_in_c3b, |
| 244 | stg4_cmp_io_sync_en_in_c3t, stg4_cmp_io_sync_en_out_c3b, stg4_cmp_io_sync_en_out_c3t, |
| 245 | stg4_db0_clk_stop_c3b, stg4_db0_clk_stop_out_c3b, stg4_dmu_io_clk_stop_in_c3b, |
| 246 | stg4_dmu_io_clk_stop_out_c3b, stg4_dmu_peu_por_in_c3b, stg4_dmu_peu_por_out_c3b, |
| 247 | stg4_dmu_peu_wmr_in_c3b, stg4_dmu_peu_wmr_out_c3b, stg4_dr_sync_en_in_c3t, |
| 248 | stg4_dr_sync_en_out_c3t, stg4_io2x_sync_en_c3t, stg4_io2x_sync_en_in_c3t, |
| 249 | stg4_io_cmp_sync_en_in_c3b, stg4_io_cmp_sync_en_in_c3t, |
| 250 | stg4_io_cmp_sync_en_out_c3b, stg4_io_cmp_sync_en_out_c3t, stg4_io_out_in_c3b, |
| 251 | stg4_io_out_in_c3t, stg4_io_out_out_c3b, stg4_io_out_out_c3t, |
| 252 | stg4_l2_por_in_c3b, stg4_l2_por_in_c3t, stg4_l2_por_out_c3b, |
| 253 | stg4_l2_por_out_c3t, stg4_l2_wmr_in_c3b, stg4_l2_wmr_in_c3t, |
| 254 | stg4_l2_wmr_out_c3b, stg4_l2_wmr_out_c3t, stg4_l2b0_clk_stop_in_c3t, |
| 255 | stg4_l2b0_clk_stop_out_c3t, stg4_l2b1_clk_stop_in_c3t, stg4_l2b1_clk_stop_out_c3t, |
| 256 | stg4_l2b2_clk_stop_in_c3b, stg4_l2b2_clk_stop_out_c3b, stg4_l2b3_clk_stop_in_c3b, |
| 257 | stg4_l2b3_clk_stop_out_c3b, stg4_l2d0_clk_stop_in_c3t, stg4_l2d0_clk_stop_out_c3t, |
| 258 | stg4_l2d1_clk_stop_in_c3t, stg4_l2d1_clk_stop_out_c3t, stg4_l2d2_clk_stop_in_c3b, |
| 259 | stg4_l2d2_clk_stop_out_c3b, stg4_l2d3_clk_stop_in_c3b, stg4_l2d3_clk_stop_out_c3b, |
| 260 | stg4_l2t0_clk_stop_in_c3t, stg4_l2t0_clk_stop_out_c3t, stg4_l2t2_clk_stop_in_c3b, |
| 261 | stg4_l2t2_clk_stop_out_c3b, stg4_mcu0_clk_stop_in_c3t, stg4_mcu0_clk_stop_out_c3t, |
| 262 | // stg4_mcu0_dr_clk_stop_in_c3t, stg4_mcu0_dr_clk_stop_out_c3t, |
| 263 | stg4_mcu0_io_clk_stop_in_c3t, |
| 264 | stg4_mcu0_io_clk_stop_out_c3t, stg4_mcu1_clk_stop_in_c3t, stg4_mcu1_clk_stop_out_c3t, |
| 265 | // stg4_mcu1_dr_clk_stop_in_c3t, stg4_mcu1_dr_clk_stop_out_c3t, |
| 266 | stg1_mcu0_dr_clk_stop_in_c2b, stg1_mcu1_dr_clk_stop_in_c2b, |
| 267 | stg2_mcu0_dr_clk_stop_in_c4t, stg2_mcu1_dr_clk_stop_in_c4t, |
| 268 | stg2_mcu0_dr_clk_stop_out_c2b, stg2_mcu1_dr_clk_stop_out_c2b, |
| 269 | stg4_mcu1_io_clk_stop_in_c3t, |
| 270 | stg4_mcu1_io_clk_stop_out_c3t, stg4_mio_clk_stop_in_c3t, |
| 271 | stg4_mio_clk_stop_out_c3t, stg4_mio_io2x_sync_en_out_c3t, stg4_ncu_clk_stop_in_c3b, |
| 272 | stg4_ncu_clk_stop_out_c3b, stg4_ncu_io_clk_stop_c3b, stg4_ncu_io_clk_stop_out_c3b, |
| 273 | stg4_peu_io_clk_stop_in_c3b, stg4_peu_io_clk_stop_out_c3b, stg4_sii_clk_stop_in_c3b, |
| 274 | stg4_sii_clk_stop_out_c3b, stg4_sii_io_clk_stop_in_c3b, stg4_sii_io_clk_stop_out_c3b, |
| 275 | stg4_spc0_clk_stop_in_c3t, stg4_spc0_clk_stop_out_c3t, // stg4_spc1_clk_stop_out_c2b, |
| 276 | stg4_spc2_clk_stop_in_c3b, stg4_spc2_clk_stop_out_c3b, // stg4_spc5_clk_stop_out_c2b, |
| 277 | // for int6.1 (set 3) |
| 278 | stg1_cmp_io_sync_en_in_c1bg, stg1_cmp_io_sync_en_in_c1tg, stg1_io_cmp_sync_en_in_c1bg, |
| 279 | stg1_io_cmp_sync_en_in_c1tg, stg1_io_out_in_c1bg, stg1_l2_por_in_c1bg, |
| 280 | stg1_l2_por_in_c1tg, stg1_l2_wmr_in_c1bg, stg1_l2_wmr_in_c1tg, |
| 281 | stg1_mio_clk_stop_in_c1tg, stg1_mio_io2x_sync_en_in_c1tg, stg4_cmp_io_sync_en_in_c3t0, |
| 282 | stg4_io_cmp_sync_en_in_c3t0, stg4_io_out_in_c3b0, stg4_l2_por_in_c3t0, |
| 283 | stg4_l2_wmr_in_c3t0, |
| 284 | |
| 285 | tcu_ccu_clk_stop, stg2_io_out_in_c2b, stg3_io_out_out_c2b, |
| 286 | tcu_ccu_io_clk_stop, tcu_ccx_clk_stop, tcu_db0_clk_stop, |
| 287 | tcu_db1_clk_stop, tcu_dmu_io_clk_stop, tcu_efu_clk_stop, |
| 288 | tcu_efu_io_clk_stop, tcu_l2b0_clk_stop, tcu_l2b1_clk_stop, |
| 289 | tcu_l2b2_clk_stop, tcu_l2b3_clk_stop, tcu_l2b4_clk_stop, |
| 290 | tcu_l2b5_clk_stop, tcu_l2b6_clk_stop, tcu_l2b7_clk_stop, |
| 291 | tcu_l2d0_clk_stop, tcu_l2d1_clk_stop, tcu_l2d2_clk_stop, |
| 292 | tcu_l2d3_clk_stop, tcu_l2d4_clk_stop, tcu_l2d5_clk_stop, |
| 293 | tcu_l2d6_clk_stop, tcu_l2d7_clk_stop, tcu_l2t0_clk_stop, |
| 294 | tcu_l2t1_clk_stop, tcu_l2t2_clk_stop, tcu_l2t3_clk_stop, |
| 295 | tcu_l2t4_clk_stop, tcu_l2t5_clk_stop, tcu_l2t6_clk_stop, |
| 296 | tcu_l2t7_clk_stop, tcu_mac_io_clk_stop, tcu_mcu0_clk_stop, |
| 297 | tcu_mcu0_dr_clk_stop, tcu_mcu0_io_clk_stop, tcu_mcu1_clk_stop, |
| 298 | tcu_mcu1_dr_clk_stop, tcu_mcu1_io_clk_stop, tcu_mcu2_clk_stop, |
| 299 | tcu_mcu2_dr_clk_stop, tcu_mcu2_io_clk_stop, tcu_mcu3_clk_stop, |
| 300 | tcu_mcu3_dr_clk_stop, tcu_mcu3_io_clk_stop, tcu_mio_clk_stop, |
| 301 | tcu_ncu_clk_stop, tcu_ncu_io_clk_stop, tcu_peu_io_clk_stop, |
| 302 | tcu_rdp_io_clk_stop, tcu_rst_clk_stop, tcu_rst_io_clk_stop, |
| 303 | tcu_rtx_io_clk_stop, tcu_sii_clk_stop, tcu_sii_io_clk_stop, |
| 304 | tcu_sio_clk_stop, tcu_sio_io_clk_stop, tcu_spc0_clk_stop, |
| 305 | tcu_spc1_clk_stop, tcu_spc2_clk_stop, tcu_spc3_clk_stop, |
| 306 | tcu_spc4_clk_stop, tcu_spc5_clk_stop, tcu_spc6_clk_stop, |
| 307 | tcu_spc7_clk_stop, tcu_tds_io_clk_stop |
| 308 | |
| 309 | |
| 310 | |
| 311 | ); |
| 312 | |
| 313 | |
| 314 | |
| 315 | |
| 316 | |
| 317 | // only clock nets |
| 318 | output cmp_gclk_c1_ccu ; |
| 319 | output cmp_gclk_c2_ccx_left ; |
| 320 | output cmp_gclk_c2_ccx_right ; |
| 321 | output cmp_gclk_c3_db0 ; |
| 322 | output cmp_gclk_c1_db1 ; |
| 323 | output cmp_gclk_c3_dmu ; |
| 324 | output cmp_gclk_c1_efu ; |
| 325 | output cmp_gclk_c3_l2b0 ; |
| 326 | output cmp_gclk_c3_l2b1 ; |
| 327 | output cmp_gclk_c3_l2b2 ; |
| 328 | output cmp_gclk_c3_l2b3 ; |
| 329 | output cmp_gclk_c1_l2b4 ; |
| 330 | output cmp_gclk_c1_l2b5 ; |
| 331 | output cmp_gclk_c1_l2b6 ; |
| 332 | output cmp_gclk_c1_l2b7 ; |
| 333 | output cmp_gclk_c3_l2d0 ; |
| 334 | output cmp_gclk_c3_l2d1 ; |
| 335 | output cmp_gclk_c3_l2d2 ; |
| 336 | output cmp_gclk_c3_l2d3 ; |
| 337 | output cmp_gclk_c1_l2d4 ; |
| 338 | output cmp_gclk_c1_l2d5 ; |
| 339 | output cmp_gclk_c1_l2d6 ; |
| 340 | output cmp_gclk_c1_l2d7 ; |
| 341 | output cmp_gclk_c3_l2t0 ; |
| 342 | output cmp_gclk_c3_l2t2 ; |
| 343 | output cmp_gclk_c1_l2t4 ; |
| 344 | output cmp_gclk_c1_l2t6 ; |
| 345 | output cmp_gclk_c2_l2t1 ; |
| 346 | output cmp_gclk_c2_l2t3 ; |
| 347 | output cmp_gclk_c2_l2t5 ; |
| 348 | output cmp_gclk_c2_l2t7 ; |
| 349 | output cmp_gclk_c4_mcu0 ; |
| 350 | output cmp_gclk_c4_mcu1 ; |
| 351 | output cmp_gclk_c0_mcu2 ; |
| 352 | output cmp_gclk_c0_mcu3 ; |
| 353 | output dr_gclk_c4_mcu0 ; |
| 354 | output dr_gclk_c4_mcu1 ; |
| 355 | output dr_gclk_c0_mcu2 ; |
| 356 | output dr_gclk_c0_mcu3 ; |
| 357 | output cmp_gclk_c1_mio ; |
| 358 | output cmp_gclk_c3_mio ; |
| 359 | output cmp_gclk_c2_mio_left ; |
| 360 | output cmp_gclk_c2_mio_right ; |
| 361 | output cmp_gclk_c3_ncu ; |
| 362 | output cmp_gclk_c3_peu ; |
| 363 | // output cmp_gclk_c1_rst ; |
| 364 | output cmp_gclk_c3_sii ; |
| 365 | output cmp_gclk_c1_sio ; |
| 366 | output cmp_gclk_c3_spc0 ; |
| 367 | output cmp_gclk_c3_spc2 ; |
| 368 | output cmp_gclk_c1_spc4 ; |
| 369 | output cmp_gclk_c1_spc6 ; |
| 370 | output cmp_gclk_c2_spc1 ; |
| 371 | output cmp_gclk_c2_spc3 ; |
| 372 | output cmp_gclk_c2_spc5 ; |
| 373 | output cmp_gclk_c2_spc7 ; |
| 374 | output cmp_gclk_c1_tcu ; |
| 375 | output cmp_gclk_c1_mac ; |
| 376 | output cmp_gclk_c0_rdp ; |
| 377 | output cmp_gclk_c0_rtx ; |
| 378 | output cmp_gclk_c0_tds ; |
| 379 | |
| 380 | output cmp_gclk_c3_rng; |
| 381 | |
| 382 | output dr_gclk_c4_fsr0_0; |
| 383 | output dr_gclk_c4_fsr0_1; |
| 384 | output dr_gclk_c4_fsr0_2; |
| 385 | output dr_gclk_c4_fsr1_0; |
| 386 | output dr_gclk_c4_fsr1_1; |
| 387 | output dr_gclk_c4_fsr1_2; |
| 388 | output dr_gclk_c4_fsr2_0; |
| 389 | output dr_gclk_c4_fsr2_1; |
| 390 | output dr_gclk_c4_fsr2_2; |
| 391 | output dr_gclk_c4_fsr3_0; |
| 392 | output dr_gclk_c4_fsr3_1; |
| 393 | output dr_gclk_c4_fsr3_2; |
| 394 | output dr_gclk_c0_fsr4_0; |
| 395 | output dr_gclk_c0_fsr4_1; |
| 396 | output dr_gclk_c0_fsr4_2; |
| 397 | output dr_gclk_c0_fsr5_0; |
| 398 | output dr_gclk_c0_fsr5_1; |
| 399 | output dr_gclk_c0_fsr5_2; |
| 400 | output dr_gclk_c0_fsr6_0; |
| 401 | output dr_gclk_c0_fsr6_1; |
| 402 | output dr_gclk_c0_fsr6_2; |
| 403 | output dr_gclk_c2_fsr7_0; |
| 404 | output dr_gclk_c2_fsr7_1; |
| 405 | output dr_gclk_c2_fsr7_2; |
| 406 | |
| 407 | input pll_dr_clk ; |
| 408 | input pll_cmp_clk ; |
| 409 | |
| 410 | input stg2_io2x_sync_en_in_c2t; |
| 411 | output stg3_io2x_sync_en_out_c2t; |
| 412 | |
| 413 | input stg2_io_out_in_c2b; |
| 414 | |
| 415 | input ccu_cmp_io_sync_en ; |
| 416 | input ccu_dr_sync_en ; |
| 417 | input ccu_io2x_out ; |
| 418 | input ccu_io2x_sync_en ; |
| 419 | input ccu_io_cmp_sync_en ; |
| 420 | input ccu_io_out ; |
| 421 | input ccu_vco_aligned ; |
| 422 | |
| 423 | input rst_dmu_peu_por_ ; |
| 424 | input rst_dmu_peu_wmr_ ; |
| 425 | input rst_l2_por_ ; |
| 426 | input rst_l2_wmr_ ; |
| 427 | input rst_niu_mac_ ; |
| 428 | input rst_niu_wmr_ ; |
| 429 | |
| 430 | input stg1_ccx_clk_stop_in_c1b ; |
| 431 | input stg1_cmp_io_sync_en_in_c1b ; |
| 432 | input stg1_cmp_io_sync_en_in_c1t; |
| 433 | input stg1_db0_clk_stop_in_c1b ; |
| 434 | input stg1_dmu_io_clk_stop_in_c1b ; |
| 435 | input stg1_dmu_peu_por_in_c1b ; |
| 436 | input stg1_dmu_peu_wmr_in_c1b ; |
| 437 | input stg1_dr_sync_en_in_c1t ; |
| 438 | input stg1_io2x_out_in_c1b ; |
| 439 | input stg1_io_cmp_sync_en_in_c1b ; |
| 440 | input stg1_io_cmp_sync_en_in_c1t ; |
| 441 | input stg1_io_out_in_c1b ; |
| 442 | input stg1_io_out_in_c1t ; |
| 443 | input stg1_l2_por_in_c1b ; |
| 444 | input stg1_l2_por_in_c1t ; |
| 445 | input stg1_l2_wmr_in_c1b ; |
| 446 | input stg1_l2_wmr_in_c1t ; |
| 447 | input stg1_l2b0_clk_stop_in_c1t ; |
| 448 | input stg1_l2b1_clk_stop_in_c1t ; |
| 449 | input stg1_l2b2_clk_stop_in_c1b ; |
| 450 | input stg1_l2b3_clk_stop_in_c1b ; |
| 451 | input stg1_l2b4_clk_stop_in_c1t ; |
| 452 | input stg1_l2b5_clk_stop_in_c1t ; |
| 453 | input stg1_l2d0_clk_stop_in_c1t ; |
| 454 | input stg1_l2d1_clk_stop_in_c1t ; |
| 455 | input stg1_l2d2_clk_stop_in_c1b ; |
| 456 | input stg1_l2d3_clk_stop_in_c1b ; |
| 457 | input stg1_l2d4_clk_stop_in_c1t ; |
| 458 | input stg1_l2d5_clk_stop_in_c1t ; |
| 459 | input stg1_l2d7_clk_stop_in_c1b ; |
| 460 | input stg1_l2t0_clk_stop_in_c1t ; |
| 461 | input stg1_l2t1_clk_stop_in_c1t ; |
| 462 | input stg1_l2t2_clk_stop_in_c1b ; |
| 463 | input stg1_l2t3_clk_stop_in_c1b ; |
| 464 | input stg1_l2t5_clk_stop_in_c1t ; |
| 465 | input stg1_l2t7_clk_stop_in_c1b ; |
| 466 | input stg1_mac_io_clk_stop_in_c1b ; |
| 467 | input stg1_mcu0_clk_stop_in_c1t ; |
| 468 | // input stg1_mcu0_dr_clk_stop_in_c1t ; |
| 469 | input stg1_mcu0_io_clk_stop_in_c1t ; |
| 470 | input stg1_mcu1_clk_stop_in_c1t ; |
| 471 | // input stg1_mcu1_dr_clk_stop_in_c1t ; |
| 472 | input stg1_mcu1_io_clk_stop_in_c1t ; |
| 473 | input stg1_mio_clk_stop_in_c1t ; |
| 474 | input stg1_mio_io2x_sync_en_in_c1t ; |
| 475 | input stg1_ncu_clk_stop_in_c1b ; |
| 476 | input stg1_ncu_io_clk_stop_in_c1b ; |
| 477 | input stg1_peu_io_clk_stop_in_c1b ; |
| 478 | input stg1_rdp_io_clk_stop_in_c1b ; |
| 479 | input stg1_rst_mac_in_c1b ; |
| 480 | input stg1_rst_niu_wmr_in_c1b ; |
| 481 | input stg1_rtx_io_clk_stop_in_c1b ; |
| 482 | input stg1_sii_clk_stop_in_c1b ; |
| 483 | input stg1_sii_io_clk_stop_in_c1b ; |
| 484 | input stg1_spc0_clk_stop_in_c1t ; |
| 485 | input stg1_spc1_clk_stop_in_c1t ; |
| 486 | input stg1_spc2_clk_stop_in_c1b ; |
| 487 | input stg1_spc3_clk_stop_in_c1b ; |
| 488 | input stg1_spc4_clk_stop_in_c1t; |
| 489 | input stg1_spc5_clk_stop_in_c1t ; |
| 490 | input stg1_spc6_clk_stop_in_c1b; |
| 491 | input stg1_spc7_clk_stop_in_c1b ; |
| 492 | input stg1_tds_io_clk_stop_in_c1b ; |
| 493 | input stg2_ccx_clk_stop_in_c2b ; |
| 494 | input stg2_cmp_io_sync_en_in_c2b ; |
| 495 | input stg2_cmp_io_sync_en_in_c2t ; |
| 496 | input stg2_db0_clk_stop_in_c2b ; |
| 497 | input stg2_dmu_io_clk_stop_in_c2b ; |
| 498 | input stg2_dmu_peu_por_in_c2b ; |
| 499 | input stg2_dmu_peu_wmr_in_c2b ; |
| 500 | input stg2_dr_sync_en_in_c2t ; |
| 501 | input stg2_io_cmp_sync_en_in_c2b ; |
| 502 | input stg2_io_cmp_sync_en_in_c2t ; |
| 503 | input stg2_io_out_in_c2t ; |
| 504 | input stg2_l2_por_in_c2b ; |
| 505 | input stg2_l2_por_in_c2t ; |
| 506 | input stg2_l2_wmr_in_c2b ; |
| 507 | input stg2_l2_wmr_in_c2t ; |
| 508 | input stg2_l2b0_clk_stop_in_c2t ; |
| 509 | input stg2_l2b1_clk_stop_in_c2t ; |
| 510 | input stg2_l2b2_clk_stop_in_c2b ; |
| 511 | input stg2_l2b3_clk_stop_in_c2b ; |
| 512 | input stg2_l2d0_clk_stop_in_c2t ; |
| 513 | input stg2_l2d1_clk_stop_in_c2t ; |
| 514 | input stg2_l2d2_clk_stop_in_c2b ; |
| 515 | input stg2_l2d3_clk_stop_in_c2b ; |
| 516 | input stg2_l2t0_clk_stop_in_c2t ; |
| 517 | input stg2_l2t1_clk_stop_in_c2t ; |
| 518 | input stg2_l2t2_clk_stop_in_c2b ; |
| 519 | input stg2_l2t3_clk_stop_in_c2bz ; |
| 520 | input stg2_l2t5_clk_stop_in_c2t ; |
| 521 | input stg2_l2t7_clk_stop_in_c2b ; |
| 522 | input stg2_mio_clk_stop_in_c2t ; |
| 523 | input stg2_mio_io2x_sync_en_in_c2t ; |
| 524 | input stg2_ncu_clk_stop_in_c2b ; |
| 525 | input stg2_ncu_io_clk_stop_in_c2b ; |
| 526 | input stg2_peu_io_clk_stop_in_c2b ; |
| 527 | input stg2_sii_clk_stop_in_c2b ; |
| 528 | input stg2_sii_io_clk_stop_in_c2b ; |
| 529 | input stg2_spc0_clk_stop_in_c2t ; |
| 530 | input stg2_spc1_clk_stop_in_c2t ; |
| 531 | input stg2_spc2_clk_stop_in_c2b ; |
| 532 | input stg2_spc3_clk_stop_in_c2b ; |
| 533 | input stg2_spc5_clk_stop_in_c2t ; |
| 534 | input stg2_spc7_clk_stop_in_c2b ; |
| 535 | input stg3_ccx_clk_stop_in_c2b ; |
| 536 | input stg3_cmp_io_sync_en_in_c2b ; |
| 537 | input stg3_cmp_io_sync_en_in_c2t ; |
| 538 | input stg3_cmp_io_sync_en_in_c3b ; |
| 539 | input stg3_cmp_io_sync_en_in_c3t ; |
| 540 | input stg3_db0_clk_stop_in_c3b ; |
| 541 | input stg3_dmu_io_clk_stop_in_c3b ; |
| 542 | input stg3_dmu_peu_por_in_c3b ; |
| 543 | input stg3_dmu_peu_wmr_in_c3b ; |
| 544 | input stg3_dr_sync_en_in_c3t ; |
| 545 | input stg3_io2x_sync_en_in_c2t ; |
| 546 | input stg3_io_cmp_sync_en_in_c2b ; |
| 547 | input stg3_io_cmp_sync_en_in_c2t ; |
| 548 | input stg3_io_cmp_sync_en_in_c3b ; |
| 549 | input stg3_io_cmp_sync_en_in_c3t ; |
| 550 | input stg3_io_out_in_c3b ; |
| 551 | input stg3_io_out_in_c3t ; |
| 552 | input stg3_l2_por_in_c2b ; |
| 553 | input stg3_l2_por_in_c2t ; |
| 554 | input stg3_l2_por_in_c3b ; |
| 555 | input stg3_l2_por_in_c3t ; |
| 556 | input stg3_l2_wmr_in_c2b ; |
| 557 | input stg3_l2_wmr_in_c2t ; |
| 558 | input stg3_l2_wmr_in_c3b ; |
| 559 | input stg3_l2_wmr_in_c3t ; |
| 560 | input stg3_l2b0_clk_stop_in_c3t ; |
| 561 | input stg3_l2b1_clk_stop_in_c3t ; |
| 562 | input stg3_l2b2_clk_stop_in_c3b ; |
| 563 | input stg3_l2b3_clk_stop_in_c3b ; |
| 564 | input stg3_l2d0_clk_stop_in_c3t ; |
| 565 | input stg3_l2d1_clk_stop_in_c3t ; |
| 566 | input stg3_l2d2_clk_stop_in_c3b ; |
| 567 | input stg3_l2d3_clk_stop_in_c3b ; |
| 568 | input stg3_l2t0_clk_stop_in_c3t ; |
| 569 | input stg3_l2t1_clk_stop_in_c2t ; |
| 570 | input stg3_l2t3_clk_stop_in_c2b ; |
| 571 | input stg3_l2t5_clk_stop_in_c2t ; |
| 572 | input stg3_l2t7_clk_stop_in_c2b ; |
| 573 | input stg3_mcu0_clk_stop_in_c3t ; |
| 574 | //input stg3_mcu0_dr_clk_stop_in_c3t ; |
| 575 | input stg3_mcu0_io_clk_stop_in_c3t ; |
| 576 | input stg3_mcu1_clk_stop_in_c3t ; |
| 577 | //input stg3_mcu1_dr_clk_stop_in_c3t ; |
| 578 | input stg3_mcu1_io_clk_stop_in_c3t ; |
| 579 | input stg3_mio_clk_stop_in_c2t ; |
| 580 | input stg3_mio_clk_stop_in_c3t ; |
| 581 | input stg3_mio_io2x_sync_en_in_c3t ; |
| 582 | input stg3_ncu_clk_stop_in_c3b ; |
| 583 | input stg3_ncu_io_clk_stop_in_c3b ; |
| 584 | input stg3_peu_io_clk_stop_in_c3b ; |
| 585 | input stg3_sii_clk_stop_in_c3b ; |
| 586 | input stg3_sii_io_clk_stop_in_c3b ; |
| 587 | input stg3_spc0_clk_stop_in_c3t ; |
| 588 | input stg3_spc1_clk_stop_in_c2t ; |
| 589 | input stg3_spc2_clk_stop_in_c3b ; |
| 590 | input stg3_spc3_clk_stop_in_c2b ; |
| 591 | input stg3_spc5_clk_stop_in_c2t ; |
| 592 | input stg3_spc7_clk_stop_in_c2b ; |
| 593 | input stg4_cmp_io_sync_en_in_c3b ; |
| 594 | input stg4_cmp_io_sync_en_in_c3t ; |
| 595 | input stg4_db0_clk_stop_c3b ; |
| 596 | input stg4_dmu_io_clk_stop_in_c3b ; |
| 597 | input stg4_dmu_peu_por_in_c3b ; |
| 598 | input stg4_dmu_peu_wmr_in_c3b ; |
| 599 | input stg4_dr_sync_en_in_c3t ; |
| 600 | //output stg4_io2x_sync_en_c3t ;//lijuan |
| 601 | input stg4_io2x_sync_en_c3t ;//lijuan |
| 602 | input stg4_io2x_sync_en_in_c3t ; |
| 603 | input stg4_io_cmp_sync_en_in_c3b ; |
| 604 | input stg4_io_cmp_sync_en_in_c3t ; |
| 605 | input stg4_io_out_in_c3b ; |
| 606 | input stg4_io_out_in_c3t ; |
| 607 | input stg4_l2_por_in_c3b ; |
| 608 | input stg4_l2_por_in_c3t ; |
| 609 | input stg4_l2_wmr_in_c3b ; |
| 610 | input stg4_l2_wmr_in_c3t ; |
| 611 | input stg4_l2b0_clk_stop_in_c3t ; |
| 612 | input stg4_l2b1_clk_stop_in_c3t ; |
| 613 | input stg4_l2b2_clk_stop_in_c3b ; |
| 614 | input stg4_l2b3_clk_stop_in_c3b ; |
| 615 | input stg4_l2d0_clk_stop_in_c3t ; |
| 616 | input stg4_l2d1_clk_stop_in_c3t ; |
| 617 | input stg4_l2d2_clk_stop_in_c3b ; |
| 618 | input stg4_l2d3_clk_stop_in_c3b ; |
| 619 | input stg4_l2t0_clk_stop_in_c3t ; |
| 620 | input stg4_l2t2_clk_stop_in_c3b ; |
| 621 | input stg4_mcu0_clk_stop_in_c3t ; |
| 622 | // input stg4_mcu0_dr_clk_stop_in_c3t ; |
| 623 | input stg4_mcu0_io_clk_stop_in_c3t ; |
| 624 | input stg4_mcu1_clk_stop_in_c3t ; |
| 625 | // input stg4_mcu1_dr_clk_stop_in_c3t ; |
| 626 | input stg4_mcu1_io_clk_stop_in_c3t ; |
| 627 | input stg4_mio_clk_stop_in_c3t ; |
| 628 | input stg4_ncu_clk_stop_in_c3b ; |
| 629 | input stg4_ncu_io_clk_stop_c3b ; |
| 630 | input stg4_peu_io_clk_stop_in_c3b ; |
| 631 | input stg4_sii_clk_stop_in_c3b ; |
| 632 | input stg4_sii_io_clk_stop_in_c3b ; |
| 633 | input stg4_spc0_clk_stop_in_c3t ; |
| 634 | input stg4_spc2_clk_stop_in_c3b ; |
| 635 | input tcu_ccu_clk_stop ; |
| 636 | input tcu_ccu_io_clk_stop ; |
| 637 | input tcu_ccx_clk_stop ; |
| 638 | input tcu_db0_clk_stop ; |
| 639 | input tcu_db1_clk_stop ; |
| 640 | input tcu_dmu_io_clk_stop ; |
| 641 | input tcu_efu_clk_stop ; |
| 642 | input tcu_efu_io_clk_stop ; |
| 643 | input tcu_l2b0_clk_stop ; |
| 644 | input tcu_l2b1_clk_stop ; |
| 645 | input tcu_l2b2_clk_stop ; |
| 646 | input tcu_l2b3_clk_stop ; |
| 647 | input tcu_l2b4_clk_stop ; |
| 648 | input tcu_l2b5_clk_stop ; |
| 649 | input tcu_l2b6_clk_stop ; |
| 650 | input tcu_l2b7_clk_stop ; |
| 651 | input tcu_l2d0_clk_stop ; |
| 652 | input tcu_l2d1_clk_stop ; |
| 653 | input tcu_l2d2_clk_stop ; |
| 654 | input tcu_l2d3_clk_stop ; |
| 655 | input tcu_l2d4_clk_stop ; |
| 656 | input tcu_l2d5_clk_stop ; |
| 657 | input tcu_l2d7_clk_stop ; |
| 658 | input tcu_l2d6_clk_stop ; |
| 659 | input tcu_l2t0_clk_stop ; |
| 660 | input tcu_l2t1_clk_stop ; |
| 661 | input tcu_l2t2_clk_stop ; |
| 662 | input tcu_l2t3_clk_stop ; |
| 663 | input tcu_l2t4_clk_stop ; |
| 664 | input tcu_l2t5_clk_stop ; |
| 665 | input tcu_l2t6_clk_stop ; |
| 666 | input tcu_l2t7_clk_stop ; |
| 667 | input tcu_mac_io_clk_stop ; |
| 668 | input tcu_mcu0_clk_stop ; |
| 669 | input tcu_mcu0_dr_clk_stop ; |
| 670 | input tcu_mcu0_io_clk_stop ; |
| 671 | input tcu_mcu1_clk_stop ; |
| 672 | input tcu_mcu1_dr_clk_stop ; |
| 673 | input tcu_mcu1_io_clk_stop ; |
| 674 | input tcu_mcu2_clk_stop ; |
| 675 | input tcu_mcu2_dr_clk_stop ; |
| 676 | input tcu_mcu2_io_clk_stop ; |
| 677 | input tcu_mcu3_clk_stop ; |
| 678 | input tcu_mcu3_dr_clk_stop ; |
| 679 | input tcu_mcu3_io_clk_stop ; |
| 680 | input tcu_mio_clk_stop ; |
| 681 | input tcu_ncu_clk_stop ; |
| 682 | input tcu_ncu_io_clk_stop ; |
| 683 | input tcu_peu_io_clk_stop ; |
| 684 | input tcu_rdp_io_clk_stop ; |
| 685 | input tcu_rst_clk_stop ; |
| 686 | input tcu_rst_io_clk_stop ; |
| 687 | input tcu_rtx_io_clk_stop ; |
| 688 | input tcu_sii_clk_stop ; |
| 689 | input tcu_sii_io_clk_stop ; |
| 690 | input tcu_sio_clk_stop ; |
| 691 | input tcu_sio_io_clk_stop ; |
| 692 | input tcu_spc0_clk_stop ; |
| 693 | input tcu_spc1_clk_stop ; |
| 694 | input tcu_spc2_clk_stop ; |
| 695 | input tcu_spc3_clk_stop ; |
| 696 | input tcu_spc4_clk_stop ; |
| 697 | input tcu_spc5_clk_stop ; |
| 698 | input tcu_spc6_clk_stop ; |
| 699 | input tcu_spc7_clk_stop ; |
| 700 | input tcu_tds_io_clk_stop ; |
| 701 | input stg3_l2t2_clk_stop_in_c3b ; |
| 702 | |
| 703 | input stg2_mcu0_clk_stop_in_c2t; |
| 704 | input stg2_mcu1_clk_stop_in_c2t; |
| 705 | |
| 706 | input stg2_mcu0_io_clk_stop_in_c2t; |
| 707 | // input stg2_mcu0_dr_clk_stop_in_c2t; |
| 708 | // input stg2_mcu1_dr_clk_stop_in_c2t; |
| 709 | input stg2_mcu1_io_clk_stop_in_c2t; |
| 710 | |
| 711 | input stg1_mcu0_dr_clk_stop_in_c2b; |
| 712 | input stg1_mcu1_dr_clk_stop_in_c2b; |
| 713 | input stg2_mcu0_dr_clk_stop_in_c4t; |
| 714 | input stg2_mcu1_dr_clk_stop_in_c4t; |
| 715 | |
| 716 | // for int6.1 (set 3) |
| 717 | input stg1_cmp_io_sync_en_in_c1bg; |
| 718 | input stg1_cmp_io_sync_en_in_c1tg; |
| 719 | input stg1_io_cmp_sync_en_in_c1bg; |
| 720 | input stg1_io_cmp_sync_en_in_c1tg; |
| 721 | input stg1_io_out_in_c1bg; |
| 722 | input stg1_l2_por_in_c1bg; |
| 723 | input stg1_l2_por_in_c1tg; |
| 724 | input stg1_l2_wmr_in_c1bg; |
| 725 | input stg1_l2_wmr_in_c1tg; |
| 726 | input stg1_mio_clk_stop_in_c1tg; |
| 727 | input stg1_mio_io2x_sync_en_in_c1tg; |
| 728 | input stg4_cmp_io_sync_en_in_c3t0; |
| 729 | input stg4_io_cmp_sync_en_in_c3t0; |
| 730 | input stg4_io_out_in_c3b0; |
| 731 | input stg4_l2_por_in_c3t0; |
| 732 | input stg4_l2_wmr_in_c3t0; |
| 733 | |
| 734 | output stg3_io_out_out_c2b; |
| 735 | output stg2_mcu0_dr_clk_stop_out_c2b; |
| 736 | output stg2_mcu1_dr_clk_stop_out_c2b; |
| 737 | |
| 738 | //output stg3_mcu0_dr_clk_stop_out_c2t; |
| 739 | output stg3_mcu0_io_clk_stop_out_c2t; |
| 740 | //output stg3_mcu1_dr_clk_stop_out_c2t; |
| 741 | output stg3_mcu1_io_clk_stop_out_c2t; |
| 742 | |
| 743 | output stg3_mcu0_clk_stop_out_c2t; |
| 744 | output stg3_mcu1_clk_stop_out_c2t; |
| 745 | |
| 746 | output gl_ccu_clk_stop ; |
| 747 | output gl_ccu_io_clk_stop ; |
| 748 | output gl_ccx_clk_stop ; |
| 749 | output gl_cmp_io_sync_en_c1b ; |
| 750 | output gl_cmp_io_sync_en_c1m ; |
| 751 | output gl_cmp_io_sync_en_c1t ; |
| 752 | output gl_cmp_io_sync_en_c2b ; |
| 753 | output gl_cmp_io_sync_en_c2t ; |
| 754 | output gl_cmp_io_sync_en_c3b ; |
| 755 | output gl_cmp_io_sync_en_c3t ; |
| 756 | output gl_cmp_io_sync_en_c3t0 ; |
| 757 | output gl_db0_clk_stop ; |
| 758 | output gl_db1_clk_stop ; |
| 759 | output gl_dmu_io_clk_stop ; |
| 760 | output gl_dmu_peu_por_c3b ; |
| 761 | output gl_dmu_peu_wmr_c3b ; |
| 762 | output gl_dr_sync_en_c1m ; |
| 763 | output gl_dr_sync_en_c3t ; |
| 764 | output gl_efu_clk_stop ; |
| 765 | output gl_efu_io_clk_stop ; |
| 766 | output gl_io2x_out_c1b ; |
| 767 | output gl_io2x_sync_en_c1m ; |
| 768 | output gl_io2x_sync_en_c3t ; |
| 769 | output gl_io2x_sync_en_c3t0 ; |
| 770 | output gl_io2x_sync_en_c2t ; |
| 771 | output gl_io_cmp_sync_en_c1b ; |
| 772 | output gl_io_cmp_sync_en_c1m ; |
| 773 | output gl_io_cmp_sync_en_c1t ; |
| 774 | output gl_io_cmp_sync_en_c2b ; |
| 775 | output gl_io_cmp_sync_en_c2t ; |
| 776 | output gl_io_cmp_sync_en_c3b ; |
| 777 | output gl_io_cmp_sync_en_c3t ; |
| 778 | output gl_io_cmp_sync_en_c3t0 ; |
| 779 | output gl_io_out_c1b ; |
| 780 | output gl_io_out_c1m ; |
| 781 | output gl_io_out_c3b ; |
| 782 | output gl_io_out_c3b0 ; |
| 783 | output gl_io_out_c3t ; |
| 784 | output gl_l2_por_c1t ; |
| 785 | output gl_l2_por_c1b ; // for int6.1 |
| 786 | output gl_l2_por_c2b ; |
| 787 | output gl_l2_por_c2t ; |
| 788 | output gl_l2_por_c3b0 ; |
| 789 | output gl_l2_por_c3t ; |
| 790 | output gl_l2_por_c3t0 ; |
| 791 | output gl_l2_wmr_c1b ; |
| 792 | output gl_l2_wmr_c1t ; |
| 793 | output gl_l2_wmr_c2b ; |
| 794 | output gl_l2_wmr_c2t ; |
| 795 | output gl_l2_wmr_c3b ; |
| 796 | output gl_l2_wmr_c3t ; |
| 797 | output gl_l2_wmr_c3t0 ; |
| 798 | output gl_l2b0_clk_stop ; |
| 799 | output gl_l2b1_clk_stop ; |
| 800 | output gl_l2b2_clk_stop ; |
| 801 | output gl_l2b3_clk_stop ; |
| 802 | output gl_l2b4_clk_stop ; |
| 803 | output gl_l2b5_clk_stop ; |
| 804 | output gl_l2b6_clk_stop ; |
| 805 | output gl_l2b7_clk_stop ; |
| 806 | output gl_l2d0_clk_stop ; |
| 807 | output gl_l2d1_clk_stop ; |
| 808 | output gl_l2d2_clk_stop ; |
| 809 | output gl_l2d3_clk_stop ; |
| 810 | output gl_l2d4_clk_stop ; |
| 811 | output gl_l2d5_clk_stop ; |
| 812 | output gl_l2d7_clk_stop ; |
| 813 | output gl_l2d6_clk_stop ; |
| 814 | output gl_l2t0_clk_stop ; |
| 815 | output gl_l2t1_clk_stop ; |
| 816 | output gl_l2t2_clk_stop ; |
| 817 | output gl_l2t3_clk_stop ; |
| 818 | output gl_l2t4_clk_stop ; |
| 819 | output gl_l2t5_clk_stop ; |
| 820 | output gl_l2t6_clk_stop ; |
| 821 | output gl_l2t7_clk_stop ; |
| 822 | output gl_mac_io_clk_stop ; |
| 823 | output gl_mcu0_clk_stop ; |
| 824 | output gl_mcu0_dr_clk_stop ; |
| 825 | output gl_mcu0_io_clk_stop ; |
| 826 | output gl_mcu1_clk_stop ; |
| 827 | output gl_mcu1_dr_clk_stop ; |
| 828 | output gl_mcu1_io_clk_stop ; |
| 829 | output gl_mcu2_clk_stop ; |
| 830 | output gl_mcu2_dr_clk_stop ; |
| 831 | output gl_mcu2_io_clk_stop ; |
| 832 | output gl_mcu3_clk_stop ; |
| 833 | output gl_mcu3_dr_clk_stop ; |
| 834 | output gl_mcu3_io_clk_stop ; |
| 835 | output gl_mio_clk_stop_c1t ; |
| 836 | output gl_mio_clk_stop_c2t ; |
| 837 | output gl_mio_clk_stop_c3t ; |
| 838 | // output gl_mio_io2x_sync_en_c1b ; |
| 839 | output gl_mio_io2x_sync_en_c1t ; |
| 840 | output gl_ncu_clk_stop ; |
| 841 | output gl_ncu_io_clk_stop ; |
| 842 | output gl_peu_io_clk_stop ; |
| 843 | output gl_rdp_io_clk_stop ; |
| 844 | output gl_rst_clk_stop ; |
| 845 | output gl_rst_io_clk_stop ; |
| 846 | output gl_rst_l2_por_c1m ; |
| 847 | output gl_rst_l2_wmr_c1m ; |
| 848 | output gl_rst_mac_c1b ; |
| 849 | output gl_rst_niu_wmr_c1b ; |
| 850 | output gl_rtx_io_clk_stop ; |
| 851 | output gl_sii_clk_stop ; |
| 852 | output gl_sii_io_clk_stop ; |
| 853 | output gl_sio_clk_stop ; |
| 854 | output gl_sio_io_clk_stop ; |
| 855 | output gl_spc0_clk_stop ; |
| 856 | output gl_spc1_clk_stop ; |
| 857 | output gl_spc2_clk_stop ; |
| 858 | output gl_spc3_clk_stop ; |
| 859 | output gl_spc4_clk_stop ; |
| 860 | output gl_spc5_clk_stop ; |
| 861 | output gl_spc6_clk_stop ; |
| 862 | output gl_spc7_clk_stop ; |
| 863 | output gl_tds_io_clk_stop ; |
| 864 | output stg1_ccx_clk_stop_out_c1b ; |
| 865 | output stg1_cmp_io_sync_en_out_c1b ; |
| 866 | output stg1_cmp_io_sync_en_out_c1t ; |
| 867 | output stg1_db0_clk_stop_out_c1b ; |
| 868 | output stg1_dmu_io_clk_stop_out_c1b ; |
| 869 | output stg1_dmu_peu_por_out_c1b ; |
| 870 | output stg1_dmu_peu_wmr_out_c1b ; |
| 871 | output stg1_dr_sync_en_out_c1t ; |
| 872 | output stg1_io2x_out_out_c1b ; |
| 873 | output stg1_io2x_sync_en_out_c1b ; |
| 874 | output stg1_io2x_sync_en_out_c1t ; |
| 875 | output stg1_io_cmp_sync_en_out_c1b ; |
| 876 | output stg1_io_cmp_sync_en_out_c1t ; |
| 877 | output stg1_io_out_out_c1b ; |
| 878 | output stg1_io_out_out_c1t ; |
| 879 | output stg1_l2b0_clk_stop_out_c1t ; |
| 880 | output stg1_l2b1_clk_stop_out_c1t ; |
| 881 | output stg1_l2b2_clk_stop_out_c1b ; |
| 882 | output stg1_l2b3_clk_stop_out_c1b ; |
| 883 | output stg1_l2b4_clk_stop_out_c1t ; |
| 884 | output stg1_l2b5_clk_stop_out_c1t ; |
| 885 | output stg1_l2d0_clk_stop_out_c1t ; |
| 886 | output stg1_l2d1_clk_stop_out_c1t ; |
| 887 | output stg1_l2d2_clk_stop_out_c1b ; |
| 888 | output stg1_l2d3_clk_stop_out_c1b ; |
| 889 | output stg1_l2d4_clk_stop_out_c1t ; |
| 890 | output stg1_l2d5_clk_stop_out_c1t ; |
| 891 | output stg1_l2d7_clk_stop_out_c1b ; |
| 892 | output stg1_l2t0_clk_stop_out_c1t ; |
| 893 | output stg1_l2t1_clk_stop_out_c1t ; |
| 894 | output stg1_l2t2_clk_stop_out_c1b ; |
| 895 | output stg1_l2t3_clk_stop_out_c1b ; |
| 896 | output stg1_l2t5_clk_stop_out_c1t ; |
| 897 | output stg1_l2t7_clk_stop_out_c1b ; |
| 898 | output stg1_mac_io_clk_stop_out_c1b ; |
| 899 | output stg1_mcu0_clk_stop_out_c1t ; |
| 900 | output stg1_mcu0_dr_clk_stop_out_c1t ; |
| 901 | output stg1_mcu0_io_clk_stop_out_c1t ; |
| 902 | output stg1_mcu1_clk_stop_out_c1t ; |
| 903 | output stg1_mcu1_dr_clk_stop_out_c1t ; |
| 904 | output stg1_mcu1_io_clk_stop_out_c1t ; |
| 905 | output stg1_mio_clk_stop_out_c1t ; |
| 906 | output stg1_ncu_clk_stop_out_c1b ; |
| 907 | output stg1_ncu_io_clk_stop_out_c1b ; |
| 908 | output stg1_peu_io_clk_stop_out_c1b ; |
| 909 | output stg1_rdp_io_clk_stop_out_c1b ; |
| 910 | output stg1_rst_l2_por_out_c1b ; |
| 911 | output stg1_rst_l2_por_out_c1t ; |
| 912 | output stg1_rst_l2_wmr_out_c1b ; |
| 913 | output stg1_rst_l2_wmr_out_c1t ; |
| 914 | output stg1_rst_niu_mac_out_c1b ; |
| 915 | output stg1_rst_niu_wmr_out_c1b ; |
| 916 | output stg1_rtx_io_clk_stop_out_c1b ; |
| 917 | output stg1_sii_clk_stop_out_c1b ; |
| 918 | output stg1_sii_io_clk_stop_out_c1b ; |
| 919 | output stg1_spc0_clk_stop_out_c1t ; |
| 920 | output stg1_spc1_clk_stop_out_c1t ; |
| 921 | output stg1_spc2_clk_stop_out_c1b ; |
| 922 | output stg1_spc3_clk_stop_out_c1b ; |
| 923 | output stg1_spc4_clk_stop_out_c1t ; |
| 924 | output stg1_spc5_clk_stop_out_c1t ; |
| 925 | output stg1_spc6_clk_stop_out_c1b ; |
| 926 | output stg1_spc7_clk_stop_out_c1b ; |
| 927 | output stg1_tds_io_clk_stop_out_c1b ; |
| 928 | output stg2_ccx_clk_stop_out_c1b ; |
| 929 | output stg2_cmp_io_sync_en_out_c1b ; |
| 930 | output stg2_cmp_io_sync_en_out_c1t ; |
| 931 | output stg2_db0_clk_stop_out_c1b ; |
| 932 | output stg2_dmu_io_clk_stop_out_c1b ; |
| 933 | output stg2_dmu_peu_por_out_c1b ; |
| 934 | output stg2_dmu_peu_wmr_out_c1b ; |
| 935 | output stg2_dr_sync_en_out_c1t ; |
| 936 | output stg2_io_out_out_c1b; |
| 937 | output stg2_io_cmp_sync_en_out_c1b ; |
| 938 | output stg2_io_cmp_sync_en_out_c1t ; |
| 939 | output stg2_io_out_out_c1t ; |
| 940 | output stg2_l2_por_out_c1b ; |
| 941 | output stg2_l2_por_out_c1t ; |
| 942 | output stg2_l2_wmr_out_c1b ; |
| 943 | output stg2_l2_wmr_out_c1t ; |
| 944 | output stg2_l2b0_clk_stop_out_c1t ; |
| 945 | output stg2_l2b1_clk_stop_out_c1t ; |
| 946 | output stg2_l2b2_clk_stop_out_c1b ; |
| 947 | output stg2_l2b3_clk_stop_out_c1b ; |
| 948 | output stg2_l2d0_clk_stop_out_c1t ; |
| 949 | output stg2_l2d1_clk_stop_out_c1t ; |
| 950 | output stg2_l2d2_clk_stop_out_c1b ; |
| 951 | output stg2_l2d3_clk_stop_out_c1b ; |
| 952 | output stg2_l2t0_clk_stop_out_c1t ; |
| 953 | output stg2_l2t1_clk_stop_out_c1t ; |
| 954 | output stg2_l2t2_clk_stop_out_c1b ; |
| 955 | output stg2_l2t3_clk_stop_out_c1b ; |
| 956 | output stg2_l2t5_clk_stop_out_c1t ; |
| 957 | output stg2_l2t7_clk_stop_out_c1b ; |
| 958 | output stg2_mcu0_clk_stop_out_c1t ; |
| 959 | // output stg2_mcu0_dr_clk_stop_out_c1t ; |
| 960 | output stg2_mcu0_io_clk_stop_out_c1t ; |
| 961 | output stg2_mcu1_clk_stop_out_c1t ; |
| 962 | // output stg2_mcu1_dr_clk_stop_out_c1t ; |
| 963 | output stg2_mcu1_io_clk_stop_out_c1t ; |
| 964 | output stg2_mio_clk_stop_out_c1t ; |
| 965 | output stg2_mio_io2x_sync_en_out_c1t ; |
| 966 | output stg2_ncu_clk_stop_out_c1b ; |
| 967 | output stg2_ncu_io_clk_stop_out_c1b ; |
| 968 | output stg2_peu_io_clk_stop_out_c1b ; |
| 969 | output stg2_sii_clk_stop_out_c1b ; |
| 970 | output stg2_sii_io_clk_stop_out_c1b ; |
| 971 | output stg2_spc0_clk_stop_out_c1t ; |
| 972 | output stg2_spc1_clk_stop_out_c1t ; |
| 973 | output stg2_spc2_clk_stop_out_c1b ; |
| 974 | output stg2_spc3_clk_stop_out_c1b ; |
| 975 | output stg2_spc5_clk_stop_out_c1t ; |
| 976 | output stg2_spc7_clk_stop_out_c1b ; |
| 977 | output stg3_ccx_clk_stop_out_c2b ; |
| 978 | output stg3_cmp_io_sync_en_out_c2b ; |
| 979 | output stg3_cmp_io_sync_en_out_c2t ; |
| 980 | output stg3_db0_clk_stop_out_c2b ; |
| 981 | output stg3_dmu_io_clk_stop_out_c2b ; |
| 982 | output stg3_dmu_peu_por_out_c2b ; |
| 983 | output stg3_dmu_peu_wmr_out_c2b ; |
| 984 | output stg3_dr_sync_en_out_c2t ; |
| 985 | output stg3_io_cmp_sync_en_out_c2b ; |
| 986 | output stg3_io_cmp_sync_en_out_c2t ; |
| 987 | output stg3_io_out_out_c2t ; |
| 988 | output stg3_l2_por_out_c2b ; |
| 989 | output stg3_l2_por_out_c2t ; |
| 990 | output stg3_l2_wmr_out_c2b ; |
| 991 | output stg3_l2_wmr_out_c2t ; |
| 992 | output stg3_l2b0_clk_stop_out_c2t ; |
| 993 | output stg3_l2b1_clk_stop_out_c2t ; |
| 994 | output stg3_l2b2_clk_stop_out_c2b ; |
| 995 | output stg3_l2b3_clk_stop_out_c2b ; |
| 996 | output stg3_l2d0_clk_stop_out_c2t ; |
| 997 | output stg3_l2d1_clk_stop_out_c2t ; |
| 998 | output stg3_l2d2_clk_stop_out_c2b ; |
| 999 | output stg3_l2d3_clk_stop_out_c2b ; |
| 1000 | output stg3_l2t0_clk_stop_out_c2t ; |
| 1001 | output stg3_l2t1_clk_stop_out_c2t ; |
| 1002 | output stg3_l2t2_clk_stop_out_c2b ; |
| 1003 | output stg3_l2t3_clk_stop_out_c2b ; |
| 1004 | output stg3_l2t5_clk_stop_out_c2t ; |
| 1005 | output stg3_l2t7_clk_stop_out_c2b ; |
| 1006 | output stg3_mio_clk_stop_out_c2t ; |
| 1007 | output stg3_mio_io2x_sync_en_out_c2t ; |
| 1008 | output stg3_ncu_clk_stop_out_c2b ; |
| 1009 | output stg3_ncu_io_clk_stop_out_c2b ; |
| 1010 | output stg3_peu_io_clk_stop_out_c2b ; |
| 1011 | output stg3_sii_clk_stop_out_c2b ; |
| 1012 | output stg3_sii_io_clk_stop_out_c2b ; |
| 1013 | output stg3_spc0_clk_stop_out_c2t ; |
| 1014 | output stg3_spc1_clk_stop_out_c2t ; |
| 1015 | output stg3_spc2_clk_stop_out_c2b ; |
| 1016 | output stg3_spc3_clk_stop_out_c2b ; |
| 1017 | output stg3_spc5_clk_stop_out_c2t ; |
| 1018 | output stg3_spc7_clk_stop_out_c2b ; |
| 1019 | output stg4_cmp_io_sync_en_out_c3b ; |
| 1020 | output stg4_cmp_io_sync_en_out_c3t ; |
| 1021 | output stg4_db0_clk_stop_out_c3b ; |
| 1022 | output stg4_dmu_io_clk_stop_out_c3b ; |
| 1023 | output stg4_dmu_peu_por_out_c3b ; |
| 1024 | output stg4_dmu_peu_wmr_out_c3b ; |
| 1025 | output stg4_dr_sync_en_out_c3t ; |
| 1026 | // output stg4_io2x_sync_en_out_c2b ; |
| 1027 | output stg4_io_cmp_sync_en_out_c3b ; |
| 1028 | output stg4_io_cmp_sync_en_out_c3t ; |
| 1029 | output stg4_io_out_out_c3b ; |
| 1030 | output stg4_io_out_out_c3t ; |
| 1031 | output stg4_l2_por_out_c3b ; |
| 1032 | output stg4_l2_por_out_c3t ; |
| 1033 | output stg4_l2_wmr_out_c3b ; |
| 1034 | output stg4_l2_wmr_out_c3t ; |
| 1035 | output stg4_l2b0_clk_stop_out_c3t ; |
| 1036 | output stg4_l2b1_clk_stop_out_c3t ; |
| 1037 | output stg4_l2b2_clk_stop_out_c3b ; |
| 1038 | output stg4_l2b3_clk_stop_out_c3b ; |
| 1039 | output stg4_l2d0_clk_stop_out_c3t ; |
| 1040 | output stg4_l2d1_clk_stop_out_c3t ; |
| 1041 | output stg4_l2d2_clk_stop_out_c3b ; |
| 1042 | output stg4_l2d3_clk_stop_out_c3b ; |
| 1043 | output stg4_l2t0_clk_stop_out_c3t ; |
| 1044 | output stg4_mcu0_clk_stop_out_c3t ; |
| 1045 | // output stg4_mcu0_dr_clk_stop_out_c3t ; |
| 1046 | output stg4_mcu0_io_clk_stop_out_c3t ; |
| 1047 | output stg4_mcu1_clk_stop_out_c3t ; |
| 1048 | // output stg4_mcu1_dr_clk_stop_out_c3t ; |
| 1049 | output stg4_mcu1_io_clk_stop_out_c3t ; |
| 1050 | output stg4_mio_clk_stop_out_c3t ; |
| 1051 | output stg4_mio_io2x_sync_en_out_c3t ; |
| 1052 | output stg4_ncu_clk_stop_out_c3b ; |
| 1053 | output stg4_ncu_io_clk_stop_out_c3b ; |
| 1054 | output stg4_peu_io_clk_stop_out_c3b ; |
| 1055 | output stg4_sii_clk_stop_out_c3b ; |
| 1056 | output stg4_sii_io_clk_stop_out_c3b ; |
| 1057 | output stg4_spc0_clk_stop_out_c3t ; |
| 1058 | // output stg4_spc1_clk_stop_out_c2b ; |
| 1059 | output stg4_spc2_clk_stop_out_c3b ; |
| 1060 | // output stg4_spc5_clk_stop_out_c2b ; |
| 1061 | output gclk_aligned ; |
| 1062 | output stg4_l2t2_clk_stop_out_c3b ; |
| 1063 | |
| 1064 | |
| 1065 | |
| 1066 | wire dr_gclk_stg_tcu; |
| 1067 | wire dr_gclk_fsr7_stg; |
| 1068 | |
| 1069 | |
| 1070 | |
| 1071 | // special aligned signal |
| 1072 | // assign gclk_aligned = ccu_vco_aligned ; |
| 1073 | |
| 1074 | |
| 1075 | // dr clock tree |
| 1076 | n2_clk_gl_dr_tree gl_dr_clk_buffer ( |
| 1077 | .pll_dr_clk (pll_dr_clk), |
| 1078 | .dr_gclk_stg_tcu (dr_gclk_stg_tcu ), |
| 1079 | .dr_gclk_fsr7_stg (dr_gclk_fsr7_stg), |
| 1080 | .dr_gclk_c4_mcu0 ( dr_gclk_c4_mcu0 ), |
| 1081 | .dr_gclk_c4_mcu1 ( dr_gclk_c4_mcu1 ), |
| 1082 | .dr_gclk_c0_mcu2 ( dr_gclk_c0_mcu2 ), |
| 1083 | .dr_gclk_c0_mcu3 ( dr_gclk_c0_mcu3 ), |
| 1084 | .dr_gclk_c4_fsr0_0 ( dr_gclk_c4_fsr0_0 ), |
| 1085 | .dr_gclk_c4_fsr0_1 ( dr_gclk_c4_fsr0_1 ), |
| 1086 | .dr_gclk_c4_fsr0_2 ( dr_gclk_c4_fsr0_2 ), |
| 1087 | .dr_gclk_c4_fsr1_0 ( dr_gclk_c4_fsr1_0 ), |
| 1088 | .dr_gclk_c4_fsr1_1 ( dr_gclk_c4_fsr1_1 ), |
| 1089 | .dr_gclk_c4_fsr1_2 ( dr_gclk_c4_fsr1_2 ), |
| 1090 | .dr_gclk_c4_fsr2_0 ( dr_gclk_c4_fsr2_0 ), |
| 1091 | .dr_gclk_c4_fsr2_1 ( dr_gclk_c4_fsr2_1 ), |
| 1092 | .dr_gclk_c4_fsr2_2 ( dr_gclk_c4_fsr2_2 ), |
| 1093 | .dr_gclk_c4_fsr3_0 ( dr_gclk_c4_fsr3_0 ), |
| 1094 | .dr_gclk_c4_fsr3_1 ( dr_gclk_c4_fsr3_1 ), |
| 1095 | .dr_gclk_c4_fsr3_2 ( dr_gclk_c4_fsr3_2 ), |
| 1096 | .dr_gclk_c0_fsr4_0 ( dr_gclk_c0_fsr4_0 ), |
| 1097 | .dr_gclk_c0_fsr4_1 ( dr_gclk_c0_fsr4_1 ), |
| 1098 | .dr_gclk_c0_fsr4_2 ( dr_gclk_c0_fsr4_2 ), |
| 1099 | .dr_gclk_c0_fsr5_0 ( dr_gclk_c0_fsr5_0 ), |
| 1100 | .dr_gclk_c0_fsr5_1 ( dr_gclk_c0_fsr5_1 ), |
| 1101 | .dr_gclk_c0_fsr5_2 ( dr_gclk_c0_fsr5_2 ), |
| 1102 | .dr_gclk_c0_fsr6_0 ( dr_gclk_c0_fsr6_0 ), |
| 1103 | .dr_gclk_c0_fsr6_1 ( dr_gclk_c0_fsr6_1 ), |
| 1104 | .dr_gclk_c0_fsr6_2 ( dr_gclk_c0_fsr6_2 ), |
| 1105 | .dr_gclk_c2_fsr7_0 ( dr_gclk_c2_fsr7_0 ), |
| 1106 | .dr_gclk_c2_fsr7_1 ( dr_gclk_c2_fsr7_1 ), |
| 1107 | .dr_gclk_c2_fsr7_2 ( dr_gclk_c2_fsr7_2 ) |
| 1108 | ); |
| 1109 | |
| 1110 | |
| 1111 | // cmp clock tree |
| 1112 | n2_clk_gl_cmp_tree gl_cmp_clk_buffer ( |
| 1113 | .pll_cmp_clk (pll_cmp_clk), |
| 1114 | .cmp_gclk_c1_ccu(cmp_gclk_c1_ccu), |
| 1115 | .cmp_gclk_c3_rng(cmp_gclk_c3_rng), |
| 1116 | .cmp_gclk_c2_ccx_left(cmp_gclk_c2_ccx_left), |
| 1117 | .cmp_gclk_c2_ccx_right(cmp_gclk_c2_ccx_right), |
| 1118 | .cmp_gclk_c3_db0(cmp_gclk_c3_db0), |
| 1119 | .cmp_gclk_c1_db1(cmp_gclk_c1_db1), |
| 1120 | .cmp_gclk_c3_dmu(cmp_gclk_c3_dmu), |
| 1121 | .cmp_gclk_c1_efu(cmp_gclk_c1_efu), |
| 1122 | .cmp_gclk_c3_l2b0(cmp_gclk_c3_l2b0), |
| 1123 | .cmp_gclk_c3_l2b1(cmp_gclk_c3_l2b1), |
| 1124 | .cmp_gclk_c3_l2b2(cmp_gclk_c3_l2b2), |
| 1125 | .cmp_gclk_c3_l2b3(cmp_gclk_c3_l2b3), |
| 1126 | .cmp_gclk_c1_l2b4(cmp_gclk_c1_l2b4), |
| 1127 | .cmp_gclk_c1_l2b5(cmp_gclk_c1_l2b5), |
| 1128 | .cmp_gclk_c1_l2b6(cmp_gclk_c1_l2b6), |
| 1129 | .cmp_gclk_c1_l2b7(cmp_gclk_c1_l2b7), |
| 1130 | .cmp_gclk_c3_l2d0(cmp_gclk_c3_l2d0), |
| 1131 | .cmp_gclk_c3_l2d1(cmp_gclk_c3_l2d1), |
| 1132 | .cmp_gclk_c3_l2d2(cmp_gclk_c3_l2d2), |
| 1133 | .cmp_gclk_c3_l2d3(cmp_gclk_c3_l2d3), |
| 1134 | .cmp_gclk_c1_l2d4(cmp_gclk_c1_l2d4), |
| 1135 | .cmp_gclk_c1_l2d5(cmp_gclk_c1_l2d5), |
| 1136 | .cmp_gclk_c1_l2d6(cmp_gclk_c1_l2d6), |
| 1137 | .cmp_gclk_c1_l2d7(cmp_gclk_c1_l2d7), |
| 1138 | .cmp_gclk_c3_l2t0(cmp_gclk_c3_l2t0), |
| 1139 | .cmp_gclk_c3_l2t2(cmp_gclk_c3_l2t2), |
| 1140 | .cmp_gclk_c1_l2t4(cmp_gclk_c1_l2t4), |
| 1141 | .cmp_gclk_c1_l2t6(cmp_gclk_c1_l2t6), |
| 1142 | .cmp_gclk_c2_l2t1(cmp_gclk_c2_l2t1), |
| 1143 | .cmp_gclk_c2_l2t3(cmp_gclk_c2_l2t3), |
| 1144 | .cmp_gclk_c2_l2t5(cmp_gclk_c2_l2t5), |
| 1145 | .cmp_gclk_c2_l2t7(cmp_gclk_c2_l2t7), |
| 1146 | .cmp_gclk_c4_mcu0(cmp_gclk_c4_mcu0), |
| 1147 | .cmp_gclk_c4_mcu1(cmp_gclk_c4_mcu1), |
| 1148 | .cmp_gclk_c0_mcu2(cmp_gclk_c0_mcu2), |
| 1149 | .cmp_gclk_c0_mcu3(cmp_gclk_c0_mcu3), |
| 1150 | .cmp_gclk_c1_mio(cmp_gclk_c1_mio), |
| 1151 | .cmp_gclk_c3_mio(cmp_gclk_c3_mio), |
| 1152 | .cmp_gclk_c2_mio_left(cmp_gclk_c2_mio_left), |
| 1153 | .cmp_gclk_c2_mio_right(cmp_gclk_c2_mio_right), |
| 1154 | .cmp_gclk_c3_ncu(cmp_gclk_c3_ncu), |
| 1155 | .cmp_gclk_c3_peu(cmp_gclk_c3_peu), |
| 1156 | // .cmp_gclk_c1_rst(cmp_gclk_c1_rst), |
| 1157 | .cmp_gclk_c3_sii(cmp_gclk_c3_sii), |
| 1158 | .cmp_gclk_c1_sio(cmp_gclk_c1_sio), |
| 1159 | .cmp_gclk_c3_spc0(cmp_gclk_c3_spc0), |
| 1160 | .cmp_gclk_c3_spc2(cmp_gclk_c3_spc2), |
| 1161 | .cmp_gclk_c1_spc4(cmp_gclk_c1_spc4), |
| 1162 | .cmp_gclk_c1_spc6(cmp_gclk_c1_spc6), |
| 1163 | .cmp_gclk_c2_spc1(cmp_gclk_c2_spc1), |
| 1164 | .cmp_gclk_c2_spc3(cmp_gclk_c2_spc3), |
| 1165 | .cmp_gclk_c2_spc5(cmp_gclk_c2_spc5), |
| 1166 | .cmp_gclk_c2_spc7(cmp_gclk_c2_spc7), |
| 1167 | .cmp_gclk_c1_tcu(cmp_gclk_c1_tcu), |
| 1168 | .cmp_gclk_c1_mac(cmp_gclk_c1_mac), |
| 1169 | .cmp_gclk_c0_rdp(cmp_gclk_c0_rdp), |
| 1170 | .cmp_gclk_c0_rtx(cmp_gclk_c0_rtx), |
| 1171 | .cmp_gclk_c0_tds(cmp_gclk_c0_tds) |
| 1172 | ); |
| 1173 | |
| 1174 | |
| 1175 | // staging flops |
| 1176 | // Using file: n2_clk_gl_cc_stage_top.v |
| 1177 | // Searching for module 'n2_clk_gl_cc_stage_top' |
| 1178 | n2_clk_gl_cc_stage_top n2_clk_gl_cc_stage_top_inst ( |
| 1179 | // for int6.1 (set 3) |
| 1180 | .stg1_cmp_io_sync_en_in_c1bg ( stg1_cmp_io_sync_en_in_c1bg ), |
| 1181 | .stg1_cmp_io_sync_en_in_c1tg ( stg1_cmp_io_sync_en_in_c1tg ), |
| 1182 | .stg1_io_cmp_sync_en_in_c1bg ( stg1_io_cmp_sync_en_in_c1bg ), |
| 1183 | .stg1_io_cmp_sync_en_in_c1tg ( stg1_io_cmp_sync_en_in_c1tg ), |
| 1184 | .stg1_io_out_in_c1bg ( stg1_io_out_in_c1bg ), |
| 1185 | .stg1_l2_por_in_c1bg ( stg1_l2_por_in_c1bg ), |
| 1186 | .stg1_l2_por_in_c1tg ( stg1_l2_por_in_c1tg ), |
| 1187 | .stg1_l2_wmr_in_c1bg ( stg1_l2_wmr_in_c1bg ), |
| 1188 | .stg1_l2_wmr_in_c1tg ( stg1_l2_wmr_in_c1tg ), |
| 1189 | .stg1_mio_clk_stop_in_c1tg ( stg1_mio_clk_stop_in_c1tg ), |
| 1190 | .stg1_mio_io2x_sync_en_in_c1tg ( stg1_mio_io2x_sync_en_in_c1tg ), |
| 1191 | .stg4_cmp_io_sync_en_in_c3t0 ( stg4_cmp_io_sync_en_in_c3t0 ), |
| 1192 | .stg4_io_cmp_sync_en_in_c3t0 ( stg4_io_cmp_sync_en_in_c3t0 ), |
| 1193 | .stg4_io_out_in_c3b0 ( stg4_io_out_in_c3b0 ), |
| 1194 | .stg4_l2_por_in_c3t0 ( stg4_l2_por_in_c3t0 ), |
| 1195 | .stg4_l2_wmr_in_c3t0 ( stg4_l2_wmr_in_c3t0 ), |
| 1196 | |
| 1197 | .ccu_cmp_io_sync_en ( ccu_cmp_io_sync_en ), |
| 1198 | .ccu_dr_sync_en ( ccu_dr_sync_en ), |
| 1199 | .ccu_io2x_out ( ccu_io2x_out ), |
| 1200 | .ccu_io2x_sync_en ( ccu_io2x_sync_en ), |
| 1201 | .ccu_io_cmp_sync_en ( ccu_io_cmp_sync_en ), |
| 1202 | .ccu_io_out ( ccu_io_out ), |
| 1203 | .ccu_vco_aligned ( ccu_vco_aligned ), |
| 1204 | .dr_gclk_stg_tcu (dr_gclk_stg_tcu ), |
| 1205 | .dr_gclk_fsr7_stg (dr_gclk_fsr7_stg), |
| 1206 | .dr_gclk_c4_mcu1 ( dr_gclk_c4_mcu1 ), |
| 1207 | .gclk_a ( pll_cmp_clk ), |
| 1208 | .gclk_aligned ( gclk_aligned ), |
| 1209 | .gclk_b ( pll_cmp_clk ), |
| 1210 | .gclk_c ( pll_cmp_clk ), |
| 1211 | .gclk_ccu ( pll_cmp_clk ), |
| 1212 | .gclk_dmu ( pll_cmp_clk ), |
| 1213 | .gclk_l2b0 ( pll_cmp_clk ), |
| 1214 | .gclk_l2b4 ( pll_cmp_clk ), |
| 1215 | .gclk_l2b5 ( pll_cmp_clk ), |
| 1216 | .gclk_l2b6 ( pll_cmp_clk ), |
| 1217 | .gclk_l2d2 ( pll_cmp_clk ), |
| 1218 | .gclk_l2d5 ( pll_cmp_clk ), |
| 1219 | .gclk_l2d6 ( pll_cmp_clk ), |
| 1220 | .gclk_l2t0 ( pll_cmp_clk ), |
| 1221 | .gclk_l2t1 ( pll_cmp_clk ), |
| 1222 | .gclk_l2t2 ( pll_cmp_clk ), |
| 1223 | .gclk_l2t3 ( pll_cmp_clk ), |
| 1224 | .gclk_l2t4 ( pll_cmp_clk ), |
| 1225 | .gclk_l2t5 ( pll_cmp_clk ), |
| 1226 | .gclk_l2t6 ( pll_cmp_clk ), |
| 1227 | .gclk_l2t7 ( pll_cmp_clk ), |
| 1228 | .gclk_mac ( pll_cmp_clk ), |
| 1229 | .gclk_ncu ( pll_cmp_clk ), |
| 1230 | .gclk_rst ( pll_cmp_clk ), |
| 1231 | .gclk_spc0 ( pll_cmp_clk ), |
| 1232 | .gclk_spc1 ( pll_cmp_clk ), |
| 1233 | .gclk_spc2 ( pll_cmp_clk ), |
| 1234 | .gclk_spc3 ( pll_cmp_clk ), |
| 1235 | .gclk_spc4 ( pll_cmp_clk ), |
| 1236 | .gclk_spc5 ( pll_cmp_clk ), |
| 1237 | .gclk_spc6 ( pll_cmp_clk ), |
| 1238 | .gclk_spc6s ( pll_cmp_clk ), // for int6.1 (set 3) |
| 1239 | .gclk_spc7 ( pll_cmp_clk ), |
| 1240 | .gclk_tcu ( pll_cmp_clk ), |
| 1241 | .stg1_mcu0_dr_clk_stop_in_c2b (stg1_mcu0_dr_clk_stop_in_c2b), |
| 1242 | .stg1_mcu1_dr_clk_stop_in_c2b (stg1_mcu1_dr_clk_stop_in_c2b), |
| 1243 | .stg2_mcu0_dr_clk_stop_in_c4t (stg2_mcu0_dr_clk_stop_in_c4t), |
| 1244 | .stg2_mcu1_dr_clk_stop_in_c4t (stg2_mcu1_dr_clk_stop_in_c4t), |
| 1245 | .stg2_mcu0_dr_clk_stop_out_c2b (stg2_mcu0_dr_clk_stop_out_c2b), |
| 1246 | .stg2_mcu1_dr_clk_stop_out_c2b (stg2_mcu1_dr_clk_stop_out_c2b), |
| 1247 | .gl_ccu_clk_stop ( gl_ccu_clk_stop ), |
| 1248 | .gl_ccu_io_clk_stop ( gl_ccu_io_clk_stop ), |
| 1249 | .gl_ccx_clk_stop ( gl_ccx_clk_stop ), |
| 1250 | .gl_cmp_io_sync_en_c1b ( gl_cmp_io_sync_en_c1b ), |
| 1251 | .gl_cmp_io_sync_en_c1m ( gl_cmp_io_sync_en_c1m ), |
| 1252 | .gl_cmp_io_sync_en_c1t ( gl_cmp_io_sync_en_c1t ), |
| 1253 | .gl_cmp_io_sync_en_c2b ( gl_cmp_io_sync_en_c2b ), |
| 1254 | .gl_cmp_io_sync_en_c2t ( gl_cmp_io_sync_en_c2t ), |
| 1255 | .gl_cmp_io_sync_en_c3b ( gl_cmp_io_sync_en_c3b ), |
| 1256 | .gl_cmp_io_sync_en_c3t ( gl_cmp_io_sync_en_c3t ), |
| 1257 | .gl_cmp_io_sync_en_c3t0 ( gl_cmp_io_sync_en_c3t0 ), |
| 1258 | .gl_db0_clk_stop ( gl_db0_clk_stop ), |
| 1259 | .gl_db1_clk_stop ( gl_db1_clk_stop ), |
| 1260 | .gl_dmu_io_clk_stop ( gl_dmu_io_clk_stop ), |
| 1261 | .gl_dmu_peu_por_c3b ( gl_dmu_peu_por_c3b ), |
| 1262 | .gl_dmu_peu_wmr_c3b ( gl_dmu_peu_wmr_c3b ), |
| 1263 | .gl_dr_sync_en_c1m ( gl_dr_sync_en_c1m ), |
| 1264 | .gl_dr_sync_en_c3t ( gl_dr_sync_en_c3t ), |
| 1265 | .gl_efu_clk_stop ( gl_efu_clk_stop ), |
| 1266 | .gl_efu_io_clk_stop ( gl_efu_io_clk_stop ), |
| 1267 | .gl_io2x_out_c1b ( gl_io2x_out_c1b ), |
| 1268 | .gl_io2x_sync_en_c1m ( gl_io2x_sync_en_c1m ), |
| 1269 | .gl_io2x_sync_en_c3t ( gl_io2x_sync_en_c3t ), |
| 1270 | .gl_io2x_sync_en_c3t0 ( gl_io2x_sync_en_c3t0 ), |
| 1271 | .gl_io2x_sync_en_c2t ( gl_io2x_sync_en_c2t ), |
| 1272 | .gl_io_cmp_sync_en_c1b ( gl_io_cmp_sync_en_c1b ), |
| 1273 | .gl_io_cmp_sync_en_c1m ( gl_io_cmp_sync_en_c1m ), |
| 1274 | .gl_io_cmp_sync_en_c1t ( gl_io_cmp_sync_en_c1t ), |
| 1275 | .gl_io_cmp_sync_en_c2b ( gl_io_cmp_sync_en_c2b ), |
| 1276 | .gl_io_cmp_sync_en_c2t ( gl_io_cmp_sync_en_c2t ), |
| 1277 | .gl_io_cmp_sync_en_c3b ( gl_io_cmp_sync_en_c3b ), |
| 1278 | .gl_io_cmp_sync_en_c3t ( gl_io_cmp_sync_en_c3t ), |
| 1279 | .gl_io_cmp_sync_en_c3t0 ( gl_io_cmp_sync_en_c3t0 ), |
| 1280 | .gl_io_out_c1b ( gl_io_out_c1b ), |
| 1281 | .gl_io_out_c1m ( gl_io_out_c1m ), |
| 1282 | .gl_io_out_c3b ( gl_io_out_c3b ), |
| 1283 | .gl_io_out_c3b0 ( gl_io_out_c3b0 ), |
| 1284 | .gl_io_out_c3t ( gl_io_out_c3t ), |
| 1285 | .gl_l2_por_c1t ( gl_l2_por_c1t ), |
| 1286 | .gl_l2_por_c1b ( gl_l2_por_c1b ), // for int6.1 |
| 1287 | .gl_l2_por_c2b ( gl_l2_por_c2b ), |
| 1288 | .gl_l2_por_c2t ( gl_l2_por_c2t ), |
| 1289 | .gl_l2_por_c3b0 ( gl_l2_por_c3b0 ), |
| 1290 | .gl_l2_por_c3t ( gl_l2_por_c3t ), |
| 1291 | .gl_l2_por_c3t0 ( gl_l2_por_c3t0 ), |
| 1292 | .gl_l2_wmr_c1b ( gl_l2_wmr_c1b ), |
| 1293 | .gl_l2_wmr_c1t ( gl_l2_wmr_c1t ), |
| 1294 | .gl_l2_wmr_c2b ( gl_l2_wmr_c2b ), |
| 1295 | .gl_l2_wmr_c2t ( gl_l2_wmr_c2t ), |
| 1296 | .gl_l2_wmr_c3b ( gl_l2_wmr_c3b ), |
| 1297 | .gl_l2_wmr_c3t ( gl_l2_wmr_c3t ), |
| 1298 | .gl_l2_wmr_c3t0 ( gl_l2_wmr_c3t0 ), |
| 1299 | .gl_l2b0_clk_stop ( gl_l2b0_clk_stop ), |
| 1300 | .gl_l2b1_clk_stop ( gl_l2b1_clk_stop ), |
| 1301 | .gl_l2b2_clk_stop ( gl_l2b2_clk_stop ), |
| 1302 | .gl_l2b3_clk_stop ( gl_l2b3_clk_stop ), |
| 1303 | .gl_l2b4_clk_stop ( gl_l2b4_clk_stop ), |
| 1304 | .gl_l2b5_clk_stop ( gl_l2b5_clk_stop ), |
| 1305 | .gl_l2b6_clk_stop ( gl_l2b6_clk_stop ), |
| 1306 | .gl_l2b7_clk_stop ( gl_l2b7_clk_stop ), |
| 1307 | .gl_l2d0_clk_stop ( gl_l2d0_clk_stop ), |
| 1308 | .gl_l2d1_clk_stop ( gl_l2d1_clk_stop ), |
| 1309 | .gl_l2d2_clk_stop ( gl_l2d2_clk_stop ), |
| 1310 | .gl_l2d3_clk_stop ( gl_l2d3_clk_stop ), |
| 1311 | .gl_l2d4_clk_stop ( gl_l2d4_clk_stop ), |
| 1312 | .gl_l2d5_clk_stop ( gl_l2d5_clk_stop ), |
| 1313 | .gl_l2d7_clk_stop ( gl_l2d7_clk_stop ), |
| 1314 | .gl_l2d6_clk_stop ( gl_l2d6_clk_stop ), |
| 1315 | .gl_l2t0_clk_stop ( gl_l2t0_clk_stop ), |
| 1316 | .gl_l2t1_clk_stop ( gl_l2t1_clk_stop ), |
| 1317 | .gl_l2t2_clk_stop ( gl_l2t2_clk_stop ), |
| 1318 | .gl_l2t3_clk_stop ( gl_l2t3_clk_stop ), |
| 1319 | .gl_l2t4_clk_stop ( gl_l2t4_clk_stop ), |
| 1320 | .gl_l2t5_clk_stop ( gl_l2t5_clk_stop ), |
| 1321 | .gl_l2t6_clk_stop ( gl_l2t6_clk_stop ), |
| 1322 | .gl_l2t7_clk_stop ( gl_l2t7_clk_stop ), |
| 1323 | .gl_mac_io_clk_stop ( gl_mac_io_clk_stop ), |
| 1324 | .gl_mcu0_clk_stop ( gl_mcu0_clk_stop ), |
| 1325 | .gl_mcu0_dr_clk_stop ( gl_mcu0_dr_clk_stop ), |
| 1326 | .gl_mcu0_io_clk_stop ( gl_mcu0_io_clk_stop ), |
| 1327 | .gl_mcu1_clk_stop ( gl_mcu1_clk_stop ), |
| 1328 | .gl_mcu1_dr_clk_stop ( gl_mcu1_dr_clk_stop ), |
| 1329 | .gl_mcu1_io_clk_stop ( gl_mcu1_io_clk_stop ), |
| 1330 | .gl_mcu2_clk_stop ( gl_mcu2_clk_stop ), |
| 1331 | .gl_mcu2_dr_clk_stop ( gl_mcu2_dr_clk_stop ), |
| 1332 | .gl_mcu2_io_clk_stop ( gl_mcu2_io_clk_stop ), |
| 1333 | .gl_mcu3_clk_stop ( gl_mcu3_clk_stop ), |
| 1334 | .gl_mcu3_dr_clk_stop ( gl_mcu3_dr_clk_stop ), |
| 1335 | .gl_mcu3_io_clk_stop ( gl_mcu3_io_clk_stop ), |
| 1336 | .gl_mio_clk_stop_c1t ( gl_mio_clk_stop_c1t ), |
| 1337 | .gl_mio_clk_stop_c2t ( gl_mio_clk_stop_c2t ), |
| 1338 | .gl_mio_clk_stop_c3t ( gl_mio_clk_stop_c3t ), |
| 1339 | // .gl_mio_io2x_sync_en_c1b ( gl_mio_io2x_sync_en_c1b ), |
| 1340 | .gl_mio_io2x_sync_en_c1t ( gl_mio_io2x_sync_en_c1t ), |
| 1341 | .gl_ncu_clk_stop ( gl_ncu_clk_stop ), |
| 1342 | .gl_ncu_io_clk_stop ( gl_ncu_io_clk_stop ), |
| 1343 | .gl_peu_io_clk_stop ( gl_peu_io_clk_stop ), |
| 1344 | .gl_rdp_io_clk_stop ( gl_rdp_io_clk_stop ), |
| 1345 | .gl_rst_clk_stop ( gl_rst_clk_stop ), |
| 1346 | .gl_rst_io_clk_stop ( gl_rst_io_clk_stop ), |
| 1347 | .gl_rst_l2_por_c1m ( gl_rst_l2_por_c1m ), |
| 1348 | .gl_rst_l2_wmr_c1m ( gl_rst_l2_wmr_c1m ), |
| 1349 | .gl_rst_mac_c1b ( gl_rst_mac_c1b ), |
| 1350 | .gl_rst_niu_wmr_c1b ( gl_rst_niu_wmr_c1b ), |
| 1351 | .gl_rtx_io_clk_stop ( gl_rtx_io_clk_stop ), |
| 1352 | .gl_sii_clk_stop ( gl_sii_clk_stop ), |
| 1353 | .gl_sii_io_clk_stop ( gl_sii_io_clk_stop ), |
| 1354 | .gl_sio_clk_stop ( gl_sio_clk_stop ), |
| 1355 | .gl_sio_io_clk_stop ( gl_sio_io_clk_stop ), |
| 1356 | .gl_spc0_clk_stop ( gl_spc0_clk_stop ), |
| 1357 | .gl_spc1_clk_stop ( gl_spc1_clk_stop ), |
| 1358 | .gl_spc2_clk_stop ( gl_spc2_clk_stop ), |
| 1359 | .gl_spc3_clk_stop ( gl_spc3_clk_stop ), |
| 1360 | .gl_spc4_clk_stop ( gl_spc4_clk_stop ), |
| 1361 | .gl_spc5_clk_stop ( gl_spc5_clk_stop ), |
| 1362 | .gl_spc6_clk_stop ( gl_spc6_clk_stop ), |
| 1363 | .gl_spc7_clk_stop ( gl_spc7_clk_stop ), |
| 1364 | .gl_tds_io_clk_stop ( gl_tds_io_clk_stop ), |
| 1365 | .rst_dmu_peu_por_ ( rst_dmu_peu_por_ ), |
| 1366 | .rst_dmu_peu_wmr_ ( rst_dmu_peu_wmr_ ), |
| 1367 | .rst_l2_por_ ( rst_l2_por_ ), |
| 1368 | .rst_l2_wmr_ ( rst_l2_wmr_ ), |
| 1369 | .rst_niu_mac_ ( rst_niu_mac_ ), |
| 1370 | .rst_niu_wmr_ ( rst_niu_wmr_ ), |
| 1371 | .stg1_ccx_clk_stop_in_c1b ( stg1_ccx_clk_stop_in_c1b ), |
| 1372 | .stg1_ccx_clk_stop_out_c1b ( stg1_ccx_clk_stop_out_c1b ), |
| 1373 | .stg1_cmp_io_sync_en_in_c1b ( stg1_cmp_io_sync_en_in_c1b ), |
| 1374 | .stg1_cmp_io_sync_en_in_c1t ( stg1_cmp_io_sync_en_in_c1t ), |
| 1375 | .stg1_cmp_io_sync_en_out_c1b ( stg1_cmp_io_sync_en_out_c1b ), |
| 1376 | .stg1_cmp_io_sync_en_out_c1t ( stg1_cmp_io_sync_en_out_c1t ), |
| 1377 | .stg1_db0_clk_stop_in_c1b ( stg1_db0_clk_stop_in_c1b ), |
| 1378 | .stg1_db0_clk_stop_out_c1b ( stg1_db0_clk_stop_out_c1b ), |
| 1379 | .stg1_dmu_io_clk_stop_in_c1b ( stg1_dmu_io_clk_stop_in_c1b ), |
| 1380 | .stg1_dmu_io_clk_stop_out_c1b ( stg1_dmu_io_clk_stop_out_c1b ), |
| 1381 | .stg1_dmu_peu_por_in_c1b ( stg1_dmu_peu_por_in_c1b ), |
| 1382 | .stg1_dmu_peu_por_out_c1b ( stg1_dmu_peu_por_out_c1b ), |
| 1383 | .stg1_dmu_peu_wmr_in_c1b ( stg1_dmu_peu_wmr_in_c1b ), |
| 1384 | .stg1_dmu_peu_wmr_out_c1b ( stg1_dmu_peu_wmr_out_c1b ), |
| 1385 | .stg1_dr_sync_en_in_c1t ( stg1_dr_sync_en_in_c1t ), |
| 1386 | .stg1_dr_sync_en_out_c1t ( stg1_dr_sync_en_out_c1t ), |
| 1387 | .stg1_io2x_out_in_c1b ( stg1_io2x_out_in_c1b ), |
| 1388 | .stg1_io2x_out_out_c1b ( stg1_io2x_out_out_c1b ), |
| 1389 | .stg1_io2x_sync_en_out_c1b ( stg1_io2x_sync_en_out_c1b ), |
| 1390 | .stg1_io2x_sync_en_out_c1t ( stg1_io2x_sync_en_out_c1t ), |
| 1391 | .stg1_io_cmp_sync_en_in_c1b ( stg1_io_cmp_sync_en_in_c1b ), |
| 1392 | .stg1_io_cmp_sync_en_in_c1t ( stg1_io_cmp_sync_en_in_c1t ), |
| 1393 | .stg1_io_cmp_sync_en_out_c1b ( stg1_io_cmp_sync_en_out_c1b ), |
| 1394 | .stg1_io_cmp_sync_en_out_c1t ( stg1_io_cmp_sync_en_out_c1t ), |
| 1395 | .stg1_io_out_in_c1b ( stg1_io_out_in_c1b ), |
| 1396 | .stg1_io_out_in_c1t ( stg1_io_out_in_c1t ), |
| 1397 | .stg1_io_out_out_c1b ( stg1_io_out_out_c1b ), |
| 1398 | .stg1_io_out_out_c1t ( stg1_io_out_out_c1t ), |
| 1399 | .stg1_l2_por_in_c1b ( stg1_l2_por_in_c1b ), |
| 1400 | .stg1_l2_por_in_c1t ( stg1_l2_por_in_c1t ), |
| 1401 | .stg1_l2_wmr_in_c1b ( stg1_l2_wmr_in_c1b ), |
| 1402 | .stg1_l2_wmr_in_c1t ( stg1_l2_wmr_in_c1t ), |
| 1403 | .stg1_l2b0_clk_stop_in_c1t ( stg1_l2b0_clk_stop_in_c1t ), |
| 1404 | .stg1_l2b0_clk_stop_out_c1t ( stg1_l2b0_clk_stop_out_c1t ), |
| 1405 | .stg1_l2b1_clk_stop_in_c1t ( stg1_l2b1_clk_stop_in_c1t ), |
| 1406 | .stg1_l2b1_clk_stop_out_c1t ( stg1_l2b1_clk_stop_out_c1t ), |
| 1407 | .stg1_l2b2_clk_stop_in_c1b ( stg1_l2b2_clk_stop_in_c1b ), |
| 1408 | .stg1_l2b2_clk_stop_out_c1b ( stg1_l2b2_clk_stop_out_c1b ), |
| 1409 | .stg1_l2b3_clk_stop_in_c1b ( stg1_l2b3_clk_stop_in_c1b ), |
| 1410 | .stg1_l2b3_clk_stop_out_c1b ( stg1_l2b3_clk_stop_out_c1b ), |
| 1411 | .stg1_l2b4_clk_stop_in_c1t ( stg1_l2b4_clk_stop_in_c1t ), |
| 1412 | .stg1_l2b4_clk_stop_out_c1t ( stg1_l2b4_clk_stop_out_c1t ), |
| 1413 | .stg1_l2b5_clk_stop_in_c1t ( stg1_l2b5_clk_stop_in_c1t ), |
| 1414 | .stg1_l2b5_clk_stop_out_c1t ( stg1_l2b5_clk_stop_out_c1t ), |
| 1415 | .stg1_l2d0_clk_stop_in_c1t ( stg1_l2d0_clk_stop_in_c1t ), |
| 1416 | .stg1_l2d0_clk_stop_out_c1t ( stg1_l2d0_clk_stop_out_c1t ), |
| 1417 | .stg1_l2d1_clk_stop_in_c1t ( stg1_l2d1_clk_stop_in_c1t ), |
| 1418 | .stg1_l2d1_clk_stop_out_c1t ( stg1_l2d1_clk_stop_out_c1t ), |
| 1419 | .stg1_l2d2_clk_stop_in_c1b ( stg1_l2d2_clk_stop_in_c1b ), |
| 1420 | .stg1_l2d2_clk_stop_out_c1b ( stg1_l2d2_clk_stop_out_c1b ), |
| 1421 | .stg1_l2d3_clk_stop_in_c1b ( stg1_l2d3_clk_stop_in_c1b ), |
| 1422 | .stg1_l2d3_clk_stop_out_c1b ( stg1_l2d3_clk_stop_out_c1b ), |
| 1423 | .stg1_l2d4_clk_stop_in_c1t ( stg1_l2d4_clk_stop_in_c1t ), |
| 1424 | .stg1_l2d4_clk_stop_out_c1t ( stg1_l2d4_clk_stop_out_c1t ), |
| 1425 | .stg1_l2d5_clk_stop_in_c1t ( stg1_l2d5_clk_stop_in_c1t ), |
| 1426 | .stg1_l2d5_clk_stop_out_c1t ( stg1_l2d5_clk_stop_out_c1t ), |
| 1427 | .stg1_l2d7_clk_stop_in_c1b ( stg1_l2d7_clk_stop_in_c1b ), |
| 1428 | .stg1_l2d7_clk_stop_out_c1b ( stg1_l2d7_clk_stop_out_c1b ), |
| 1429 | .stg1_l2t0_clk_stop_in_c1t ( stg1_l2t0_clk_stop_in_c1t ), |
| 1430 | .stg1_l2t0_clk_stop_out_c1t ( stg1_l2t0_clk_stop_out_c1t ), |
| 1431 | .stg1_l2t1_clk_stop_in_c1t ( stg1_l2t1_clk_stop_in_c1t ), |
| 1432 | .stg1_l2t1_clk_stop_out_c1t ( stg1_l2t1_clk_stop_out_c1t ), |
| 1433 | .stg1_l2t2_clk_stop_in_c1b ( stg1_l2t2_clk_stop_in_c1b ), |
| 1434 | .stg1_l2t2_clk_stop_out_c1b ( stg1_l2t2_clk_stop_out_c1b ), |
| 1435 | .stg1_l2t3_clk_stop_in_c1b ( stg1_l2t3_clk_stop_in_c1b ), |
| 1436 | .stg1_l2t3_clk_stop_out_c1b ( stg1_l2t3_clk_stop_out_c1b ), |
| 1437 | .stg1_l2t5_clk_stop_in_c1t ( stg1_l2t5_clk_stop_in_c1t ), |
| 1438 | .stg1_l2t5_clk_stop_out_c1t ( stg1_l2t5_clk_stop_out_c1t ), |
| 1439 | .stg1_l2t7_clk_stop_in_c1b ( stg1_l2t7_clk_stop_in_c1b ), |
| 1440 | .stg1_l2t7_clk_stop_out_c1b ( stg1_l2t7_clk_stop_out_c1b ), |
| 1441 | .stg1_mac_io_clk_stop_in_c1b ( stg1_mac_io_clk_stop_in_c1b ), |
| 1442 | .stg1_mac_io_clk_stop_out_c1b ( stg1_mac_io_clk_stop_out_c1b ), |
| 1443 | .stg1_mcu0_clk_stop_in_c1t ( stg1_mcu0_clk_stop_in_c1t ), |
| 1444 | .stg1_mcu0_clk_stop_out_c1t ( stg1_mcu0_clk_stop_out_c1t ), |
| 1445 | // .stg1_mcu0_dr_clk_stop_in_c1t ( stg1_mcu0_dr_clk_stop_in_c1t ), |
| 1446 | .stg1_mcu0_dr_clk_stop_out_c1t ( stg1_mcu0_dr_clk_stop_out_c1t ), |
| 1447 | .stg1_mcu0_io_clk_stop_in_c1t ( stg1_mcu0_io_clk_stop_in_c1t ), |
| 1448 | .stg1_mcu0_io_clk_stop_out_c1t ( stg1_mcu0_io_clk_stop_out_c1t ), |
| 1449 | .stg1_mcu1_clk_stop_in_c1t ( stg1_mcu1_clk_stop_in_c1t ), |
| 1450 | .stg1_mcu1_clk_stop_out_c1t ( stg1_mcu1_clk_stop_out_c1t ), |
| 1451 | // .stg1_mcu1_dr_clk_stop_in_c1t ( stg1_mcu1_dr_clk_stop_in_c1t ), |
| 1452 | .stg1_mcu1_dr_clk_stop_out_c1t ( stg1_mcu1_dr_clk_stop_out_c1t ), |
| 1453 | .stg1_mcu1_io_clk_stop_in_c1t ( stg1_mcu1_io_clk_stop_in_c1t ), |
| 1454 | .stg1_mcu1_io_clk_stop_out_c1t ( stg1_mcu1_io_clk_stop_out_c1t ), |
| 1455 | .stg1_mio_clk_stop_in_c1t ( stg1_mio_clk_stop_in_c1t ), |
| 1456 | .stg1_mio_clk_stop_out_c1t ( stg1_mio_clk_stop_out_c1t ), |
| 1457 | .stg1_mio_io2x_sync_en_in_c1t ( stg1_mio_io2x_sync_en_in_c1t ), |
| 1458 | .stg1_ncu_clk_stop_in_c1b ( stg1_ncu_clk_stop_in_c1b ), |
| 1459 | .stg1_ncu_clk_stop_out_c1b ( stg1_ncu_clk_stop_out_c1b ), |
| 1460 | .stg1_ncu_io_clk_stop_in_c1b ( stg1_ncu_io_clk_stop_in_c1b ), |
| 1461 | .stg1_ncu_io_clk_stop_out_c1b ( stg1_ncu_io_clk_stop_out_c1b ), |
| 1462 | .stg1_peu_io_clk_stop_in_c1b ( stg1_peu_io_clk_stop_in_c1b ), |
| 1463 | .stg1_peu_io_clk_stop_out_c1b ( stg1_peu_io_clk_stop_out_c1b ), |
| 1464 | .stg1_rdp_io_clk_stop_in_c1b ( stg1_rdp_io_clk_stop_in_c1b ), |
| 1465 | .stg1_rdp_io_clk_stop_out_c1b ( stg1_rdp_io_clk_stop_out_c1b ), |
| 1466 | .stg1_rst_l2_por_out_c1b ( stg1_rst_l2_por_out_c1b ), |
| 1467 | .stg1_rst_l2_por_out_c1t ( stg1_rst_l2_por_out_c1t ), |
| 1468 | .stg1_rst_l2_wmr_out_c1b ( stg1_rst_l2_wmr_out_c1b ), |
| 1469 | .stg1_rst_l2_wmr_out_c1t ( stg1_rst_l2_wmr_out_c1t ), |
| 1470 | .stg1_rst_mac_in_c1b ( stg1_rst_mac_in_c1b ), |
| 1471 | .stg1_rst_niu_mac_out_c1b ( stg1_rst_niu_mac_out_c1b ), |
| 1472 | .stg1_rst_niu_wmr_in_c1b ( stg1_rst_niu_wmr_in_c1b ), |
| 1473 | .stg1_rst_niu_wmr_out_c1b ( stg1_rst_niu_wmr_out_c1b ), |
| 1474 | .stg1_rtx_io_clk_stop_in_c1b ( stg1_rtx_io_clk_stop_in_c1b ), |
| 1475 | .stg1_rtx_io_clk_stop_out_c1b ( stg1_rtx_io_clk_stop_out_c1b ), |
| 1476 | .stg1_sii_clk_stop_in_c1b ( stg1_sii_clk_stop_in_c1b ), |
| 1477 | .stg1_sii_clk_stop_out_c1b ( stg1_sii_clk_stop_out_c1b ), |
| 1478 | .stg1_sii_io_clk_stop_in_c1b ( stg1_sii_io_clk_stop_in_c1b ), |
| 1479 | .stg1_sii_io_clk_stop_out_c1b ( stg1_sii_io_clk_stop_out_c1b ), |
| 1480 | .stg1_spc0_clk_stop_in_c1t ( stg1_spc0_clk_stop_in_c1t ), |
| 1481 | .stg1_spc0_clk_stop_out_c1t ( stg1_spc0_clk_stop_out_c1t ), |
| 1482 | .stg1_spc1_clk_stop_in_c1t ( stg1_spc1_clk_stop_in_c1t ), |
| 1483 | .stg1_spc1_clk_stop_out_c1t ( stg1_spc1_clk_stop_out_c1t ), |
| 1484 | .stg1_spc2_clk_stop_in_c1b ( stg1_spc2_clk_stop_in_c1b ), |
| 1485 | .stg1_spc2_clk_stop_out_c1b ( stg1_spc2_clk_stop_out_c1b ), |
| 1486 | .stg1_spc3_clk_stop_in_c1b ( stg1_spc3_clk_stop_in_c1b ), |
| 1487 | .stg1_spc3_clk_stop_out_c1b ( stg1_spc3_clk_stop_out_c1b ), |
| 1488 | .stg1_spc4_clk_stop_in_c1t ( stg1_spc4_clk_stop_in_c1t ), |
| 1489 | .stg1_spc4_clk_stop_out_c1t ( stg1_spc4_clk_stop_out_c1t ), |
| 1490 | .stg1_spc5_clk_stop_in_c1t ( stg1_spc5_clk_stop_in_c1t ), |
| 1491 | .stg1_spc5_clk_stop_out_c1t ( stg1_spc5_clk_stop_out_c1t ), |
| 1492 | .stg1_spc6_clk_stop_in_c1b ( stg1_spc6_clk_stop_in_c1b ), // for int6.1 (set 3) |
| 1493 | .stg1_spc6_clk_stop_out_c1b ( stg1_spc6_clk_stop_out_c1b ), |
| 1494 | .stg1_spc7_clk_stop_in_c1b ( stg1_spc7_clk_stop_in_c1b ), |
| 1495 | .stg1_spc7_clk_stop_out_c1b ( stg1_spc7_clk_stop_out_c1b ), |
| 1496 | .stg1_tds_io_clk_stop_in_c1b ( stg1_tds_io_clk_stop_in_c1b ), |
| 1497 | .stg1_tds_io_clk_stop_out_c1b ( stg1_tds_io_clk_stop_out_c1b ), |
| 1498 | .stg2_io_out_out_c1b ( stg2_io_out_out_c1b), |
| 1499 | .stg2_ccx_clk_stop_in_c2b ( stg2_ccx_clk_stop_in_c2b ), |
| 1500 | .stg2_ccx_clk_stop_out_c1b ( stg2_ccx_clk_stop_out_c1b ), |
| 1501 | .stg2_cmp_io_sync_en_in_c2b ( stg2_cmp_io_sync_en_in_c2b ), |
| 1502 | .stg2_cmp_io_sync_en_in_c2t ( stg2_cmp_io_sync_en_in_c2t ), |
| 1503 | .stg2_cmp_io_sync_en_out_c1b ( stg2_cmp_io_sync_en_out_c1b ), |
| 1504 | .stg2_cmp_io_sync_en_out_c1t ( stg2_cmp_io_sync_en_out_c1t ), |
| 1505 | .stg2_db0_clk_stop_in_c2b ( stg2_db0_clk_stop_in_c2b ), |
| 1506 | .stg2_db0_clk_stop_out_c1b ( stg2_db0_clk_stop_out_c1b ), |
| 1507 | .stg2_dmu_io_clk_stop_in_c2b ( stg2_dmu_io_clk_stop_in_c2b ), |
| 1508 | .stg2_dmu_io_clk_stop_out_c1b ( stg2_dmu_io_clk_stop_out_c1b ), |
| 1509 | .stg2_dmu_peu_por_in_c2b ( stg2_dmu_peu_por_in_c2b ), |
| 1510 | .stg2_dmu_peu_por_out_c1b ( stg2_dmu_peu_por_out_c1b ), |
| 1511 | .stg2_dmu_peu_wmr_in_c2b ( stg2_dmu_peu_wmr_in_c2b ), |
| 1512 | .stg2_dmu_peu_wmr_out_c1b ( stg2_dmu_peu_wmr_out_c1b ), |
| 1513 | .stg2_dr_sync_en_in_c2t ( stg2_dr_sync_en_in_c2t ), |
| 1514 | .stg2_dr_sync_en_out_c1t ( stg2_dr_sync_en_out_c1t ), |
| 1515 | .stg2_io_cmp_sync_en_in_c2b ( stg2_io_cmp_sync_en_in_c2b ), |
| 1516 | .stg2_io_cmp_sync_en_in_c2t ( stg2_io_cmp_sync_en_in_c2t ), |
| 1517 | .stg2_io_cmp_sync_en_out_c1b ( stg2_io_cmp_sync_en_out_c1b ), |
| 1518 | .stg2_io_cmp_sync_en_out_c1t ( stg2_io_cmp_sync_en_out_c1t ), |
| 1519 | .stg2_io_out_in_c2t ( stg2_io_out_in_c2t ), |
| 1520 | .stg2_io_out_out_c1t ( stg2_io_out_out_c1t ), |
| 1521 | .stg2_io2x_sync_en_in_c2t (stg2_io2x_sync_en_in_c2t ), |
| 1522 | .stg2_l2_por_in_c2b ( stg2_l2_por_in_c2b ), |
| 1523 | .stg2_l2_por_in_c2t ( stg2_l2_por_in_c2t ), |
| 1524 | .stg2_l2_por_out_c1b ( stg2_l2_por_out_c1b ), |
| 1525 | .stg2_l2_por_out_c1t ( stg2_l2_por_out_c1t ), |
| 1526 | .stg2_l2_wmr_in_c2b ( stg2_l2_wmr_in_c2b ), |
| 1527 | .stg2_l2_wmr_in_c2t ( stg2_l2_wmr_in_c2t ), |
| 1528 | .stg2_l2_wmr_out_c1b ( stg2_l2_wmr_out_c1b ), |
| 1529 | .stg2_l2_wmr_out_c1t ( stg2_l2_wmr_out_c1t ), |
| 1530 | .stg2_io_out_in_c2b (stg2_io_out_in_c2b ), |
| 1531 | .stg2_l2b0_clk_stop_in_c2t ( stg2_l2b0_clk_stop_in_c2t ), |
| 1532 | .stg2_l2b0_clk_stop_out_c1t ( stg2_l2b0_clk_stop_out_c1t ), |
| 1533 | .stg2_l2b1_clk_stop_in_c2t ( stg2_l2b1_clk_stop_in_c2t ), |
| 1534 | .stg2_l2b1_clk_stop_out_c1t ( stg2_l2b1_clk_stop_out_c1t ), |
| 1535 | .stg2_l2b2_clk_stop_in_c2b ( stg2_l2b2_clk_stop_in_c2b ), |
| 1536 | .stg2_l2b2_clk_stop_out_c1b ( stg2_l2b2_clk_stop_out_c1b ), |
| 1537 | .stg2_l2b3_clk_stop_in_c2b ( stg2_l2b3_clk_stop_in_c2b ), |
| 1538 | .stg2_l2b3_clk_stop_out_c1b ( stg2_l2b3_clk_stop_out_c1b ), |
| 1539 | .stg2_l2d0_clk_stop_in_c2t ( stg2_l2d0_clk_stop_in_c2t ), |
| 1540 | .stg2_l2d0_clk_stop_out_c1t ( stg2_l2d0_clk_stop_out_c1t ), |
| 1541 | .stg2_l2d1_clk_stop_in_c2t ( stg2_l2d1_clk_stop_in_c2t ), |
| 1542 | .stg2_l2d1_clk_stop_out_c1t ( stg2_l2d1_clk_stop_out_c1t ), |
| 1543 | .stg2_l2d2_clk_stop_in_c2b ( stg2_l2d2_clk_stop_in_c2b ), |
| 1544 | .stg2_l2d2_clk_stop_out_c1b ( stg2_l2d2_clk_stop_out_c1b ), |
| 1545 | .stg2_l2d3_clk_stop_in_c2b ( stg2_l2d3_clk_stop_in_c2b ), |
| 1546 | .stg2_l2d3_clk_stop_out_c1b ( stg2_l2d3_clk_stop_out_c1b ), |
| 1547 | .stg2_l2t0_clk_stop_in_c2t ( stg2_l2t0_clk_stop_in_c2t ), |
| 1548 | .stg2_l2t0_clk_stop_out_c1t ( stg2_l2t0_clk_stop_out_c1t ), |
| 1549 | .stg2_l2t1_clk_stop_in_c2t ( stg2_l2t1_clk_stop_in_c2t ), |
| 1550 | .stg2_l2t1_clk_stop_out_c1t ( stg2_l2t1_clk_stop_out_c1t ), |
| 1551 | .stg2_l2t2_clk_stop_in_c2b ( stg2_l2t2_clk_stop_in_c2b ), |
| 1552 | .stg2_l2t2_clk_stop_out_c1b ( stg2_l2t2_clk_stop_out_c1b ), |
| 1553 | .stg2_l2t3_clk_stop_in_c2bz ( stg2_l2t3_clk_stop_in_c2bz ), |
| 1554 | .stg2_l2t3_clk_stop_out_c1b ( stg2_l2t3_clk_stop_out_c1b ), |
| 1555 | .stg2_l2t5_clk_stop_in_c2t ( stg2_l2t5_clk_stop_in_c2t ), |
| 1556 | .stg2_l2t5_clk_stop_out_c1t ( stg2_l2t5_clk_stop_out_c1t ), |
| 1557 | .stg2_l2t7_clk_stop_in_c2b ( stg2_l2t7_clk_stop_in_c2b ), |
| 1558 | .stg2_l2t7_clk_stop_out_c1b ( stg2_l2t7_clk_stop_out_c1b ), |
| 1559 | .stg2_mcu0_clk_stop_out_c1t ( stg2_mcu0_clk_stop_out_c1t ), |
| 1560 | // .stg2_mcu0_dr_clk_stop_out_c1t ( stg2_mcu0_dr_clk_stop_out_c1t ), |
| 1561 | .stg2_mcu0_io_clk_stop_out_c1t ( stg2_mcu0_io_clk_stop_out_c1t ), |
| 1562 | .stg2_mcu1_clk_stop_out_c1t ( stg2_mcu1_clk_stop_out_c1t ), |
| 1563 | // .stg2_mcu1_dr_clk_stop_out_c1t ( stg2_mcu1_dr_clk_stop_out_c1t ), |
| 1564 | .stg2_mcu1_io_clk_stop_out_c1t ( stg2_mcu1_io_clk_stop_out_c1t ), |
| 1565 | .stg2_mio_clk_stop_in_c2t ( stg2_mio_clk_stop_in_c2t ), |
| 1566 | .stg2_mio_clk_stop_out_c1t ( stg2_mio_clk_stop_out_c1t ), |
| 1567 | .stg2_mio_io2x_sync_en_in_c2t ( stg2_mio_io2x_sync_en_in_c2t ), |
| 1568 | .stg2_mio_io2x_sync_en_out_c1t ( stg2_mio_io2x_sync_en_out_c1t ), |
| 1569 | .stg2_ncu_clk_stop_in_c2b ( stg2_ncu_clk_stop_in_c2b ), |
| 1570 | .stg2_ncu_clk_stop_out_c1b ( stg2_ncu_clk_stop_out_c1b ), |
| 1571 | .stg2_ncu_io_clk_stop_in_c2b ( stg2_ncu_io_clk_stop_in_c2b ), |
| 1572 | .stg2_ncu_io_clk_stop_out_c1b ( stg2_ncu_io_clk_stop_out_c1b ), |
| 1573 | .stg2_peu_io_clk_stop_in_c2b ( stg2_peu_io_clk_stop_in_c2b ), |
| 1574 | .stg2_peu_io_clk_stop_out_c1b ( stg2_peu_io_clk_stop_out_c1b ), |
| 1575 | .stg2_sii_clk_stop_in_c2b ( stg2_sii_clk_stop_in_c2b ), |
| 1576 | .stg2_sii_clk_stop_out_c1b ( stg2_sii_clk_stop_out_c1b ), |
| 1577 | .stg2_sii_io_clk_stop_in_c2b ( stg2_sii_io_clk_stop_in_c2b ), |
| 1578 | .stg2_sii_io_clk_stop_out_c1b ( stg2_sii_io_clk_stop_out_c1b ), |
| 1579 | .stg2_spc0_clk_stop_in_c2t ( stg2_spc0_clk_stop_in_c2t ), |
| 1580 | .stg2_spc0_clk_stop_out_c1t ( stg2_spc0_clk_stop_out_c1t ), |
| 1581 | .stg2_spc1_clk_stop_in_c2t ( stg2_spc1_clk_stop_in_c2t ), |
| 1582 | .stg2_spc1_clk_stop_out_c1t ( stg2_spc1_clk_stop_out_c1t ), |
| 1583 | .stg2_spc2_clk_stop_in_c2b ( stg2_spc2_clk_stop_in_c2b ), |
| 1584 | .stg2_spc2_clk_stop_out_c1b ( stg2_spc2_clk_stop_out_c1b ), |
| 1585 | .stg2_spc3_clk_stop_in_c2b ( stg2_spc3_clk_stop_in_c2b ), |
| 1586 | .stg2_spc3_clk_stop_out_c1b ( stg2_spc3_clk_stop_out_c1b ), |
| 1587 | .stg2_spc5_clk_stop_in_c2t ( stg2_spc5_clk_stop_in_c2t ), |
| 1588 | .stg2_spc5_clk_stop_out_c1t ( stg2_spc5_clk_stop_out_c1t ), |
| 1589 | .stg2_spc7_clk_stop_in_c2b ( stg2_spc7_clk_stop_in_c2b ), |
| 1590 | .stg2_spc7_clk_stop_out_c1b ( stg2_spc7_clk_stop_out_c1b ), |
| 1591 | .stg2_mcu0_clk_stop_in_c2t ( stg2_mcu0_clk_stop_in_c2t ), |
| 1592 | .stg2_mcu1_clk_stop_in_c2t ( stg2_mcu1_clk_stop_in_c2t ), |
| 1593 | .stg2_mcu0_io_clk_stop_in_c2t ( stg2_mcu0_io_clk_stop_in_c2t ), |
| 1594 | // .stg2_mcu0_dr_clk_stop_in_c2t ( stg2_mcu0_dr_clk_stop_in_c2t ), |
| 1595 | // .stg2_mcu1_dr_clk_stop_in_c2t ( stg2_mcu1_dr_clk_stop_in_c2t ), |
| 1596 | .stg2_mcu1_io_clk_stop_in_c2t ( stg2_mcu1_io_clk_stop_in_c2t ), |
| 1597 | // .stg3_mcu0_dr_clk_stop_out_c2t ( stg3_mcu0_dr_clk_stop_out_c2t ), |
| 1598 | .stg3_mcu0_io_clk_stop_out_c2t ( stg3_mcu0_io_clk_stop_out_c2t ), |
| 1599 | // .stg3_mcu1_dr_clk_stop_out_c2t ( stg3_mcu1_dr_clk_stop_out_c2t ), |
| 1600 | .stg3_mcu1_io_clk_stop_out_c2t ( stg3_mcu1_io_clk_stop_out_c2t ), |
| 1601 | .stg3_mcu0_clk_stop_out_c2t ( stg3_mcu0_clk_stop_out_c2t ), |
| 1602 | .stg3_mcu1_clk_stop_out_c2t ( stg3_mcu1_clk_stop_out_c2t ), |
| 1603 | .stg3_ccx_clk_stop_in_c2b ( stg3_ccx_clk_stop_in_c2b ), |
| 1604 | .stg3_ccx_clk_stop_out_c2b ( stg3_ccx_clk_stop_out_c2b ), |
| 1605 | .stg3_cmp_io_sync_en_in_c2b ( stg3_cmp_io_sync_en_in_c2b ), |
| 1606 | .stg3_cmp_io_sync_en_in_c2t ( stg3_cmp_io_sync_en_in_c2t ), |
| 1607 | .stg3_cmp_io_sync_en_in_c3b ( stg3_cmp_io_sync_en_in_c3b ), |
| 1608 | .stg3_cmp_io_sync_en_in_c3t ( stg3_cmp_io_sync_en_in_c3t ), |
| 1609 | .stg3_cmp_io_sync_en_out_c2b ( stg3_cmp_io_sync_en_out_c2b ), |
| 1610 | .stg3_cmp_io_sync_en_out_c2t ( stg3_cmp_io_sync_en_out_c2t ), |
| 1611 | .stg3_db0_clk_stop_in_c3b ( stg3_db0_clk_stop_in_c3b ), |
| 1612 | .stg3_db0_clk_stop_out_c2b ( stg3_db0_clk_stop_out_c2b ), |
| 1613 | .stg3_dmu_io_clk_stop_in_c3b ( stg3_dmu_io_clk_stop_in_c3b ), |
| 1614 | .stg3_dmu_io_clk_stop_out_c2b ( stg3_dmu_io_clk_stop_out_c2b ), |
| 1615 | .stg3_dmu_peu_por_in_c3b ( stg3_dmu_peu_por_in_c3b ), |
| 1616 | .stg3_dmu_peu_por_out_c2b ( stg3_dmu_peu_por_out_c2b ), |
| 1617 | .stg3_dmu_peu_wmr_in_c3b ( stg3_dmu_peu_wmr_in_c3b ), |
| 1618 | .stg3_dmu_peu_wmr_out_c2b ( stg3_dmu_peu_wmr_out_c2b ), |
| 1619 | .stg3_dr_sync_en_in_c3t ( stg3_dr_sync_en_in_c3t ), |
| 1620 | .stg3_dr_sync_en_out_c2t ( stg3_dr_sync_en_out_c2t ), |
| 1621 | .stg3_io2x_sync_en_in_c2t ( stg3_io2x_sync_en_in_c2t ), |
| 1622 | .stg3_io_cmp_sync_en_in_c2b ( stg3_io_cmp_sync_en_in_c2b ), |
| 1623 | .stg3_io_cmp_sync_en_in_c2t ( stg3_io_cmp_sync_en_in_c2t ), |
| 1624 | .stg3_io_cmp_sync_en_in_c3b ( stg3_io_cmp_sync_en_in_c3b ), |
| 1625 | .stg3_io_cmp_sync_en_in_c3t ( stg3_io_cmp_sync_en_in_c3t ), |
| 1626 | .stg3_io_cmp_sync_en_out_c2b ( stg3_io_cmp_sync_en_out_c2b ), |
| 1627 | .stg3_io_cmp_sync_en_out_c2t ( stg3_io_cmp_sync_en_out_c2t ), |
| 1628 | .stg3_io_out_in_c3b ( stg3_io_out_in_c3b ), |
| 1629 | .stg3_io_out_in_c3t ( stg3_io_out_in_c3t ), |
| 1630 | .stg3_io_out_out_c2t ( stg3_io_out_out_c2t ), |
| 1631 | .stg3_io2x_sync_en_out_c2t (stg3_io2x_sync_en_out_c2t ), |
| 1632 | .stg3_l2_por_in_c2b ( stg3_l2_por_in_c2b ), |
| 1633 | .stg3_l2_por_in_c2t ( stg3_l2_por_in_c2t ), |
| 1634 | .stg3_l2_por_in_c3b ( stg3_l2_por_in_c3b ), |
| 1635 | .stg3_l2_por_in_c3t ( stg3_l2_por_in_c3t ), |
| 1636 | .stg3_l2_por_out_c2b ( stg3_l2_por_out_c2b ), |
| 1637 | .stg3_l2_por_out_c2t ( stg3_l2_por_out_c2t ), |
| 1638 | .stg3_l2_wmr_in_c2b ( stg3_l2_wmr_in_c2b ), |
| 1639 | .stg3_l2_wmr_in_c2t ( stg3_l2_wmr_in_c2t ), |
| 1640 | .stg3_l2_wmr_in_c3b ( stg3_l2_wmr_in_c3b ), |
| 1641 | .stg3_l2_wmr_in_c3t ( stg3_l2_wmr_in_c3t ), |
| 1642 | .stg3_l2_wmr_out_c2b ( stg3_l2_wmr_out_c2b ), |
| 1643 | .stg3_l2_wmr_out_c2t ( stg3_l2_wmr_out_c2t ), |
| 1644 | .stg3_l2b0_clk_stop_in_c3t ( stg3_l2b0_clk_stop_in_c3t ), |
| 1645 | .stg3_l2b0_clk_stop_out_c2t ( stg3_l2b0_clk_stop_out_c2t ), |
| 1646 | .stg3_l2b1_clk_stop_in_c3t ( stg3_l2b1_clk_stop_in_c3t ), |
| 1647 | .stg3_l2b1_clk_stop_out_c2t ( stg3_l2b1_clk_stop_out_c2t ), |
| 1648 | .stg3_l2b2_clk_stop_in_c3b ( stg3_l2b2_clk_stop_in_c3b ), |
| 1649 | .stg3_l2b2_clk_stop_out_c2b ( stg3_l2b2_clk_stop_out_c2b ), |
| 1650 | .stg3_l2b3_clk_stop_in_c3b ( stg3_l2b3_clk_stop_in_c3b ), |
| 1651 | .stg3_l2b3_clk_stop_out_c2b ( stg3_l2b3_clk_stop_out_c2b ), |
| 1652 | .stg3_l2d0_clk_stop_in_c3t ( stg3_l2d0_clk_stop_in_c3t ), |
| 1653 | .stg3_l2d0_clk_stop_out_c2t ( stg3_l2d0_clk_stop_out_c2t ), |
| 1654 | .stg3_l2d1_clk_stop_in_c3t ( stg3_l2d1_clk_stop_in_c3t ), |
| 1655 | .stg3_l2d1_clk_stop_out_c2t ( stg3_l2d1_clk_stop_out_c2t ), |
| 1656 | .stg3_l2d2_clk_stop_in_c3b ( stg3_l2d2_clk_stop_in_c3b ), |
| 1657 | .stg3_l2d2_clk_stop_out_c2b ( stg3_l2d2_clk_stop_out_c2b ), |
| 1658 | .stg3_l2d3_clk_stop_in_c3b ( stg3_l2d3_clk_stop_in_c3b ), |
| 1659 | .stg3_l2d3_clk_stop_out_c2b ( stg3_l2d3_clk_stop_out_c2b ), |
| 1660 | .stg3_l2t0_clk_stop_in_c3t ( stg3_l2t0_clk_stop_in_c3t ), |
| 1661 | .stg3_l2t0_clk_stop_out_c2t ( stg3_l2t0_clk_stop_out_c2t ), |
| 1662 | .stg3_l2t1_clk_stop_in_c2t ( stg3_l2t1_clk_stop_in_c2t ), |
| 1663 | .stg3_l2t1_clk_stop_out_c2t ( stg3_l2t1_clk_stop_out_c2t ), |
| 1664 | .stg3_l2t2_clk_stop_in_c3b ( stg3_l2t2_clk_stop_in_c3b ), |
| 1665 | .stg3_l2t2_clk_stop_out_c2b ( stg3_l2t2_clk_stop_out_c2b ), |
| 1666 | .stg3_l2t3_clk_stop_in_c2b ( stg3_l2t3_clk_stop_in_c2b ), |
| 1667 | .stg3_l2t3_clk_stop_out_c2b ( stg3_l2t3_clk_stop_out_c2b ), |
| 1668 | .stg3_l2t5_clk_stop_in_c2t ( stg3_l2t5_clk_stop_in_c2t ), |
| 1669 | .stg3_l2t5_clk_stop_out_c2t ( stg3_l2t5_clk_stop_out_c2t ), |
| 1670 | .stg3_l2t7_clk_stop_in_c2b ( stg3_l2t7_clk_stop_in_c2b ), |
| 1671 | .stg3_l2t7_clk_stop_out_c2b ( stg3_l2t7_clk_stop_out_c2b ), |
| 1672 | .stg3_mcu0_clk_stop_in_c3t ( stg3_mcu0_clk_stop_in_c3t ), |
| 1673 | // .stg3_mcu0_dr_clk_stop_in_c3t ( stg3_mcu0_dr_clk_stop_in_c3t ), |
| 1674 | .stg3_mcu0_io_clk_stop_in_c3t ( stg3_mcu0_io_clk_stop_in_c3t ), |
| 1675 | .stg3_mcu1_clk_stop_in_c3t ( stg3_mcu1_clk_stop_in_c3t ), |
| 1676 | // .stg3_mcu1_dr_clk_stop_in_c3t ( stg3_mcu1_dr_clk_stop_in_c3t ), |
| 1677 | .stg3_mcu1_io_clk_stop_in_c3t ( stg3_mcu1_io_clk_stop_in_c3t ), |
| 1678 | .stg3_mio_clk_stop_in_c2t ( stg3_mio_clk_stop_in_c2t ), |
| 1679 | .stg3_mio_clk_stop_in_c3t ( stg3_mio_clk_stop_in_c3t ), |
| 1680 | .stg3_mio_clk_stop_out_c2t ( stg3_mio_clk_stop_out_c2t ), |
| 1681 | .stg3_mio_io2x_sync_en_in_c3t ( stg3_mio_io2x_sync_en_in_c3t ), |
| 1682 | .stg3_mio_io2x_sync_en_out_c2t ( stg3_mio_io2x_sync_en_out_c2t ), |
| 1683 | .stg3_ncu_clk_stop_in_c3b ( stg3_ncu_clk_stop_in_c3b ), |
| 1684 | .stg3_ncu_clk_stop_out_c2b ( stg3_ncu_clk_stop_out_c2b ), |
| 1685 | .stg3_ncu_io_clk_stop_in_c3b ( stg3_ncu_io_clk_stop_in_c3b ), |
| 1686 | .stg3_ncu_io_clk_stop_out_c2b ( stg3_ncu_io_clk_stop_out_c2b ), |
| 1687 | .stg3_io_out_out_c2b ( stg3_io_out_out_c2b ), |
| 1688 | .stg3_peu_io_clk_stop_in_c3b ( stg3_peu_io_clk_stop_in_c3b ), |
| 1689 | .stg3_peu_io_clk_stop_out_c2b ( stg3_peu_io_clk_stop_out_c2b ), |
| 1690 | .stg3_sii_clk_stop_in_c3b ( stg3_sii_clk_stop_in_c3b ), |
| 1691 | .stg3_sii_clk_stop_out_c2b ( stg3_sii_clk_stop_out_c2b ), |
| 1692 | .stg3_sii_io_clk_stop_in_c3b ( stg3_sii_io_clk_stop_in_c3b ), |
| 1693 | .stg3_sii_io_clk_stop_out_c2b ( stg3_sii_io_clk_stop_out_c2b ), |
| 1694 | .stg3_spc0_clk_stop_in_c3t ( stg3_spc0_clk_stop_in_c3t ), |
| 1695 | .stg3_spc0_clk_stop_out_c2t ( stg3_spc0_clk_stop_out_c2t ), |
| 1696 | .stg3_spc1_clk_stop_in_c2t ( stg3_spc1_clk_stop_in_c2t ), |
| 1697 | .stg3_spc1_clk_stop_out_c2t ( stg3_spc1_clk_stop_out_c2t ), |
| 1698 | .stg3_spc2_clk_stop_in_c3b ( stg3_spc2_clk_stop_in_c3b ), |
| 1699 | .stg3_spc2_clk_stop_out_c2b ( stg3_spc2_clk_stop_out_c2b ), |
| 1700 | .stg3_spc3_clk_stop_in_c2b ( stg3_spc3_clk_stop_in_c2b ), |
| 1701 | .stg3_spc3_clk_stop_out_c2b ( stg3_spc3_clk_stop_out_c2b ), |
| 1702 | .stg3_spc5_clk_stop_in_c2t ( stg3_spc5_clk_stop_in_c2t ), |
| 1703 | .stg3_spc5_clk_stop_out_c2t ( stg3_spc5_clk_stop_out_c2t ), |
| 1704 | .stg3_spc7_clk_stop_in_c2b ( stg3_spc7_clk_stop_in_c2b ), |
| 1705 | .stg3_spc7_clk_stop_out_c2b ( stg3_spc7_clk_stop_out_c2b ), |
| 1706 | .stg4_cmp_io_sync_en_in_c3b ( stg4_cmp_io_sync_en_in_c3b ), |
| 1707 | .stg4_cmp_io_sync_en_in_c3t ( stg4_cmp_io_sync_en_in_c3t ), |
| 1708 | .stg4_cmp_io_sync_en_out_c3b ( stg4_cmp_io_sync_en_out_c3b ), |
| 1709 | .stg4_cmp_io_sync_en_out_c3t ( stg4_cmp_io_sync_en_out_c3t ), |
| 1710 | .stg4_db0_clk_stop_c3b ( stg4_db0_clk_stop_c3b ), |
| 1711 | .stg4_db0_clk_stop_out_c3b ( stg4_db0_clk_stop_out_c3b ), |
| 1712 | .stg4_dmu_io_clk_stop_in_c3b ( stg4_dmu_io_clk_stop_in_c3b ), |
| 1713 | .stg4_dmu_io_clk_stop_out_c3b ( stg4_dmu_io_clk_stop_out_c3b ), |
| 1714 | .stg4_dmu_peu_por_in_c3b ( stg4_dmu_peu_por_in_c3b ), |
| 1715 | .stg4_dmu_peu_por_out_c3b ( stg4_dmu_peu_por_out_c3b ), |
| 1716 | .stg4_dmu_peu_wmr_in_c3b ( stg4_dmu_peu_wmr_in_c3b ), |
| 1717 | .stg4_dmu_peu_wmr_out_c3b ( stg4_dmu_peu_wmr_out_c3b ), |
| 1718 | .stg4_dr_sync_en_in_c3t ( stg4_dr_sync_en_in_c3t ), |
| 1719 | .stg4_dr_sync_en_out_c3t ( stg4_dr_sync_en_out_c3t ), |
| 1720 | .stg4_io2x_sync_en_c3t ( stg4_io2x_sync_en_c3t ), |
| 1721 | .stg4_io2x_sync_en_in_c3t ( stg4_io2x_sync_en_in_c3t ), |
| 1722 | // .stg4_io2x_sync_en_out_c2b ( stg4_io2x_sync_en_out_c2b ), |
| 1723 | .stg4_io_cmp_sync_en_in_c3b ( stg4_io_cmp_sync_en_in_c3b ), |
| 1724 | .stg4_io_cmp_sync_en_in_c3t ( stg4_io_cmp_sync_en_in_c3t ), |
| 1725 | .stg4_io_cmp_sync_en_out_c3b ( stg4_io_cmp_sync_en_out_c3b ), |
| 1726 | .stg4_io_cmp_sync_en_out_c3t ( stg4_io_cmp_sync_en_out_c3t ), |
| 1727 | .stg4_io_out_in_c3b ( stg4_io_out_in_c3b ), |
| 1728 | .stg4_io_out_in_c3t ( stg4_io_out_in_c3t ), |
| 1729 | .stg4_io_out_out_c3b ( stg4_io_out_out_c3b ), |
| 1730 | .stg4_io_out_out_c3t ( stg4_io_out_out_c3t ), |
| 1731 | .stg4_l2_por_in_c3b ( stg4_l2_por_in_c3b ), |
| 1732 | .stg4_l2_por_in_c3t ( stg4_l2_por_in_c3t ), |
| 1733 | .stg4_l2_por_out_c3b ( stg4_l2_por_out_c3b ), |
| 1734 | .stg4_l2_por_out_c3t ( stg4_l2_por_out_c3t ), |
| 1735 | .stg4_l2_wmr_in_c3b ( stg4_l2_wmr_in_c3b ), |
| 1736 | .stg4_l2_wmr_in_c3t ( stg4_l2_wmr_in_c3t ), |
| 1737 | .stg4_l2_wmr_out_c3b ( stg4_l2_wmr_out_c3b ), |
| 1738 | .stg4_l2_wmr_out_c3t ( stg4_l2_wmr_out_c3t ), |
| 1739 | .stg4_l2b0_clk_stop_in_c3t ( stg4_l2b0_clk_stop_in_c3t ), |
| 1740 | .stg4_l2b0_clk_stop_out_c3t ( stg4_l2b0_clk_stop_out_c3t ), |
| 1741 | .stg4_l2b1_clk_stop_in_c3t ( stg4_l2b1_clk_stop_in_c3t ), |
| 1742 | .stg4_l2b1_clk_stop_out_c3t ( stg4_l2b1_clk_stop_out_c3t ), |
| 1743 | .stg4_l2b2_clk_stop_in_c3b ( stg4_l2b2_clk_stop_in_c3b ), |
| 1744 | .stg4_l2b2_clk_stop_out_c3b ( stg4_l2b2_clk_stop_out_c3b ), |
| 1745 | .stg4_l2b3_clk_stop_in_c3b ( stg4_l2b3_clk_stop_in_c3b ), |
| 1746 | .stg4_l2b3_clk_stop_out_c3b ( stg4_l2b3_clk_stop_out_c3b ), |
| 1747 | .stg4_l2d0_clk_stop_in_c3t ( stg4_l2d0_clk_stop_in_c3t ), |
| 1748 | .stg4_l2d0_clk_stop_out_c3t ( stg4_l2d0_clk_stop_out_c3t ), |
| 1749 | .stg4_l2d1_clk_stop_in_c3t ( stg4_l2d1_clk_stop_in_c3t ), |
| 1750 | .stg4_l2d1_clk_stop_out_c3t ( stg4_l2d1_clk_stop_out_c3t ), |
| 1751 | .stg4_l2d2_clk_stop_in_c3b ( stg4_l2d2_clk_stop_in_c3b ), |
| 1752 | .stg4_l2d2_clk_stop_out_c3b ( stg4_l2d2_clk_stop_out_c3b ), |
| 1753 | .stg4_l2d3_clk_stop_in_c3b ( stg4_l2d3_clk_stop_in_c3b ), |
| 1754 | .stg4_l2d3_clk_stop_out_c3b ( stg4_l2d3_clk_stop_out_c3b ), |
| 1755 | .stg4_l2t0_clk_stop_in_c3t ( stg4_l2t0_clk_stop_in_c3t ), |
| 1756 | .stg4_l2t0_clk_stop_out_c3t ( stg4_l2t0_clk_stop_out_c3t ), |
| 1757 | .stg4_l2t2_clk_stop_in_c3b ( stg4_l2t2_clk_stop_in_c3b ), |
| 1758 | .stg4_l2t2_clk_stop_out_c3b ( stg4_l2t2_clk_stop_out_c3b ), |
| 1759 | .stg4_mcu0_clk_stop_in_c3t ( stg4_mcu0_clk_stop_in_c3t ), |
| 1760 | .stg4_mcu0_clk_stop_out_c3t ( stg4_mcu0_clk_stop_out_c3t ), |
| 1761 | // .stg4_mcu0_dr_clk_stop_in_c3t ( stg4_mcu0_dr_clk_stop_in_c3t ), |
| 1762 | // .stg4_mcu0_dr_clk_stop_out_c3t ( stg4_mcu0_dr_clk_stop_out_c3t ), |
| 1763 | .stg4_mcu0_io_clk_stop_in_c3t ( stg4_mcu0_io_clk_stop_in_c3t ), |
| 1764 | .stg4_mcu0_io_clk_stop_out_c3t ( stg4_mcu0_io_clk_stop_out_c3t ), |
| 1765 | .stg4_mcu1_clk_stop_in_c3t ( stg4_mcu1_clk_stop_in_c3t ), |
| 1766 | .stg4_mcu1_clk_stop_out_c3t ( stg4_mcu1_clk_stop_out_c3t ), |
| 1767 | // .stg4_mcu1_dr_clk_stop_in_c3t ( stg4_mcu1_dr_clk_stop_in_c3t ), |
| 1768 | // .stg4_mcu1_dr_clk_stop_out_c3t ( stg4_mcu1_dr_clk_stop_out_c3t ), |
| 1769 | .stg4_mcu1_io_clk_stop_in_c3t ( stg4_mcu1_io_clk_stop_in_c3t ), |
| 1770 | .stg4_mcu1_io_clk_stop_out_c3t ( stg4_mcu1_io_clk_stop_out_c3t ), |
| 1771 | .stg4_mio_clk_stop_in_c3t ( stg4_mio_clk_stop_in_c3t ), |
| 1772 | .stg4_mio_clk_stop_out_c3t ( stg4_mio_clk_stop_out_c3t ), |
| 1773 | .stg4_mio_io2x_sync_en_out_c3t ( stg4_mio_io2x_sync_en_out_c3t ), |
| 1774 | .stg4_ncu_clk_stop_in_c3b ( stg4_ncu_clk_stop_in_c3b ), |
| 1775 | .stg4_ncu_clk_stop_out_c3b ( stg4_ncu_clk_stop_out_c3b ), |
| 1776 | .stg4_ncu_io_clk_stop_c3b ( stg4_ncu_io_clk_stop_c3b ), |
| 1777 | .stg4_ncu_io_clk_stop_out_c3b ( stg4_ncu_io_clk_stop_out_c3b ), |
| 1778 | .stg4_peu_io_clk_stop_in_c3b ( stg4_peu_io_clk_stop_in_c3b ), |
| 1779 | .stg4_peu_io_clk_stop_out_c3b ( stg4_peu_io_clk_stop_out_c3b ), |
| 1780 | .stg4_sii_clk_stop_in_c3b ( stg4_sii_clk_stop_in_c3b ), |
| 1781 | .stg4_sii_clk_stop_out_c3b ( stg4_sii_clk_stop_out_c3b ), |
| 1782 | .stg4_sii_io_clk_stop_in_c3b ( stg4_sii_io_clk_stop_in_c3b ), |
| 1783 | .stg4_sii_io_clk_stop_out_c3b ( stg4_sii_io_clk_stop_out_c3b ), |
| 1784 | .stg4_spc0_clk_stop_in_c3t ( stg4_spc0_clk_stop_in_c3t ), |
| 1785 | .stg4_spc0_clk_stop_out_c3t ( stg4_spc0_clk_stop_out_c3t ), |
| 1786 | // .stg4_spc1_clk_stop_out_c2b ( stg4_spc1_clk_stop_out_c2b ), |
| 1787 | .stg4_spc2_clk_stop_in_c3b ( stg4_spc2_clk_stop_in_c3b ), |
| 1788 | .stg4_spc2_clk_stop_out_c3b ( stg4_spc2_clk_stop_out_c3b ), |
| 1789 | // .stg4_spc5_clk_stop_out_c2b ( stg4_spc5_clk_stop_out_c2b ), |
| 1790 | .tcu_ccu_clk_stop ( tcu_ccu_clk_stop ), |
| 1791 | .tcu_ccu_io_clk_stop ( tcu_ccu_io_clk_stop ), |
| 1792 | .tcu_ccx_clk_stop ( tcu_ccx_clk_stop ), |
| 1793 | .tcu_db0_clk_stop ( tcu_db0_clk_stop ), |
| 1794 | .tcu_db1_clk_stop ( tcu_db1_clk_stop ), |
| 1795 | .tcu_dmu_io_clk_stop ( tcu_dmu_io_clk_stop ), |
| 1796 | .tcu_efu_clk_stop ( tcu_efu_clk_stop ), |
| 1797 | .tcu_efu_io_clk_stop ( tcu_efu_io_clk_stop ), |
| 1798 | .tcu_l2b0_clk_stop ( tcu_l2b0_clk_stop ), |
| 1799 | .tcu_l2b1_clk_stop ( tcu_l2b1_clk_stop ), |
| 1800 | .tcu_l2b2_clk_stop ( tcu_l2b2_clk_stop ), |
| 1801 | .tcu_l2b3_clk_stop ( tcu_l2b3_clk_stop ), |
| 1802 | .tcu_l2b4_clk_stop ( tcu_l2b4_clk_stop ), |
| 1803 | .tcu_l2b5_clk_stop ( tcu_l2b5_clk_stop ), |
| 1804 | .tcu_l2b6_clk_stop ( tcu_l2b6_clk_stop ), |
| 1805 | .tcu_l2b7_clk_stop ( tcu_l2b7_clk_stop ), |
| 1806 | .tcu_l2d0_clk_stop ( tcu_l2d0_clk_stop ), |
| 1807 | .tcu_l2d1_clk_stop ( tcu_l2d1_clk_stop ), |
| 1808 | .tcu_l2d2_clk_stop ( tcu_l2d2_clk_stop ), |
| 1809 | .tcu_l2d3_clk_stop ( tcu_l2d3_clk_stop ), |
| 1810 | .tcu_l2d4_clk_stop ( tcu_l2d4_clk_stop ), |
| 1811 | .tcu_l2d5_clk_stop ( tcu_l2d5_clk_stop ), |
| 1812 | .tcu_l2d7_clk_stop ( tcu_l2d7_clk_stop ), |
| 1813 | .tcu_l2d6_clk_stop ( tcu_l2d6_clk_stop ), |
| 1814 | .tcu_l2t0_clk_stop ( tcu_l2t0_clk_stop ), |
| 1815 | .tcu_l2t1_clk_stop ( tcu_l2t1_clk_stop ), |
| 1816 | .tcu_l2t2_clk_stop ( tcu_l2t2_clk_stop ), |
| 1817 | .tcu_l2t3_clk_stop ( tcu_l2t3_clk_stop ), |
| 1818 | .tcu_l2t4_clk_stop ( tcu_l2t4_clk_stop ), |
| 1819 | .tcu_l2t5_clk_stop ( tcu_l2t5_clk_stop ), |
| 1820 | .tcu_l2t6_clk_stop ( tcu_l2t6_clk_stop ), |
| 1821 | .tcu_l2t7_clk_stop ( tcu_l2t7_clk_stop ), |
| 1822 | .tcu_mac_io_clk_stop ( tcu_mac_io_clk_stop ), |
| 1823 | .tcu_mcu0_clk_stop ( tcu_mcu0_clk_stop ), |
| 1824 | .tcu_mcu0_dr_clk_stop ( tcu_mcu0_dr_clk_stop ), |
| 1825 | .tcu_mcu0_io_clk_stop ( tcu_mcu0_io_clk_stop ), |
| 1826 | .tcu_mcu1_clk_stop ( tcu_mcu1_clk_stop ), |
| 1827 | .tcu_mcu1_dr_clk_stop ( tcu_mcu1_dr_clk_stop ), |
| 1828 | .tcu_mcu1_io_clk_stop ( tcu_mcu1_io_clk_stop ), |
| 1829 | .tcu_mcu2_clk_stop ( tcu_mcu2_clk_stop ), |
| 1830 | .tcu_mcu2_dr_clk_stop ( tcu_mcu2_dr_clk_stop ), |
| 1831 | .tcu_mcu2_io_clk_stop ( tcu_mcu2_io_clk_stop ), |
| 1832 | .tcu_mcu3_clk_stop ( tcu_mcu3_clk_stop ), |
| 1833 | .tcu_mcu3_dr_clk_stop ( tcu_mcu3_dr_clk_stop ), |
| 1834 | .tcu_mcu3_io_clk_stop ( tcu_mcu3_io_clk_stop ), |
| 1835 | .tcu_mio_clk_stop ( tcu_mio_clk_stop ), |
| 1836 | .tcu_ncu_clk_stop ( tcu_ncu_clk_stop ), |
| 1837 | .tcu_ncu_io_clk_stop ( tcu_ncu_io_clk_stop ), |
| 1838 | .tcu_peu_io_clk_stop ( tcu_peu_io_clk_stop ), |
| 1839 | .tcu_rdp_io_clk_stop ( tcu_rdp_io_clk_stop ), |
| 1840 | .tcu_rst_clk_stop ( tcu_rst_clk_stop ), |
| 1841 | .tcu_rst_io_clk_stop ( tcu_rst_io_clk_stop ), |
| 1842 | .tcu_rtx_io_clk_stop ( tcu_rtx_io_clk_stop ), |
| 1843 | .tcu_sii_clk_stop ( tcu_sii_clk_stop ), |
| 1844 | .tcu_sii_io_clk_stop ( tcu_sii_io_clk_stop ), |
| 1845 | .tcu_sio_clk_stop ( tcu_sio_clk_stop ), |
| 1846 | .tcu_sio_io_clk_stop ( tcu_sio_io_clk_stop ), |
| 1847 | .tcu_spc0_clk_stop ( tcu_spc0_clk_stop ), |
| 1848 | .tcu_spc1_clk_stop ( tcu_spc1_clk_stop ), |
| 1849 | .tcu_spc2_clk_stop ( tcu_spc2_clk_stop ), |
| 1850 | .tcu_spc3_clk_stop ( tcu_spc3_clk_stop ), |
| 1851 | .tcu_spc4_clk_stop ( tcu_spc4_clk_stop ), |
| 1852 | .tcu_spc5_clk_stop ( tcu_spc5_clk_stop ), |
| 1853 | .tcu_spc6_clk_stop ( tcu_spc6_clk_stop ), |
| 1854 | .tcu_spc7_clk_stop ( tcu_spc7_clk_stop ), |
| 1855 | .tcu_tds_io_clk_stop ( tcu_tds_io_clk_stop ) |
| 1856 | ); |
| 1857 | |
| 1858 | |
| 1859 | endmodule |
| 1860 | |
| 1861 | |
| 1862 | |
| 1863 | |
| 1864 | // ************************************************************************ |
| 1865 | // module n2_clk_gl_dr_tree |
| 1866 | // ************************************************************************ |
| 1867 | |
| 1868 | module n2_clk_gl_dr_tree ( pll_dr_clk, dr_gclk_stg_tcu, dr_gclk_fsr7_stg, |
| 1869 | dr_gclk_c4_mcu0 , dr_gclk_c4_mcu1 , dr_gclk_c0_mcu2 , dr_gclk_c0_mcu3 , |
| 1870 | dr_gclk_c4_fsr0_0 , dr_gclk_c4_fsr0_1 , dr_gclk_c4_fsr0_2 , |
| 1871 | dr_gclk_c4_fsr1_0 , dr_gclk_c4_fsr1_1 , dr_gclk_c4_fsr1_2 , |
| 1872 | dr_gclk_c4_fsr2_0 , dr_gclk_c4_fsr2_1 , dr_gclk_c4_fsr2_2 , |
| 1873 | dr_gclk_c4_fsr3_0 , dr_gclk_c4_fsr3_1 , dr_gclk_c4_fsr3_2 , |
| 1874 | dr_gclk_c0_fsr4_0 , dr_gclk_c0_fsr4_1 , dr_gclk_c0_fsr4_2 , |
| 1875 | dr_gclk_c0_fsr5_0 , dr_gclk_c0_fsr5_1 , dr_gclk_c0_fsr5_2 , |
| 1876 | dr_gclk_c0_fsr6_0 , dr_gclk_c0_fsr6_1 , dr_gclk_c0_fsr6_2 , |
| 1877 | dr_gclk_c2_fsr7_0 , dr_gclk_c2_fsr7_1 , dr_gclk_c2_fsr7_2 |
| 1878 | ); |
| 1879 | |
| 1880 | input pll_dr_clk ; |
| 1881 | |
| 1882 | output dr_gclk_stg_tcu; |
| 1883 | output dr_gclk_fsr7_stg; |
| 1884 | output dr_gclk_c4_mcu0 ; |
| 1885 | output dr_gclk_c4_mcu1 ; |
| 1886 | output dr_gclk_c0_mcu2 ; |
| 1887 | output dr_gclk_c0_mcu3 ; |
| 1888 | output dr_gclk_c4_fsr0_0; |
| 1889 | output dr_gclk_c4_fsr0_1; |
| 1890 | output dr_gclk_c4_fsr0_2; |
| 1891 | output dr_gclk_c4_fsr1_0; |
| 1892 | output dr_gclk_c4_fsr1_1; |
| 1893 | output dr_gclk_c4_fsr1_2; |
| 1894 | output dr_gclk_c4_fsr2_0; |
| 1895 | output dr_gclk_c4_fsr2_1; |
| 1896 | output dr_gclk_c4_fsr2_2; |
| 1897 | output dr_gclk_c4_fsr3_0; |
| 1898 | output dr_gclk_c4_fsr3_1; |
| 1899 | output dr_gclk_c4_fsr3_2; |
| 1900 | output dr_gclk_c0_fsr4_0; |
| 1901 | output dr_gclk_c0_fsr4_1; |
| 1902 | output dr_gclk_c0_fsr4_2; |
| 1903 | output dr_gclk_c0_fsr5_0; |
| 1904 | output dr_gclk_c0_fsr5_1; |
| 1905 | output dr_gclk_c0_fsr5_2; |
| 1906 | output dr_gclk_c0_fsr6_0; |
| 1907 | output dr_gclk_c0_fsr6_1; |
| 1908 | output dr_gclk_c0_fsr6_2; |
| 1909 | output dr_gclk_c2_fsr7_0; |
| 1910 | output dr_gclk_c2_fsr7_1; |
| 1911 | output dr_gclk_c2_fsr7_2; |
| 1912 | |
| 1913 | assign dr_gclk_stg_tcu = pll_dr_clk; |
| 1914 | assign dr_gclk_fsr7_stg = pll_dr_clk; |
| 1915 | assign dr_gclk_c4_mcu0 = pll_dr_clk ; |
| 1916 | assign dr_gclk_c4_mcu1 = pll_dr_clk ; |
| 1917 | assign dr_gclk_c0_mcu2 = pll_dr_clk ; |
| 1918 | assign dr_gclk_c0_mcu3 = pll_dr_clk ; |
| 1919 | assign dr_gclk_c4_fsr0_0 = pll_dr_clk; |
| 1920 | assign dr_gclk_c4_fsr0_1 = pll_dr_clk; |
| 1921 | assign dr_gclk_c4_fsr0_2 = pll_dr_clk; |
| 1922 | assign dr_gclk_c4_fsr1_0 = pll_dr_clk; |
| 1923 | assign dr_gclk_c4_fsr1_1 = pll_dr_clk; |
| 1924 | assign dr_gclk_c4_fsr1_2 = pll_dr_clk; |
| 1925 | assign dr_gclk_c4_fsr2_0 = pll_dr_clk; |
| 1926 | assign dr_gclk_c4_fsr2_1 = pll_dr_clk; |
| 1927 | assign dr_gclk_c4_fsr2_2 = pll_dr_clk; |
| 1928 | assign dr_gclk_c4_fsr3_0 = pll_dr_clk; |
| 1929 | assign dr_gclk_c4_fsr3_1 = pll_dr_clk; |
| 1930 | assign dr_gclk_c4_fsr3_2 = pll_dr_clk; |
| 1931 | assign dr_gclk_c0_fsr4_0 = pll_dr_clk; |
| 1932 | assign dr_gclk_c0_fsr4_1 = pll_dr_clk; |
| 1933 | assign dr_gclk_c0_fsr4_2 = pll_dr_clk; |
| 1934 | assign dr_gclk_c0_fsr5_0 = pll_dr_clk; |
| 1935 | assign dr_gclk_c0_fsr5_1 = pll_dr_clk; |
| 1936 | assign dr_gclk_c0_fsr5_2 = pll_dr_clk; |
| 1937 | assign dr_gclk_c0_fsr6_0 = pll_dr_clk; |
| 1938 | assign dr_gclk_c0_fsr6_1 = pll_dr_clk; |
| 1939 | assign dr_gclk_c0_fsr6_2 = pll_dr_clk; |
| 1940 | assign dr_gclk_c2_fsr7_0 = pll_dr_clk; |
| 1941 | assign dr_gclk_c2_fsr7_1 = pll_dr_clk; |
| 1942 | assign dr_gclk_c2_fsr7_2 = pll_dr_clk; |
| 1943 | |
| 1944 | endmodule |
| 1945 | |
| 1946 | |
| 1947 | // ************************************************************************ |
| 1948 | // module n2_clk_gl_cmp_tree |
| 1949 | // ************************************************************************ |
| 1950 | |
| 1951 | module n2_clk_gl_cmp_tree ( |
| 1952 | cmp_gclk_c1_ccu , cmp_gclk_c2_ccx_left , cmp_gclk_c2_ccx_right , |
| 1953 | cmp_gclk_c3_db0 , cmp_gclk_c1_db1 , cmp_gclk_c3_dmu , |
| 1954 | cmp_gclk_c1_efu , cmp_gclk_c3_l2b0 , cmp_gclk_c3_l2b1 , |
| 1955 | cmp_gclk_c3_l2b2 , cmp_gclk_c3_l2b3 , cmp_gclk_c1_l2b4 , |
| 1956 | cmp_gclk_c1_l2b5 , cmp_gclk_c1_l2b6 , cmp_gclk_c1_l2b7 , |
| 1957 | cmp_gclk_c3_l2d0 , cmp_gclk_c3_l2d1 , cmp_gclk_c3_l2d2 , |
| 1958 | cmp_gclk_c3_l2d3 , cmp_gclk_c1_l2d4 , cmp_gclk_c1_l2d5 , |
| 1959 | cmp_gclk_c1_l2d6 , cmp_gclk_c1_l2d7 , cmp_gclk_c3_l2t0 , |
| 1960 | cmp_gclk_c3_l2t2 , cmp_gclk_c1_l2t4 , cmp_gclk_c1_l2t6 , |
| 1961 | cmp_gclk_c2_l2t1 , cmp_gclk_c2_l2t3 , cmp_gclk_c2_l2t5 , |
| 1962 | cmp_gclk_c2_l2t7 , cmp_gclk_c4_mcu0 , cmp_gclk_c4_mcu1 , |
| 1963 | cmp_gclk_c0_mcu2 , cmp_gclk_c0_mcu3 , |
| 1964 | cmp_gclk_c1_mio , cmp_gclk_c3_mio , cmp_gclk_c2_mio_left , |
| 1965 | cmp_gclk_c2_mio_right , cmp_gclk_c3_ncu , cmp_gclk_c3_peu , |
| 1966 | // cmp_gclk_c1_rst , |
| 1967 | cmp_gclk_c3_sii , cmp_gclk_c1_sio , |
| 1968 | cmp_gclk_c3_spc0 , cmp_gclk_c3_spc2 , cmp_gclk_c1_spc4 , |
| 1969 | cmp_gclk_c1_spc6 , cmp_gclk_c2_spc1 , cmp_gclk_c2_spc3 , |
| 1970 | cmp_gclk_c2_spc5 , cmp_gclk_c2_spc7 , cmp_gclk_c1_tcu , |
| 1971 | cmp_gclk_c1_mac , cmp_gclk_c0_rdp , cmp_gclk_c0_rtx , |
| 1972 | cmp_gclk_c0_tds , cmp_gclk_c3_rng, |
| 1973 | pll_cmp_clk ); |
| 1974 | |
| 1975 | output cmp_gclk_c3_rng ; |
| 1976 | output cmp_gclk_c1_ccu ; |
| 1977 | output cmp_gclk_c2_ccx_left ; |
| 1978 | output cmp_gclk_c2_ccx_right ; |
| 1979 | output cmp_gclk_c3_db0 ; |
| 1980 | output cmp_gclk_c1_db1 ; |
| 1981 | output cmp_gclk_c3_dmu ; |
| 1982 | output cmp_gclk_c1_efu ; |
| 1983 | output cmp_gclk_c3_l2b0 ; |
| 1984 | output cmp_gclk_c3_l2b1 ; |
| 1985 | output cmp_gclk_c3_l2b2 ; |
| 1986 | output cmp_gclk_c3_l2b3 ; |
| 1987 | output cmp_gclk_c1_l2b4 ; |
| 1988 | output cmp_gclk_c1_l2b5 ; |
| 1989 | output cmp_gclk_c1_l2b6 ; |
| 1990 | output cmp_gclk_c1_l2b7 ; |
| 1991 | output cmp_gclk_c3_l2d0 ; |
| 1992 | output cmp_gclk_c3_l2d1 ; |
| 1993 | output cmp_gclk_c3_l2d2 ; |
| 1994 | output cmp_gclk_c3_l2d3 ; |
| 1995 | output cmp_gclk_c1_l2d4 ; |
| 1996 | output cmp_gclk_c1_l2d5 ; |
| 1997 | output cmp_gclk_c1_l2d6 ; |
| 1998 | output cmp_gclk_c1_l2d7 ; |
| 1999 | output cmp_gclk_c3_l2t0 ; |
| 2000 | output cmp_gclk_c3_l2t2 ; |
| 2001 | output cmp_gclk_c1_l2t4 ; |
| 2002 | output cmp_gclk_c1_l2t6 ; |
| 2003 | output cmp_gclk_c2_l2t1 ; |
| 2004 | output cmp_gclk_c2_l2t3 ; |
| 2005 | output cmp_gclk_c2_l2t5 ; |
| 2006 | output cmp_gclk_c2_l2t7 ; |
| 2007 | output cmp_gclk_c4_mcu0 ; |
| 2008 | output cmp_gclk_c4_mcu1 ; |
| 2009 | output cmp_gclk_c0_mcu2 ; |
| 2010 | output cmp_gclk_c0_mcu3 ; |
| 2011 | output cmp_gclk_c1_mio ; |
| 2012 | output cmp_gclk_c3_mio ; |
| 2013 | output cmp_gclk_c2_mio_left ; |
| 2014 | output cmp_gclk_c2_mio_right ; |
| 2015 | output cmp_gclk_c3_ncu ; |
| 2016 | output cmp_gclk_c3_peu ; |
| 2017 | // output cmp_gclk_c1_rst ; |
| 2018 | output cmp_gclk_c3_sii ; |
| 2019 | output cmp_gclk_c1_sio ; |
| 2020 | output cmp_gclk_c3_spc0 ; |
| 2021 | output cmp_gclk_c3_spc2 ; |
| 2022 | output cmp_gclk_c1_spc4 ; |
| 2023 | output cmp_gclk_c1_spc6 ; |
| 2024 | output cmp_gclk_c2_spc1 ; |
| 2025 | output cmp_gclk_c2_spc3 ; |
| 2026 | output cmp_gclk_c2_spc5 ; |
| 2027 | output cmp_gclk_c2_spc7 ; |
| 2028 | output cmp_gclk_c1_tcu ; |
| 2029 | output cmp_gclk_c1_mac ; |
| 2030 | output cmp_gclk_c0_rdp ; |
| 2031 | output cmp_gclk_c0_rtx ; |
| 2032 | output cmp_gclk_c0_tds ; |
| 2033 | input pll_cmp_clk ; |
| 2034 | |
| 2035 | |
| 2036 | // new clock names are here to stay |
| 2037 | assign cmp_gclk_c3_rng = pll_cmp_clk ; |
| 2038 | assign cmp_gclk_c1_ccu = pll_cmp_clk ; |
| 2039 | assign cmp_gclk_c2_ccx_left = pll_cmp_clk ; |
| 2040 | assign cmp_gclk_c2_ccx_right = pll_cmp_clk ; |
| 2041 | assign cmp_gclk_c3_db0 = pll_cmp_clk ; |
| 2042 | assign cmp_gclk_c1_db1 = pll_cmp_clk ; |
| 2043 | assign cmp_gclk_c3_dmu = pll_cmp_clk ; |
| 2044 | assign cmp_gclk_c1_efu = pll_cmp_clk ; |
| 2045 | assign cmp_gclk_c3_l2b0 = pll_cmp_clk ; |
| 2046 | assign cmp_gclk_c3_l2b1 = pll_cmp_clk ; |
| 2047 | assign cmp_gclk_c3_l2b2 = pll_cmp_clk ; |
| 2048 | assign cmp_gclk_c3_l2b3 = pll_cmp_clk ; |
| 2049 | assign cmp_gclk_c1_l2b4 = pll_cmp_clk ; |
| 2050 | assign cmp_gclk_c1_l2b5 = pll_cmp_clk ; |
| 2051 | assign cmp_gclk_c1_l2b6 = pll_cmp_clk ; |
| 2052 | assign cmp_gclk_c1_l2b7 = pll_cmp_clk ; |
| 2053 | assign cmp_gclk_c3_l2d0 = pll_cmp_clk ; |
| 2054 | assign cmp_gclk_c3_l2d1 = pll_cmp_clk ; |
| 2055 | assign cmp_gclk_c3_l2d2 = pll_cmp_clk ; |
| 2056 | assign cmp_gclk_c3_l2d3 = pll_cmp_clk ; |
| 2057 | assign cmp_gclk_c1_l2d4 = pll_cmp_clk ; |
| 2058 | assign cmp_gclk_c1_l2d5 = pll_cmp_clk ; |
| 2059 | assign cmp_gclk_c1_l2d6 = pll_cmp_clk ; |
| 2060 | assign cmp_gclk_c1_l2d7 = pll_cmp_clk ; |
| 2061 | assign cmp_gclk_c3_l2t0 = pll_cmp_clk ; |
| 2062 | assign cmp_gclk_c3_l2t2 = pll_cmp_clk ; |
| 2063 | assign cmp_gclk_c1_l2t4 = pll_cmp_clk ; |
| 2064 | assign cmp_gclk_c1_l2t6 = pll_cmp_clk ; |
| 2065 | assign cmp_gclk_c2_l2t1 = pll_cmp_clk ; |
| 2066 | assign cmp_gclk_c2_l2t3 = pll_cmp_clk ; |
| 2067 | assign cmp_gclk_c2_l2t5 = pll_cmp_clk ; |
| 2068 | assign cmp_gclk_c2_l2t7 = pll_cmp_clk ; |
| 2069 | assign cmp_gclk_c4_mcu0 = pll_cmp_clk ; |
| 2070 | assign cmp_gclk_c4_mcu1 = pll_cmp_clk ; |
| 2071 | assign cmp_gclk_c0_mcu2 = pll_cmp_clk ; |
| 2072 | assign cmp_gclk_c0_mcu3 = pll_cmp_clk ; |
| 2073 | assign cmp_gclk_c1_mio = pll_cmp_clk ; |
| 2074 | assign cmp_gclk_c3_mio = pll_cmp_clk ; |
| 2075 | assign cmp_gclk_c2_mio_left = pll_cmp_clk ; |
| 2076 | assign cmp_gclk_c2_mio_right = pll_cmp_clk ; |
| 2077 | assign cmp_gclk_c3_ncu = pll_cmp_clk ; |
| 2078 | assign cmp_gclk_c3_peu = pll_cmp_clk ; |
| 2079 | // assign cmp_gclk_c1_rst = pll_cmp_clk ; |
| 2080 | assign cmp_gclk_c3_sii = pll_cmp_clk ; |
| 2081 | assign cmp_gclk_c1_sio = pll_cmp_clk ; |
| 2082 | assign cmp_gclk_c3_spc0 = pll_cmp_clk ; |
| 2083 | assign cmp_gclk_c3_spc2 = pll_cmp_clk ; |
| 2084 | assign cmp_gclk_c1_spc4 = pll_cmp_clk ; |
| 2085 | assign cmp_gclk_c1_spc6 = pll_cmp_clk ; |
| 2086 | assign cmp_gclk_c2_spc1 = pll_cmp_clk ; |
| 2087 | assign cmp_gclk_c2_spc3 = pll_cmp_clk ; |
| 2088 | assign cmp_gclk_c2_spc5 = pll_cmp_clk ; |
| 2089 | assign cmp_gclk_c2_spc7 = pll_cmp_clk ; |
| 2090 | assign cmp_gclk_c1_tcu = pll_cmp_clk ; |
| 2091 | assign cmp_gclk_c1_mac = pll_cmp_clk ; |
| 2092 | assign cmp_gclk_c0_rdp = pll_cmp_clk ; |
| 2093 | assign cmp_gclk_c0_rtx = pll_cmp_clk ; |
| 2094 | assign cmp_gclk_c0_tds = pll_cmp_clk ; |
| 2095 | |
| 2096 | endmodule |
| 2097 | |
| 2098 | |
| 2099 | |
| 2100 | |
| 2101 | // TBD -- check niu reset stuff |
| 2102 | // -- sync pulses for l2b, l2t (falls under mapping) |
| 2103 | // -- extra clock port for rng |
| 2104 | // -- [error] mcu*_dr_clk_stop needs separate gclk |
| 2105 | // -- how to handle spare ports?? |
| 2106 | |
| 2107 | // MACRO = n2_clk_gl_cc |
| 2108 | // |
| 2109 | // TOP: n2_clk_gl_cust |
| 2110 | // - n2_clk_gl_cmp_tree |
| 2111 | // - n2_clk_gl_dr_tree |
| 2112 | // - n2_clk_gl_cc_stage_top |
| 2113 | // |
| 2114 | |
| 2115 | // tcu_l2t6_clk_stop & tcu_l2t5_clk_stop connectivity swapped at primary inputs |
| 2116 | // spc1 & spc5 clk_stops messed up in latest cdms version (older one ok) |
| 2117 | // no use for outputs stg3_io2x_sync_en_out_c2t & stg4_io2x_sync_en_c3t |
| 2118 | // change stg4_io2x_sync_en_c3t from output pin to input pin, //lijuan |
| 2119 | |
| 2120 | // 34 n2_clk_gl_cc_stage_top |
| 2121 | // 2 n2_clk_gl_cc_stage_ccu_m0 |
| 2122 | // 3 n2_clk_gl_cc_stage_rst_m0 |
| 2123 | // 4 n2_clk_gl_cc_stage_tcu_m0 - need correction for dr_clk_stop |
| 2124 | // 5 n2_clk_gl_cc_stage_17s1 |
| 2125 | // 17 n2_clk_gl_cc_stage_8s2 |
| 2126 | // 7 n2_clk_gl_cc_stage_4s4 |
| 2127 | // 1 n2_clk_gl_cc_stg_c2b_s1_1 |
| 2128 | // 6 n2_clk_gl_cc_stg_c1t_s1_0 |
| 2129 | // 8 n2_clk_gl_cc_stg_c1t_s4_0 |
| 2130 | // 9 n2_clk_gl_cc_stg_c1t_s4_1 |
| 2131 | // 10 n2_clk_gl_cc_stg_c1t_s4_2 |
| 2132 | // 11 n2_clk_gl_cc_stg_c1t_s1_1 |
| 2133 | // 12 n2_clk_gl_cc_stg_c1b_s4_0 |
| 2134 | // 13 n2_clk_gl_cc_stg_c1b_s4_1 |
| 2135 | // 14 n2_clk_gl_cc_stg_c1b_s4_2 |
| 2136 | // 15 n2_clk_gl_cc_stg_c1b_s4_3 |
| 2137 | // 16 n2_clk_gl_cc_stg_c2b_s1_0 |
| 2138 | // 18 n2_clk_gl_cc_stg_c2b_s2_0 |
| 2139 | // 19 n2_clk_gl_cc_stg_c2b_s2_1 |
| 2140 | // 20 n2_clk_gl_cc_stg_c2t_s1_0 |
| 2141 | // 21 n2_clk_gl_cc_stg_c2t_s2_0 |
| 2142 | // 22 n2_clk_gl_cc_stg_c2t_s2_1 |
| 2143 | // 23 n2_clk_gl_cc_stg_c3t_s1_0 |
| 2144 | // 24 n2_clk_gl_cc_stg_c3t_s1_1 |
| 2145 | // 25 n2_clk_gl_cc_stg_c3t_s1_3 |
| 2146 | // 26 n2_clk_gl_cc_stg_c3t_s1_2 |
| 2147 | // 27 n2_clk_gl_cc_stg_c3b_s1_0 - connection errors (wires crossed) |
| 2148 | // 28 n2_clk_gl_cc_stg_c3b_s1_1 - compilation errors here |
| 2149 | // 29 n2_clk_gl_cc_stg_c3b_s1_3 |
| 2150 | // 30 n2_clk_gl_cc_stg_c3b_s1_2 - compilation errors here |
| 2151 | // 31 n2_clk_gl_cc_stg_c1b_s1_0 |
| 2152 | // 32 n2_clk_gl_cc_stg_c1b_s1_1 |
| 2153 | // 33 n2_clk_gl_cc_stg_c2t_s1_1 |
| 2154 | // 35 n2_clk_gl_cc_stage_align |
| 2155 | // 36 n2_clk_gl_cc_stg_mcu_dr - FOR INT6.1 |
| 2156 | |
| 2157 | |
| 2158 | // EDITS NEEDED |
| 2159 | // input [2:2] stg3_l2t_clk_stop_in_c3b -> stg3_l2t2_clk_stop_in_c3b |
| 2160 | // output [2:2] stg4_l2t_clk_stop_out_c3b -> stg4_l2t2_clk_stop_out_c3b |
| 2161 | |
| 2162 | // ADDITIONAL |
| 2163 | // input ccu_vco_aligned |
| 2164 | // output gclk_aligned |
| 2165 | |
| 2166 | // MAPPING FOR ALL OUTPUTS |
| 2167 | // |
| 2168 | // gl_ccx_clk_stop; |
| 2169 | // gl_cmp_io_sync_en_c1b; |
| 2170 | // gl_cmp_io_sync_en_c1m; |
| 2171 | // gl_cmp_io_sync_en_c1t; |
| 2172 | // gl_cmp_io_sync_en_c2b; |
| 2173 | // gl_cmp_io_sync_en_c2t; |
| 2174 | // gl_cmp_io_sync_en_c3b; |
| 2175 | // gl_cmp_io_sync_en_c3t0; |
| 2176 | // gl_cmp_io_sync_en_c3t; |
| 2177 | // gl_dmu_peu_por_c3b; |
| 2178 | // gl_dmu_peu_wmr_c3b; |
| 2179 | // gl_dr_sync_en_c1m; |
| 2180 | // gl_dr_sync_en_c3t; |
| 2181 | // gl_io2x_out_c1b; |
| 2182 | // gl_io2x_sync_en_c1m; |
| 2183 | // gl_io2x_sync_en_c3t0; |
| 2184 | // gl_io2x_sync_en_c3t; |
| 2185 | // gl_io2x_sync_en_in_c2b; |
| 2186 | // gl_io_cmp_sync_en_c1b; |
| 2187 | // gl_io_cmp_sync_en_c1m; |
| 2188 | // gl_io_cmp_sync_en_c1t; |
| 2189 | // gl_io_cmp_sync_en_c2b; |
| 2190 | // gl_io_cmp_sync_en_c2t; |
| 2191 | // gl_io_cmp_sync_en_c3b; |
| 2192 | // gl_io_cmp_sync_en_c3t0; |
| 2193 | // gl_io_cmp_sync_en_c3t; |
| 2194 | // gl_io_out_c1b; |
| 2195 | // gl_io_out_c1m; |
| 2196 | // gl_io_out_c3b0; |
| 2197 | // gl_io_out_c3b; |
| 2198 | // gl_io_out_c3t; |
| 2199 | // gl_l2_por_c1t; |
| 2200 | // gl_l2_por_c2b; |
| 2201 | // gl_l2_por_c2t; |
| 2202 | // gl_l2_por_c3b0; |
| 2203 | // gl_l2_por_c3b; |
| 2204 | // gl_l2_por_c3t0; |
| 2205 | // gl_l2_por_c3t; |
| 2206 | // gl_l2_wmr_c1b; |
| 2207 | // gl_l2_wmr_c1t; |
| 2208 | // gl_l2_wmr_c2b; |
| 2209 | // gl_l2_wmr_c2t; |
| 2210 | // gl_l2_wmr_c3b; |
| 2211 | // gl_l2_wmr_c3t0; |
| 2212 | // gl_l2_wmr_c3t; |
| 2213 | // gl_mio_clk_stop_c1t; |
| 2214 | // gl_mio_clk_stop_c2t; |
| 2215 | // gl_mio_clk_stop_c3t; |
| 2216 | // gl_mio_io2x_sync_en_c1b; |
| 2217 | // gl_mio_io2x_sync_en_c1t; |
| 2218 | // gl_rst_l2_por_c1m; |
| 2219 | // gl_rst_l2_wmr_c1m; |
| 2220 | // gl_rst_mac_c1b; |
| 2221 | // gl_rst_niu_wmr_c1b; |
| 2222 | |
| 2223 | |
| 2224 | |
| 2225 | // ************************************************************************ |
| 2226 | // 1 module n2_clk_gl_cc_stg_c2b_s1_1 (8x1) |
| 2227 | // ************************************************************************ |
| 2228 | |
| 2229 | module n2_clk_gl_cc_stg_c2b_s1_1 (stg2_sii_clk_stop_in_c2b ,gclk_l2t7 , |
| 2230 | stg2_ncu_clk_stop_in_c2b ,stg3_l2t7_clk_stop_out_c2b , |
| 2231 | stg3_ccx_clk_stop_out_c2b ,stg3_sii_clk_stop_out_c2b , |
| 2232 | stg3_ncu_clk_stop_out_c2b ,stg3_sii_io_clk_stop_out_c2b , |
| 2233 | stg3_ncu_io_clk_stop_out_c2b ,stg3_dmu_io_clk_stop_out_c2b , |
| 2234 | stg3_peu_io_clk_stop_out_c2b ,stg2_peu_io_clk_stop_in_c2b , |
| 2235 | stg2_sii_io_clk_stop_in_c2b ,stg2_ncu_io_clk_stop_in_c2b , |
| 2236 | stg2_dmu_io_clk_stop_in_c2b ,stg2_l2t7_clk_stop_in_c2b , |
| 2237 | stg2_ccx_clk_stop_in_c2b ); |
| 2238 | |
| 2239 | input gclk_l2t7 ; |
| 2240 | input stg2_ccx_clk_stop_in_c2b ; |
| 2241 | input stg2_dmu_io_clk_stop_in_c2b ; |
| 2242 | input stg2_l2t7_clk_stop_in_c2b ; |
| 2243 | input stg2_ncu_clk_stop_in_c2b ; |
| 2244 | input stg2_ncu_io_clk_stop_in_c2b ; |
| 2245 | input stg2_peu_io_clk_stop_in_c2b ; |
| 2246 | input stg2_sii_clk_stop_in_c2b ; |
| 2247 | input stg2_sii_io_clk_stop_in_c2b ; |
| 2248 | output stg3_ccx_clk_stop_out_c2b ; |
| 2249 | output stg3_dmu_io_clk_stop_out_c2b ; |
| 2250 | output stg3_l2t7_clk_stop_out_c2b ; |
| 2251 | output stg3_ncu_clk_stop_out_c2b ; |
| 2252 | output stg3_ncu_io_clk_stop_out_c2b ; |
| 2253 | output stg3_peu_io_clk_stop_out_c2b ; |
| 2254 | output stg3_sii_clk_stop_out_c2b ; |
| 2255 | output stg3_sii_io_clk_stop_out_c2b ; |
| 2256 | |
| 2257 | wire [8:0] unused; |
| 2258 | |
| 2259 | n2_clk_gl_cc_stage_17s1 xc2b_s1_1 ( |
| 2260 | .stg0_in ( {9'b0, |
| 2261 | stg2_ccx_clk_stop_in_c2b, stg2_dmu_io_clk_stop_in_c2b, |
| 2262 | stg2_l2t7_clk_stop_in_c2b, stg2_ncu_clk_stop_in_c2b, |
| 2263 | stg2_ncu_io_clk_stop_in_c2b, stg2_peu_io_clk_stop_in_c2b, |
| 2264 | stg2_sii_clk_stop_in_c2b, stg2_sii_io_clk_stop_in_c2b} ), |
| 2265 | .stg1_out ( {unused, |
| 2266 | stg3_ccx_clk_stop_out_c2b, stg3_dmu_io_clk_stop_out_c2b, |
| 2267 | stg3_l2t7_clk_stop_out_c2b, stg3_ncu_clk_stop_out_c2b, |
| 2268 | stg3_ncu_io_clk_stop_out_c2b, stg3_peu_io_clk_stop_out_c2b, |
| 2269 | stg3_sii_clk_stop_out_c2b, stg3_sii_io_clk_stop_out_c2b} ), |
| 2270 | .gclk (gclk_l2t7) ); |
| 2271 | |
| 2272 | endmodule |
| 2273 | |
| 2274 | |
| 2275 | // ************************************************************************ |
| 2276 | // 2 module n2_clk_gl_cc_stage_ccu_m1 (special) |
| 2277 | // ************************************************************************ |
| 2278 | |
| 2279 | module n2_clk_gl_exp (gclk_in ,gl_cmp_io_sync_en_c1m , |
| 2280 | gl_io_out_c1m ,gl_io_cmp_sync_en_c1m ,stg1_io2x_out_out_c1b , |
| 2281 | gl_io2x_sync_en_c1m ,ccu_cmp_io_sync_en ,ccu_io_out , |
| 2282 | stg1_dr_sync_en_out_c1t ,stg1_io2x_sync_en_out_c1b , |
| 2283 | stg1_cmp_io_sync_en_out_c1t ,stg1_io_cmp_sync_en_out_c1t , |
| 2284 | stg1_io2x_sync_en_out_c1t ,ccu_io2x_sync_en ,gl_dr_sync_en_c1m , |
| 2285 | stg1_cmp_io_sync_en_out_c1b ,stg1_io_out_out_c1t , |
| 2286 | stg1_io_out_out_c1b ,stg1_io_cmp_sync_en_out_c1b , |
| 2287 | ccu_io_cmp_sync_en ,ccu_dr_sync_en ,ccu_io2x_out ); |
| 2288 | input ccu_cmp_io_sync_en ; |
| 2289 | input ccu_dr_sync_en ; |
| 2290 | input ccu_io2x_out ; |
| 2291 | input ccu_io2x_sync_en ; |
| 2292 | input ccu_io_cmp_sync_en ; |
| 2293 | input ccu_io_out ; |
| 2294 | input gclk_in ; |
| 2295 | output gl_cmp_io_sync_en_c1m ; |
| 2296 | output gl_dr_sync_en_c1m ; |
| 2297 | output gl_io2x_sync_en_c1m ; |
| 2298 | output gl_io_cmp_sync_en_c1m ; |
| 2299 | output gl_io_out_c1m ; |
| 2300 | output stg1_cmp_io_sync_en_out_c1b ; |
| 2301 | output stg1_cmp_io_sync_en_out_c1t ; |
| 2302 | output stg1_dr_sync_en_out_c1t ; |
| 2303 | output stg1_io2x_out_out_c1b ; |
| 2304 | output stg1_io2x_sync_en_out_c1b ; |
| 2305 | output stg1_io2x_sync_en_out_c1t ; |
| 2306 | output stg1_io_cmp_sync_en_out_c1b ; |
| 2307 | output stg1_io_cmp_sync_en_out_c1t ; |
| 2308 | output stg1_io_out_out_c1b ; |
| 2309 | output stg1_io_out_out_c1t ; |
| 2310 | |
| 2311 | wire stg1_cmp_io_sync_en_c1m ; |
| 2312 | wire stg1_dr_sync_en_c1m ; |
| 2313 | wire stg1_io2x_sync_en_c1m ; |
| 2314 | wire stg1_io_cmp_sync_en_c1m ; |
| 2315 | wire stg1_io_out_c1m ; |
| 2316 | |
| 2317 | wire [1:0] unused0; |
| 2318 | wire [2:0] unused1; |
| 2319 | |
| 2320 | n2_clk_gl_cc_stage_17s1 xccu_m0_0 ( |
| 2321 | .stg0_in ( {2'b0, ccu_cmp_io_sync_en, |
| 2322 | ccu_cmp_io_sync_en, ccu_cmp_io_sync_en, |
| 2323 | ccu_dr_sync_en, ccu_dr_sync_en, |
| 2324 | ccu_io2x_out, ccu_io2x_sync_en, |
| 2325 | ccu_io2x_sync_en, ccu_io2x_sync_en, |
| 2326 | ccu_io_cmp_sync_en, ccu_io_cmp_sync_en, |
| 2327 | ccu_io_cmp_sync_en, ccu_io_out, |
| 2328 | ccu_io_out, ccu_io_out} ), |
| 2329 | .stg1_out ( {unused0, stg1_cmp_io_sync_en_c1m, |
| 2330 | stg1_cmp_io_sync_en_out_c1b, stg1_cmp_io_sync_en_out_c1t, |
| 2331 | stg1_dr_sync_en_c1m, stg1_dr_sync_en_out_c1t, |
| 2332 | stg1_io2x_out_out_c1b, stg1_io2x_sync_en_c1m, |
| 2333 | stg1_io2x_sync_en_out_c1b, stg1_io2x_sync_en_out_c1t, |
| 2334 | stg1_io_cmp_sync_en_c1m, stg1_io_cmp_sync_en_out_c1b, |
| 2335 | stg1_io_cmp_sync_en_out_c1t, stg1_io_out_c1m, |
| 2336 | stg1_io_out_out_c1b, stg1_io_out_out_c1t} ), |
| 2337 | .gclk (gclk_in) |
| 2338 | ); |
| 2339 | |
| 2340 | |
| 2341 | n2_clk_gl_cc_stage_4s4 xccu_m0_1 ( |
| 2342 | .stg1_in ( |
| 2343 | {stg1_cmp_io_sync_en_c1m, stg1_dr_sync_en_c1m, |
| 2344 | stg1_io2x_sync_en_c1m, stg1_io_cmp_sync_en_c1m} ), |
| 2345 | .stg5_out ( |
| 2346 | {gl_cmp_io_sync_en_c1m, gl_dr_sync_en_c1m, |
| 2347 | gl_io2x_sync_en_c1m, gl_io_cmp_sync_en_c1m} ), |
| 2348 | .gclk (gclk_in) |
| 2349 | ); |
| 2350 | |
| 2351 | |
| 2352 | n2_clk_gl_cc_stage_4s4 xccu_m0_2 ( |
| 2353 | .stg1_in ( {3'b0, stg1_io_out_c1m} ), |
| 2354 | .stg5_out ( {unused1, gl_io_out_c1m} ), |
| 2355 | .gclk (gclk_in) |
| 2356 | ); |
| 2357 | |
| 2358 | |
| 2359 | endmodule |
| 2360 | |
| 2361 | |
| 2362 | // ************************************************************************ |
| 2363 | // 3 module n2_clk_gl_cc_stage_rst_m0 (special) |
| 2364 | // ************************************************************************ |
| 2365 | |
| 2366 | module n2_clk_gl_cc_stage_rst_m0 (stg1_rst_l2_por_out_c1b , |
| 2367 | stg1_dmu_peu_por_out_c1b ,gclk_in ,gl_rst_l2_por_c1m , |
| 2368 | stg1_rst_l2_wmr_out_c1t ,stg1_rst_l2_wmr_out_c1b , |
| 2369 | stg1_rst_niu_wmr_out_c1b ,stg1_dmu_peu_wmr_out_c1b ,rst_niu_mac_ , |
| 2370 | rst_l2_por_ ,rst_l2_wmr_ ,stg1_rst_niu_mac_out_c1b , |
| 2371 | rst_dmu_peu_por_ ,rst_dmu_peu_wmr_ ,stg1_rst_l2_por_out_c1t , |
| 2372 | gl_rst_l2_wmr_c1m ,rst_niu_wmr_ ); |
| 2373 | |
| 2374 | input gclk_in ; |
| 2375 | |
| 2376 | input rst_dmu_peu_por_ ; |
| 2377 | input rst_dmu_peu_wmr_ ; |
| 2378 | input rst_l2_por_ ; |
| 2379 | input rst_l2_wmr_ ; |
| 2380 | input rst_niu_mac_ ; |
| 2381 | input rst_niu_wmr_ ; |
| 2382 | |
| 2383 | output gl_rst_l2_por_c1m ; |
| 2384 | output gl_rst_l2_wmr_c1m ; |
| 2385 | |
| 2386 | output stg1_dmu_peu_por_out_c1b ; |
| 2387 | output stg1_dmu_peu_wmr_out_c1b ; |
| 2388 | output stg1_rst_l2_por_out_c1b ; |
| 2389 | output stg1_rst_l2_por_out_c1t ; |
| 2390 | output stg1_rst_l2_wmr_out_c1b ; |
| 2391 | output stg1_rst_l2_wmr_out_c1t ; |
| 2392 | output stg1_rst_niu_mac_out_c1b ; |
| 2393 | output stg1_rst_niu_wmr_out_c1b ; |
| 2394 | |
| 2395 | wire stg1_rst_l2_por_c1m ; |
| 2396 | wire stg1_rst_l2_wmr_c1m ; |
| 2397 | |
| 2398 | wire [6:0] unused0; |
| 2399 | wire [1:0] unused1; |
| 2400 | |
| 2401 | n2_clk_gl_cc_stage_17s1 xrst_m0_0 ( |
| 2402 | .stg0_in ( {7'b0, |
| 2403 | rst_dmu_peu_por_, rst_dmu_peu_wmr_, |
| 2404 | rst_l2_por_, rst_l2_por_, |
| 2405 | rst_l2_wmr_, rst_l2_wmr_, |
| 2406 | rst_niu_mac_, rst_niu_wmr_, |
| 2407 | rst_l2_por_, rst_l2_wmr_} ), |
| 2408 | .stg1_out ( {unused0, |
| 2409 | stg1_dmu_peu_por_out_c1b, stg1_dmu_peu_wmr_out_c1b, |
| 2410 | stg1_rst_l2_por_out_c1b, stg1_rst_l2_por_out_c1t, |
| 2411 | stg1_rst_l2_wmr_out_c1b, stg1_rst_l2_wmr_out_c1t, |
| 2412 | stg1_rst_niu_mac_out_c1b, stg1_rst_niu_wmr_out_c1b, |
| 2413 | stg1_rst_l2_por_c1m, stg1_rst_l2_wmr_c1m} ), |
| 2414 | .gclk (gclk_in) |
| 2415 | ); |
| 2416 | |
| 2417 | n2_clk_gl_cc_stage_4s4 xrst_m0_1 ( |
| 2418 | .stg1_in ( {2'b0, stg1_rst_l2_por_c1m, stg1_rst_l2_wmr_c1m} ), |
| 2419 | .stg5_out ( {unused1, gl_rst_l2_por_c1m, gl_rst_l2_wmr_c1m} ), |
| 2420 | .gclk (gclk_in) |
| 2421 | ); |
| 2422 | |
| 2423 | endmodule |
| 2424 | |
| 2425 | |
| 2426 | // ************************************************************************ |
| 2427 | // 4 module n2_clk_gl_cc_stage_tcu_m0 (special) |
| 2428 | // ************************************************************************ |
| 2429 | |
| 2430 | module n2_clk_gl_cc_stage_tcu_m0 (stg1_peu_io_clk_stop_out_c1b , |
| 2431 | gl_l2t4_clk_stop ,tcu_mcu1_clk_stop ,gl_ccu_io_clk_stop , |
| 2432 | gl_sio_clk_stop ,gl_sio_io_clk_stop ,gl_db1_clk_stop , |
| 2433 | gl_rst_clk_stop ,gl_rst_io_clk_stop ,gl_efu_clk_stop , |
| 2434 | stg1_l2t3_clk_stop_out_c1b ,tcu_l2t5_clk_stop ,tcu_l2t7_clk_stop , |
| 2435 | stg1_ncu_clk_stop_out_c1b ,gl_mcu2_dr_clk_stop , |
| 2436 | stg1_l2t1_clk_stop_out_c1t ,tcu_spc1_clk_stop ,tcu_sii_clk_stop , |
| 2437 | tcu_ncu_io_clk_stop ,tcu_sii_io_clk_stop ,tcu_ncu_clk_stop , |
| 2438 | tcu_db0_clk_stop ,gl_l2d6_clk_stop ,gl_l2t6_clk_stop , |
| 2439 | stg1_l2t7_clk_stop_out_c1b ,stg1_sii_io_clk_stop_out_c1b , |
| 2440 | stg1_l2d0_clk_stop_out_c1t ,stg1_ccx_clk_stop_out_c1b , |
| 2441 | stg1_rtx_io_clk_stop_out_c1b ,gclk_in ,tcu_mcu2_io_clk_stop , |
| 2442 | gl_efu_io_clk_stop ,tcu_mcu0_clk_stop ,stg1_mio_clk_stop_out_c1t , |
| 2443 | stg1_l2t2_clk_stop_out_c1b ,stg1_mcu1_clk_stop_out_c1t , |
| 2444 | stg1_ncu_io_clk_stop_out_c1b ,tcu_ccu_clk_stop ,tcu_ccu_io_clk_stop |
| 2445 | ,tcu_efu_io_clk_stop ,tcu_l2b6_clk_stop ,tcu_l2t6_clk_stop , |
| 2446 | tcu_rst_clk_stop ,tcu_rst_io_clk_stop ,tcu_efu_clk_stop , |
| 2447 | tcu_sio_clk_stop ,tcu_sio_io_clk_stop ,tcu_db1_clk_stop , |
| 2448 | tcu_peu_io_clk_stop ,stg1_db0_clk_stop_out_c1b ,tcu_ccx_clk_stop , |
| 2449 | tcu_spc0_clk_stop ,tcu_spc2_clk_stop ,stg1_mcu1_dr_clk_stop_out_c1t |
| 2450 | ,tcu_spc3_clk_stop ,tcu_spc4_clk_stop ,tcu_spc5_clk_stop , |
| 2451 | tcu_spc6_clk_stop ,tcu_spc7_clk_stop ,tcu_mcu2_clk_stop , |
| 2452 | tcu_mcu3_io_clk_stop ,tcu_mcu3_dr_clk_stop ,tcu_l2t0_clk_stop , |
| 2453 | gl_mcu2_clk_stop ,tcu_l2t3_clk_stop ,tcu_l2t2_clk_stop , |
| 2454 | tcu_l2t1_clk_stop ,tcu_l2d0_clk_stop ,tcu_l2d1_clk_stop , |
| 2455 | tcu_l2d2_clk_stop ,tcu_l2d3_clk_stop ,tcu_l2d4_clk_stop , |
| 2456 | tcu_l2d5_clk_stop ,tcu_l2d7_clk_stop ,tcu_l2b0_clk_stop , |
| 2457 | tcu_l2b1_clk_stop ,tcu_l2b2_clk_stop ,tcu_l2b3_clk_stop , |
| 2458 | tcu_l2b4_clk_stop ,tcu_l2b5_clk_stop ,tcu_mcu0_io_clk_stop , |
| 2459 | tcu_mcu1_io_clk_stop ,tcu_mcu0_dr_clk_stop ,tcu_mcu1_dr_clk_stop , |
| 2460 | gl_ccu_clk_stop ,stg1_spc1_clk_stop_out_c1t ,tcu_mac_io_clk_stop , |
| 2461 | tcu_tds_io_clk_stop ,tcu_rtx_io_clk_stop ,tcu_rdp_io_clk_stop , |
| 2462 | stg1_spc2_clk_stop_out_c1b ,gl_l2b6_clk_stop , |
| 2463 | stg1_spc3_clk_stop_out_c1b ,stg1_spc4_clk_stop_out_c1t , |
| 2464 | stg1_spc5_clk_stop_out_c1t ,gl_l2b7_clk_stop ,gl_mcu3_clk_stop , |
| 2465 | tcu_mcu3_clk_stop ,tcu_l2b7_clk_stop ,tcu_l2d6_clk_stop , |
| 2466 | tcu_l2t4_clk_stop ,stg1_spc6_clk_stop_out_c1b , |
| 2467 | stg1_spc7_clk_stop_out_c1b ,stg1_l2t0_clk_stop_out_c1t , |
| 2468 | tcu_dmu_io_clk_stop ,stg1_l2t5_clk_stop_out_c1t , |
| 2469 | stg1_l2d1_clk_stop_out_c1t ,stg1_l2d2_clk_stop_out_c1b , |
| 2470 | stg1_l2d3_clk_stop_out_c1b ,stg1_l2d4_clk_stop_out_c1t , |
| 2471 | stg1_l2d5_clk_stop_out_c1t ,stg1_l2d7_clk_stop_out_c1b , |
| 2472 | stg1_l2b0_clk_stop_out_c1t ,stg1_sii_clk_stop_out_c1b , |
| 2473 | stg1_l2b1_clk_stop_out_c1t ,stg1_l2b2_clk_stop_out_c1b , |
| 2474 | stg1_l2b3_clk_stop_out_c1b ,stg1_l2b4_clk_stop_out_c1t , |
| 2475 | stg1_l2b5_clk_stop_out_c1t ,stg1_mcu0_clk_stop_out_c1t , |
| 2476 | stg1_spc0_clk_stop_out_c1t ,stg1_mcu1_io_clk_stop_out_c1t , |
| 2477 | stg1_mcu0_dr_clk_stop_out_c1t ,stg1_rdp_io_clk_stop_out_c1b , |
| 2478 | stg1_tds_io_clk_stop_out_c1b ,stg1_mac_io_clk_stop_out_c1b , |
| 2479 | stg1_dmu_io_clk_stop_out_c1b ,stg1_mcu0_io_clk_stop_out_c1t , |
| 2480 | tcu_mio_clk_stop ,gl_mcu2_io_clk_stop ,tcu_mcu2_dr_clk_stop , |
| 2481 | gl_mcu3_io_clk_stop ,gl_mcu3_dr_clk_stop, dr_gclk_in ); |
| 2482 | |
| 2483 | input gclk_in ; |
| 2484 | input dr_gclk_in; // FOR INT6.1 |
| 2485 | input tcu_ccu_clk_stop ; |
| 2486 | input tcu_ccu_io_clk_stop ; |
| 2487 | input tcu_ccx_clk_stop ; |
| 2488 | input tcu_db0_clk_stop ; |
| 2489 | input tcu_db1_clk_stop ; |
| 2490 | input tcu_dmu_io_clk_stop ; |
| 2491 | input tcu_efu_clk_stop ; |
| 2492 | input tcu_efu_io_clk_stop ; |
| 2493 | input tcu_l2b0_clk_stop ; |
| 2494 | input tcu_l2b1_clk_stop ; |
| 2495 | input tcu_l2b2_clk_stop ; |
| 2496 | input tcu_l2b3_clk_stop ; |
| 2497 | input tcu_l2b4_clk_stop ; |
| 2498 | input tcu_l2b5_clk_stop ; |
| 2499 | input tcu_l2b6_clk_stop ; |
| 2500 | input tcu_l2b7_clk_stop ; |
| 2501 | input tcu_l2d0_clk_stop ; |
| 2502 | input tcu_l2d1_clk_stop ; |
| 2503 | input tcu_l2d2_clk_stop ; |
| 2504 | input tcu_l2d3_clk_stop ; |
| 2505 | input tcu_l2d4_clk_stop ; |
| 2506 | input tcu_l2d5_clk_stop ; |
| 2507 | input tcu_l2d7_clk_stop ; |
| 2508 | input tcu_l2d6_clk_stop ; |
| 2509 | input tcu_l2t0_clk_stop ; |
| 2510 | input tcu_l2t1_clk_stop ; |
| 2511 | input tcu_l2t2_clk_stop ; |
| 2512 | input tcu_l2t3_clk_stop ; |
| 2513 | input tcu_l2t4_clk_stop ; |
| 2514 | input tcu_l2t5_clk_stop ; |
| 2515 | input tcu_l2t6_clk_stop ; |
| 2516 | input tcu_l2t7_clk_stop ; |
| 2517 | input tcu_mac_io_clk_stop ; |
| 2518 | input tcu_mcu0_clk_stop ; |
| 2519 | input tcu_mcu0_dr_clk_stop ; |
| 2520 | input tcu_mcu0_io_clk_stop ; |
| 2521 | input tcu_mcu1_clk_stop ; |
| 2522 | input tcu_mcu1_dr_clk_stop ; |
| 2523 | input tcu_mcu1_io_clk_stop ; |
| 2524 | input tcu_mcu2_clk_stop ; |
| 2525 | input tcu_mcu2_dr_clk_stop ; |
| 2526 | input tcu_mcu2_io_clk_stop ; |
| 2527 | input tcu_mcu3_clk_stop ; |
| 2528 | input tcu_mcu3_dr_clk_stop ; |
| 2529 | input tcu_mcu3_io_clk_stop ; |
| 2530 | input tcu_mio_clk_stop ; |
| 2531 | input tcu_ncu_clk_stop ; |
| 2532 | input tcu_ncu_io_clk_stop ; |
| 2533 | input tcu_peu_io_clk_stop ; |
| 2534 | input tcu_rdp_io_clk_stop ; |
| 2535 | input tcu_rst_clk_stop ; |
| 2536 | input tcu_rst_io_clk_stop ; |
| 2537 | input tcu_rtx_io_clk_stop ; |
| 2538 | input tcu_sii_clk_stop ; |
| 2539 | input tcu_sii_io_clk_stop ; |
| 2540 | input tcu_sio_clk_stop ; |
| 2541 | input tcu_sio_io_clk_stop ; |
| 2542 | input tcu_spc0_clk_stop ; |
| 2543 | input tcu_spc1_clk_stop ; |
| 2544 | input tcu_spc2_clk_stop ; |
| 2545 | input tcu_spc3_clk_stop ; |
| 2546 | input tcu_spc4_clk_stop ; |
| 2547 | input tcu_spc5_clk_stop ; |
| 2548 | input tcu_spc6_clk_stop ; |
| 2549 | input tcu_spc7_clk_stop ; |
| 2550 | input tcu_tds_io_clk_stop ; |
| 2551 | |
| 2552 | output gl_ccu_clk_stop ; |
| 2553 | output gl_ccu_io_clk_stop ; |
| 2554 | output gl_db1_clk_stop ; |
| 2555 | output gl_efu_clk_stop ; |
| 2556 | output gl_efu_io_clk_stop ; |
| 2557 | output gl_l2b6_clk_stop ; |
| 2558 | output gl_l2b7_clk_stop ; |
| 2559 | output gl_l2d6_clk_stop ; |
| 2560 | output gl_l2t4_clk_stop ; |
| 2561 | output gl_l2t6_clk_stop ; |
| 2562 | output gl_mcu2_clk_stop ; |
| 2563 | output gl_mcu2_dr_clk_stop ; |
| 2564 | output gl_mcu2_io_clk_stop ; |
| 2565 | output gl_mcu3_clk_stop ; |
| 2566 | output gl_mcu3_dr_clk_stop ; |
| 2567 | output gl_mcu3_io_clk_stop ; |
| 2568 | output gl_rst_clk_stop ; |
| 2569 | output gl_rst_io_clk_stop ; |
| 2570 | output gl_sio_clk_stop ; |
| 2571 | output gl_sio_io_clk_stop ; |
| 2572 | |
| 2573 | |
| 2574 | output stg1_ccx_clk_stop_out_c1b ; |
| 2575 | output stg1_db0_clk_stop_out_c1b ; |
| 2576 | output stg1_dmu_io_clk_stop_out_c1b ; |
| 2577 | output stg1_l2b0_clk_stop_out_c1t ; |
| 2578 | output stg1_l2b1_clk_stop_out_c1t ; |
| 2579 | output stg1_l2b2_clk_stop_out_c1b ; |
| 2580 | output stg1_l2b3_clk_stop_out_c1b ; |
| 2581 | output stg1_l2b4_clk_stop_out_c1t ; |
| 2582 | output stg1_l2b5_clk_stop_out_c1t ; |
| 2583 | output stg1_l2d0_clk_stop_out_c1t ; |
| 2584 | output stg1_l2d1_clk_stop_out_c1t ; |
| 2585 | output stg1_l2d2_clk_stop_out_c1b ; |
| 2586 | output stg1_l2d3_clk_stop_out_c1b ; |
| 2587 | output stg1_l2d4_clk_stop_out_c1t ; |
| 2588 | output stg1_l2d5_clk_stop_out_c1t ; |
| 2589 | output stg1_l2d7_clk_stop_out_c1b ; |
| 2590 | output stg1_l2t0_clk_stop_out_c1t ; |
| 2591 | output stg1_l2t1_clk_stop_out_c1t ; |
| 2592 | output stg1_l2t2_clk_stop_out_c1b ; |
| 2593 | output stg1_l2t3_clk_stop_out_c1b ; |
| 2594 | output stg1_l2t5_clk_stop_out_c1t ; |
| 2595 | output stg1_l2t7_clk_stop_out_c1b ; |
| 2596 | output stg1_mac_io_clk_stop_out_c1b ; |
| 2597 | output stg1_mcu0_clk_stop_out_c1t ; |
| 2598 | output stg1_mcu0_dr_clk_stop_out_c1t ; |
| 2599 | output stg1_mcu0_io_clk_stop_out_c1t ; |
| 2600 | output stg1_mcu1_clk_stop_out_c1t ; |
| 2601 | output stg1_mcu1_dr_clk_stop_out_c1t ; |
| 2602 | output stg1_mcu1_io_clk_stop_out_c1t ; |
| 2603 | output stg1_mio_clk_stop_out_c1t ; |
| 2604 | output stg1_ncu_clk_stop_out_c1b ; |
| 2605 | output stg1_ncu_io_clk_stop_out_c1b ; |
| 2606 | output stg1_peu_io_clk_stop_out_c1b ; |
| 2607 | output stg1_rdp_io_clk_stop_out_c1b ; |
| 2608 | output stg1_rtx_io_clk_stop_out_c1b ; |
| 2609 | output stg1_sii_clk_stop_out_c1b ; |
| 2610 | output stg1_sii_io_clk_stop_out_c1b ; |
| 2611 | output stg1_spc0_clk_stop_out_c1t ; |
| 2612 | output stg1_spc1_clk_stop_out_c1t ; |
| 2613 | output stg1_spc2_clk_stop_out_c1b ; |
| 2614 | output stg1_spc3_clk_stop_out_c1b ; |
| 2615 | output stg1_spc4_clk_stop_out_c1t ; |
| 2616 | output stg1_spc5_clk_stop_out_c1t ; |
| 2617 | output stg1_spc6_clk_stop_out_c1b ; |
| 2618 | output stg1_spc7_clk_stop_out_c1b ; |
| 2619 | output stg1_tds_io_clk_stop_out_c1b ; |
| 2620 | |
| 2621 | |
| 2622 | wire stg1_ccu_clk_stop ; |
| 2623 | wire stg1_ccu_io_clk_stop ; |
| 2624 | wire stg1_db1_clk_stop ; |
| 2625 | wire stg1_efu_clk_stop ; |
| 2626 | wire stg1_efu_io_clk_stop ; |
| 2627 | wire stg1_l2b6_clk_stop ; |
| 2628 | wire stg1_l2b7_clk_stop ; |
| 2629 | wire stg1_l2d6_clk_stop ; |
| 2630 | wire stg1_l2t4_clk_stop ; |
| 2631 | wire stg1_l2t6_clk_stop ; |
| 2632 | wire stg1_mcu2_clk_stop ; |
| 2633 | wire stg1_mcu2_dr_clk_stop ; |
| 2634 | wire stg1_mcu2_io_clk_stop ; |
| 2635 | wire stg1_mcu3_clk_stop ; |
| 2636 | wire stg1_mcu3_dr_clk_stop ; |
| 2637 | wire stg1_mcu3_io_clk_stop ; |
| 2638 | wire stg1_rst_clk_stop ; |
| 2639 | wire stg1_rst_io_clk_stop ; |
| 2640 | wire stg1_sio_clk_stop ; |
| 2641 | wire stg1_sio_io_clk_stop ; |
| 2642 | |
| 2643 | wire [1:0] unused; |
| 2644 | wire [1:0] unused_1; |
| 2645 | wire [1:0] unused_2; |
| 2646 | wire unused_3; |
| 2647 | wire unused_4; |
| 2648 | wire [1:0] unused_5; |
| 2649 | wire [12:0] unused_6; |
| 2650 | wire [5:0] unused_7; |
| 2651 | |
| 2652 | |
| 2653 | // ordered pairs (set 0) |
| 2654 | n2_clk_gl_cc_stage_17s1 xtcu_m0_0 ( |
| 2655 | .stg1_out ( {stg1_ccx_clk_stop_out_c1b, |
| 2656 | stg1_db0_clk_stop_out_c1b, stg1_dmu_io_clk_stop_out_c1b, |
| 2657 | stg1_l2b0_clk_stop_out_c1t, stg1_l2b1_clk_stop_out_c1t, |
| 2658 | stg1_l2b2_clk_stop_out_c1b, stg1_l2b3_clk_stop_out_c1b, |
| 2659 | stg1_l2b4_clk_stop_out_c1t, stg1_l2b5_clk_stop_out_c1t, |
| 2660 | stg1_l2d0_clk_stop_out_c1t, stg1_l2d1_clk_stop_out_c1t, |
| 2661 | stg1_l2d2_clk_stop_out_c1b, stg1_l2d3_clk_stop_out_c1b, |
| 2662 | stg1_l2d4_clk_stop_out_c1t, stg1_l2d5_clk_stop_out_c1t, |
| 2663 | stg1_l2d7_clk_stop_out_c1b, stg1_l2t0_clk_stop_out_c1t} ), |
| 2664 | .stg0_in ( {tcu_ccx_clk_stop, |
| 2665 | tcu_db0_clk_stop, tcu_dmu_io_clk_stop, |
| 2666 | tcu_l2b0_clk_stop, tcu_l2b1_clk_stop, |
| 2667 | tcu_l2b2_clk_stop, tcu_l2b3_clk_stop, |
| 2668 | tcu_l2b4_clk_stop, tcu_l2b5_clk_stop, |
| 2669 | tcu_l2d0_clk_stop, tcu_l2d1_clk_stop, |
| 2670 | tcu_l2d2_clk_stop, tcu_l2d3_clk_stop, |
| 2671 | tcu_l2d4_clk_stop, tcu_l2d5_clk_stop, |
| 2672 | tcu_l2d7_clk_stop, tcu_l2t0_clk_stop} ), |
| 2673 | .gclk (gclk_in) |
| 2674 | ); |
| 2675 | |
| 2676 | // ordered pairs (set 1) |
| 2677 | n2_clk_gl_cc_stage_17s1 xtcu_m0_1 ( |
| 2678 | .stg1_out ( {unused_5, stg1_l2t1_clk_stop_out_c1t, |
| 2679 | stg1_l2t2_clk_stop_out_c1b, stg1_l2t3_clk_stop_out_c1b, |
| 2680 | stg1_l2t5_clk_stop_out_c1t, stg1_l2t7_clk_stop_out_c1b, |
| 2681 | stg1_mac_io_clk_stop_out_c1b, stg1_mcu0_clk_stop_out_c1t, |
| 2682 | // stg1_mcu0_dr_clk_stop_out_c1t, |
| 2683 | stg1_mcu0_io_clk_stop_out_c1t, |
| 2684 | stg1_mcu1_clk_stop_out_c1t, // stg1_mcu1_dr_clk_stop_out_c1t, |
| 2685 | stg1_mcu1_io_clk_stop_out_c1t, stg1_mio_clk_stop_out_c1t, |
| 2686 | stg1_ncu_clk_stop_out_c1b, stg1_ncu_io_clk_stop_out_c1b, |
| 2687 | stg1_peu_io_clk_stop_out_c1b, stg1_rdp_io_clk_stop_out_c1b} ), |
| 2688 | .stg0_in ( {2'b0, tcu_l2t1_clk_stop, |
| 2689 | tcu_l2t2_clk_stop, tcu_l2t3_clk_stop, |
| 2690 | tcu_l2t5_clk_stop, tcu_l2t7_clk_stop, |
| 2691 | tcu_mac_io_clk_stop, tcu_mcu0_clk_stop, |
| 2692 | // tcu_mcu0_dr_clk_stop, |
| 2693 | tcu_mcu0_io_clk_stop, |
| 2694 | tcu_mcu1_clk_stop, // tcu_mcu1_dr_clk_stop, |
| 2695 | tcu_mcu1_io_clk_stop, tcu_mio_clk_stop, |
| 2696 | tcu_ncu_clk_stop, tcu_ncu_io_clk_stop, |
| 2697 | tcu_peu_io_clk_stop, tcu_rdp_io_clk_stop} ), |
| 2698 | .gclk (gclk_in) |
| 2699 | ); |
| 2700 | |
| 2701 | |
| 2702 | // ordered pairs (set 2) - last 5 will be finalized |
| 2703 | n2_clk_gl_cc_stage_17s1 xtcu_m0_2 ( |
| 2704 | .stg1_out ({stg1_rtx_io_clk_stop_out_c1b, |
| 2705 | stg1_sii_clk_stop_out_c1b, stg1_sii_io_clk_stop_out_c1b, |
| 2706 | stg1_spc0_clk_stop_out_c1t, stg1_spc1_clk_stop_out_c1t, |
| 2707 | stg1_spc2_clk_stop_out_c1b, stg1_spc3_clk_stop_out_c1b, |
| 2708 | stg1_spc4_clk_stop_out_c1t, stg1_spc5_clk_stop_out_c1t, |
| 2709 | stg1_spc6_clk_stop_out_c1b, stg1_spc7_clk_stop_out_c1b, |
| 2710 | stg1_tds_io_clk_stop_out_c1b, stg1_ccu_clk_stop, |
| 2711 | stg1_ccu_io_clk_stop, stg1_db1_clk_stop, |
| 2712 | stg1_efu_clk_stop, stg1_efu_io_clk_stop} ), |
| 2713 | .stg0_in ({tcu_rtx_io_clk_stop, |
| 2714 | tcu_sii_clk_stop, tcu_sii_io_clk_stop, |
| 2715 | tcu_spc0_clk_stop, tcu_spc1_clk_stop, |
| 2716 | tcu_spc2_clk_stop, tcu_spc3_clk_stop, |
| 2717 | tcu_spc4_clk_stop, tcu_spc5_clk_stop, |
| 2718 | tcu_spc6_clk_stop, tcu_spc7_clk_stop, |
| 2719 | tcu_tds_io_clk_stop, tcu_ccu_clk_stop, |
| 2720 | tcu_ccu_io_clk_stop, tcu_db1_clk_stop, |
| 2721 | tcu_efu_clk_stop, tcu_efu_io_clk_stop} ), |
| 2722 | .gclk (gclk_in) |
| 2723 | ); |
| 2724 | |
| 2725 | |
| 2726 | // ordered pairs (set 3) |
| 2727 | n2_clk_gl_cc_stage_17s1 xtcu_m0_3 ( |
| 2728 | .stg1_out ({unused, unused_1, stg1_l2b6_clk_stop, |
| 2729 | stg1_l2b7_clk_stop, stg1_l2d6_clk_stop, |
| 2730 | stg1_l2t4_clk_stop, stg1_l2t6_clk_stop, |
| 2731 | stg1_mcu2_clk_stop, // stg1_mcu2_dr_clk_stop, |
| 2732 | stg1_mcu2_io_clk_stop, stg1_mcu3_clk_stop, |
| 2733 | // stg1_mcu3_dr_clk_stop, |
| 2734 | stg1_mcu3_io_clk_stop, |
| 2735 | stg1_rst_clk_stop, stg1_rst_io_clk_stop, |
| 2736 | stg1_sio_clk_stop, stg1_sio_io_clk_stop} ), |
| 2737 | .stg0_in ({4'b0, tcu_l2b6_clk_stop, |
| 2738 | tcu_l2b7_clk_stop, tcu_l2d6_clk_stop, |
| 2739 | tcu_l2t4_clk_stop, tcu_l2t6_clk_stop, |
| 2740 | tcu_mcu2_clk_stop, // tcu_mcu2_dr_clk_stop, |
| 2741 | tcu_mcu2_io_clk_stop, tcu_mcu3_clk_stop, |
| 2742 | // tcu_mcu3_dr_clk_stop, |
| 2743 | tcu_mcu3_io_clk_stop, |
| 2744 | tcu_rst_clk_stop, tcu_rst_io_clk_stop, |
| 2745 | tcu_sio_clk_stop, tcu_sio_io_clk_stop} ), |
| 2746 | .gclk (gclk_in) |
| 2747 | ); |
| 2748 | |
| 2749 | |
| 2750 | // ordered pairs (set 4) |
| 2751 | n2_clk_gl_cc_stage_4s4 xtcu_m0_4 ( |
| 2752 | .stg1_in ({ |
| 2753 | stg1_ccu_clk_stop, stg1_ccu_io_clk_stop, |
| 2754 | stg1_db1_clk_stop, stg1_efu_clk_stop}), |
| 2755 | .stg5_out ({ |
| 2756 | gl_ccu_clk_stop, gl_ccu_io_clk_stop, |
| 2757 | gl_db1_clk_stop, gl_efu_clk_stop}), |
| 2758 | .gclk (gclk_in) |
| 2759 | ); |
| 2760 | |
| 2761 | // ordered pairs (set 5) |
| 2762 | n2_clk_gl_cc_stage_4s4 xtcu_m0_5 ( |
| 2763 | .stg1_in ({ |
| 2764 | stg1_efu_io_clk_stop, stg1_l2b6_clk_stop, |
| 2765 | stg1_l2b7_clk_stop, stg1_l2d6_clk_stop}), |
| 2766 | .stg5_out ({ |
| 2767 | gl_efu_io_clk_stop, gl_l2b6_clk_stop, |
| 2768 | gl_l2b7_clk_stop, gl_l2d6_clk_stop}), |
| 2769 | .gclk (gclk_in) |
| 2770 | ); |
| 2771 | |
| 2772 | |
| 2773 | // ordered pairs (set 6) |
| 2774 | n2_clk_gl_cc_stage_4s4 xtcu_m0_6 ( |
| 2775 | .stg1_in ({1'b0, |
| 2776 | stg1_l2t4_clk_stop, stg1_l2t6_clk_stop, |
| 2777 | stg1_mcu2_clk_stop // , stg1_mcu2_dr_clk_stop |
| 2778 | }), |
| 2779 | .stg5_out ({unused_3, |
| 2780 | gl_l2t4_clk_stop, gl_l2t6_clk_stop, |
| 2781 | gl_mcu2_clk_stop // , gl_mcu2_dr_clk_stop |
| 2782 | }), |
| 2783 | .gclk (gclk_in) |
| 2784 | ); |
| 2785 | |
| 2786 | |
| 2787 | // ordered pairs (set 7) |
| 2788 | n2_clk_gl_cc_stage_4s4 xtcu_m0_7 ( |
| 2789 | .stg1_in ({ 1'b0, |
| 2790 | stg1_mcu2_io_clk_stop, stg1_mcu3_clk_stop, |
| 2791 | // stg1_mcu3_dr_clk_stop, |
| 2792 | stg1_mcu3_io_clk_stop}), |
| 2793 | .stg5_out ({ unused_4, |
| 2794 | gl_mcu2_io_clk_stop, gl_mcu3_clk_stop, |
| 2795 | // gl_mcu3_dr_clk_stop, |
| 2796 | gl_mcu3_io_clk_stop}), |
| 2797 | .gclk (gclk_in) |
| 2798 | ); |
| 2799 | |
| 2800 | // ordered pairs (set 8) |
| 2801 | n2_clk_gl_cc_stage_4s4 xtcu_m0_8 ( |
| 2802 | .stg1_in ({ |
| 2803 | stg1_rst_clk_stop, stg1_rst_io_clk_stop, |
| 2804 | stg1_sio_clk_stop, stg1_sio_io_clk_stop}), |
| 2805 | .stg5_out ({ |
| 2806 | gl_rst_clk_stop, gl_rst_io_clk_stop, |
| 2807 | gl_sio_clk_stop, gl_sio_io_clk_stop}), |
| 2808 | .gclk (gclk_in) |
| 2809 | ); |
| 2810 | |
| 2811 | |
| 2812 | // ordered pairs (set 9) -- FOR INT6.1 // stage 4 dr_stop signals once |
| 2813 | n2_clk_gl_cc_stage_17s1 xtcu_m0_9 ( |
| 2814 | .gclk (dr_gclk_in), |
| 2815 | .stg0_in ({13'b0, tcu_mcu0_dr_clk_stop, tcu_mcu1_dr_clk_stop, |
| 2816 | tcu_mcu2_dr_clk_stop, tcu_mcu3_dr_clk_stop}), |
| 2817 | .stg1_out ({unused_6,stg1_mcu0_dr_clk_stop_out_c1t, stg1_mcu1_dr_clk_stop_out_c1t, |
| 2818 | stg1_mcu2_dr_clk_stop, stg1_mcu3_dr_clk_stop}) |
| 2819 | ); |
| 2820 | |
| 2821 | // ordered pairs (set 10) -- FOR INT6.1 // stage 2 dr_stop signals twice |
| 2822 | n2_clk_gl_cc_stage_8s2 xtcu_m0_10 ( |
| 2823 | .gclk (dr_gclk_in), |
| 2824 | .stg3_in ({6'b0, stg1_mcu2_dr_clk_stop, stg1_mcu3_dr_clk_stop}), |
| 2825 | .stg5_out ({unused_7, gl_mcu2_dr_clk_stop, gl_mcu3_dr_clk_stop}) |
| 2826 | ); |
| 2827 | |
| 2828 | |
| 2829 | endmodule |
| 2830 | |
| 2831 | |
| 2832 | // ************************************************************************ |
| 2833 | // 5 module n2_clk_gl_cc_stage_17s1 (17x1) |
| 2834 | // ************************************************************************ |
| 2835 | |
| 2836 | module n2_clk_gl_cc_stage_17s1 (stg0_in ,stg1_out ,gclk ); |
| 2837 | output [16:0] stg1_out ; |
| 2838 | input [16:0] stg0_in ; |
| 2839 | input gclk ; |
| 2840 | |
| 2841 | wire [16:0] stg1_out ; |
| 2842 | wire [16:0] stg0_in ; |
| 2843 | wire gclk ; |
| 2844 | |
| 2845 | reg [16:0] q1; |
| 2846 | |
| 2847 | always @(posedge gclk) begin |
| 2848 | q1 <= stg0_in; |
| 2849 | end |
| 2850 | |
| 2851 | //ifdef FLOP_STAGES_ON |
| 2852 | assign stg1_out = q1; |
| 2853 | //else |
| 2854 | // assign stg1_out = stg0_in; |
| 2855 | //endif |
| 2856 | |
| 2857 | |
| 2858 | endmodule |
| 2859 | |
| 2860 | |
| 2861 | |
| 2862 | // ************************************************************************ |
| 2863 | // 6 module n2_clk_gl_cc_stg_c1t_s1_0 (17x1) |
| 2864 | // ************************************************************************ |
| 2865 | |
| 2866 | module n2_clk_gl_cc_stg_c1t_s1_0 (stg2_l2_por_out_c1t , |
| 2867 | stg2_l2b1_clk_stop_out_c1t ,stg2_l2t0_clk_stop_out_c1t , |
| 2868 | stg2_spc5_clk_stop_out_c1t ,stg2_spc0_clk_stop_out_c1t , |
| 2869 | stg2_dr_sync_en_out_c1t ,stg2_mio_io2x_sync_en_out_c1t , |
| 2870 | stg2_l2_wmr_out_c1t ,stg2_cmp_io_sync_en_out_c1t , |
| 2871 | stg2_spc1_clk_stop_out_c1t ,stg1_spc5_clk_stop_in_c1t , |
| 2872 | stg2_io_cmp_sync_en_out_c1t ,stg2_io_out_out_c1t ,gclk_l2b5 , |
| 2873 | stg2_l2t1_clk_stop_out_c1t ,stg2_l2t5_clk_stop_out_c1t , |
| 2874 | stg2_l2b0_clk_stop_out_c1t ,stg2_l2d1_clk_stop_out_c1t , |
| 2875 | stg2_l2d0_clk_stop_out_c1t ,stg1_l2b1_clk_stop_in_c1t , |
| 2876 | stg1_cmp_io_sync_en_in_c1t ,stg1_mio_io2x_sync_en_in_c1t , |
| 2877 | stg1_l2_wmr_in_c1t ,stg1_l2_por_in_c1t ,stg1_spc1_clk_stop_in_c1t , |
| 2878 | stg1_l2b0_clk_stop_in_c1t ,stg1_l2t5_clk_stop_in_c1t , |
| 2879 | stg1_l2t1_clk_stop_in_c1t ,stg1_l2d1_clk_stop_in_c1t , |
| 2880 | stg1_io_cmp_sync_en_in_c1t ,stg1_io_out_in_c1t , |
| 2881 | stg1_l2d0_clk_stop_in_c1t ,stg1_l2t0_clk_stop_in_c1t , |
| 2882 | stg1_dr_sync_en_in_c1t ,stg1_spc0_clk_stop_in_c1t ); |
| 2883 | |
| 2884 | |
| 2885 | |
| 2886 | input gclk_l2b5 ; |
| 2887 | input stg1_cmp_io_sync_en_in_c1t ; |
| 2888 | input stg1_dr_sync_en_in_c1t ; |
| 2889 | input stg1_io_cmp_sync_en_in_c1t ; |
| 2890 | input stg1_io_out_in_c1t ; |
| 2891 | input stg1_l2_por_in_c1t ; |
| 2892 | input stg1_l2_wmr_in_c1t ; |
| 2893 | input stg1_l2b0_clk_stop_in_c1t ; |
| 2894 | input stg1_l2b1_clk_stop_in_c1t ; |
| 2895 | input stg1_l2d0_clk_stop_in_c1t ; |
| 2896 | input stg1_l2d1_clk_stop_in_c1t ; |
| 2897 | input stg1_l2t0_clk_stop_in_c1t ; |
| 2898 | input stg1_l2t1_clk_stop_in_c1t ; |
| 2899 | input stg1_l2t5_clk_stop_in_c1t ; |
| 2900 | input stg1_mio_io2x_sync_en_in_c1t ; |
| 2901 | input stg1_spc0_clk_stop_in_c1t ; |
| 2902 | input stg1_spc1_clk_stop_in_c1t ; |
| 2903 | input stg1_spc5_clk_stop_in_c1t ; |
| 2904 | output stg2_cmp_io_sync_en_out_c1t ; |
| 2905 | output stg2_dr_sync_en_out_c1t ; |
| 2906 | output stg2_io_cmp_sync_en_out_c1t ; |
| 2907 | output stg2_io_out_out_c1t ; |
| 2908 | output stg2_l2_por_out_c1t ; |
| 2909 | output stg2_l2_wmr_out_c1t ; |
| 2910 | output stg2_l2b0_clk_stop_out_c1t ; |
| 2911 | output stg2_l2b1_clk_stop_out_c1t ; |
| 2912 | output stg2_l2d0_clk_stop_out_c1t ; |
| 2913 | output stg2_l2d1_clk_stop_out_c1t ; |
| 2914 | output stg2_l2t0_clk_stop_out_c1t ; |
| 2915 | output stg2_l2t1_clk_stop_out_c1t ; |
| 2916 | output stg2_l2t5_clk_stop_out_c1t ; |
| 2917 | output stg2_mio_io2x_sync_en_out_c1t ; |
| 2918 | output stg2_spc0_clk_stop_out_c1t ; |
| 2919 | output stg2_spc1_clk_stop_out_c1t ; |
| 2920 | output stg2_spc5_clk_stop_out_c1t ; |
| 2921 | |
| 2922 | |
| 2923 | |
| 2924 | n2_clk_gl_cc_stage_17s1 xc1t_s1_0 ( |
| 2925 | .stg0_in ({stg1_l2t5_clk_stop_in_c1t , |
| 2926 | stg1_l2t1_clk_stop_in_c1t ,stg1_l2t0_clk_stop_in_c1t , |
| 2927 | stg1_l2b1_clk_stop_in_c1t ,stg1_l2b0_clk_stop_in_c1t , |
| 2928 | stg1_l2d1_clk_stop_in_c1t ,stg1_l2d0_clk_stop_in_c1t , |
| 2929 | stg1_spc5_clk_stop_in_c1t ,stg1_spc1_clk_stop_in_c1t , |
| 2930 | stg1_spc0_clk_stop_in_c1t ,stg1_l2_por_in_c1t , |
| 2931 | stg1_l2_wmr_in_c1t ,stg1_io_out_in_c1t , |
| 2932 | stg1_dr_sync_en_in_c1t ,stg1_mio_io2x_sync_en_in_c1t , |
| 2933 | stg1_io_cmp_sync_en_in_c1t ,stg1_cmp_io_sync_en_in_c1t } ), |
| 2934 | .stg1_out ({stg2_l2t5_clk_stop_out_c1t , |
| 2935 | stg2_l2t1_clk_stop_out_c1t ,stg2_l2t0_clk_stop_out_c1t , |
| 2936 | stg2_l2b1_clk_stop_out_c1t ,stg2_l2b0_clk_stop_out_c1t , |
| 2937 | stg2_l2d1_clk_stop_out_c1t ,stg2_l2d0_clk_stop_out_c1t , |
| 2938 | stg2_spc5_clk_stop_out_c1t ,stg2_spc1_clk_stop_out_c1t , |
| 2939 | stg2_spc0_clk_stop_out_c1t ,stg2_l2_por_out_c1t , |
| 2940 | stg2_l2_wmr_out_c1t ,stg2_io_out_out_c1t , |
| 2941 | stg2_dr_sync_en_out_c1t ,stg2_mio_io2x_sync_en_out_c1t , |
| 2942 | stg2_io_cmp_sync_en_out_c1t ,stg2_cmp_io_sync_en_out_c1t } ) |
| 2943 | , |
| 2944 | .gclk (gclk_l2b5 ) ); |
| 2945 | endmodule |
| 2946 | |
| 2947 | |
| 2948 | |
| 2949 | // ************************************************************************ |
| 2950 | // 7 module n2_clk_gl_cc_stage_4s4 (4x4) |
| 2951 | // ************************************************************************ |
| 2952 | |
| 2953 | module n2_clk_gl_cc_stage_4s4 (stg1_in ,stg5_out ,gclk ); |
| 2954 | |
| 2955 | output [3:0] stg5_out ; |
| 2956 | input [3:0] stg1_in ; |
| 2957 | input gclk ; |
| 2958 | |
| 2959 | wire [3:0] stg5_out ; |
| 2960 | wire [3:0] stg1_in ; |
| 2961 | wire gclk ; |
| 2962 | |
| 2963 | reg [3:0] q1; |
| 2964 | reg [3:0] q2; |
| 2965 | reg [3:0] q3; |
| 2966 | reg [3:0] q4; |
| 2967 | |
| 2968 | always @(posedge gclk) begin |
| 2969 | q1 <= stg1_in; |
| 2970 | q2 <= q1; |
| 2971 | q3 <= q2; |
| 2972 | q4 <= q3; |
| 2973 | end |
| 2974 | |
| 2975 | //ifdef FLOP_STAGES_ON |
| 2976 | assign stg5_out = q4; |
| 2977 | //else |
| 2978 | // assign stg5_out = stg1_in; |
| 2979 | //endif |
| 2980 | |
| 2981 | |
| 2982 | endmodule |
| 2983 | |
| 2984 | |
| 2985 | |
| 2986 | // ************************************************************************ |
| 2987 | // 8 module n2_clk_gl_cc_stg_c1t_s4_0 (4x4) |
| 2988 | // ************************************************************************ |
| 2989 | |
| 2990 | module n2_clk_gl_cc_stg_c1t_s4_0 (gl_mio_io2x_sync_en_c1t ,gl_l2_wmr_c1t |
| 2991 | ,stg1_io_cmp_sync_en_in_c1t ,stg1_cmp_io_sync_en_in_c1t, |
| 2992 | stg1_mio_io2x_sync_en_in_c1t,stg1_l2_wmr_in_c1t , |
| 2993 | gl_io_cmp_sync_en_c1t ,gclk_spc4 ,gl_cmp_io_sync_en_c1t ); |
| 2994 | |
| 2995 | |
| 2996 | |
| 2997 | input gclk_spc4 ; |
| 2998 | input stg1_cmp_io_sync_en_in_c1t; |
| 2999 | input stg1_io_cmp_sync_en_in_c1t ; |
| 3000 | input stg1_l2_wmr_in_c1t ; |
| 3001 | input stg1_mio_io2x_sync_en_in_c1t; |
| 3002 | output gl_cmp_io_sync_en_c1t ; |
| 3003 | output gl_io_cmp_sync_en_c1t ; |
| 3004 | output gl_l2_wmr_c1t ; |
| 3005 | output gl_mio_io2x_sync_en_c1t ; |
| 3006 | |
| 3007 | |
| 3008 | n2_clk_gl_cc_stage_4s4 x6 ( |
| 3009 | .stg1_in ({stg1_l2_wmr_in_c1t ,stg1_mio_io2x_sync_en_in_c1t, |
| 3010 | stg1_io_cmp_sync_en_in_c1t ,stg1_cmp_io_sync_en_in_c1t} ), |
| 3011 | .stg5_out ({gl_l2_wmr_c1t ,gl_mio_io2x_sync_en_c1t, |
| 3012 | gl_io_cmp_sync_en_c1t ,gl_cmp_io_sync_en_c1t } ), |
| 3013 | .gclk (gclk_spc4 ) ); |
| 3014 | endmodule |
| 3015 | |
| 3016 | |
| 3017 | |
| 3018 | // ************************************************************************ |
| 3019 | // 9 module n2_clk_gl_cc_stg_c1t_s4_1 (3x4) |
| 3020 | // ************************************************************************ |
| 3021 | |
| 3022 | module n2_clk_gl_cc_stg_c1t_s4_1 (gl_l2d4_clk_stop ,gclk_l2b4 , |
| 3023 | stg1_l2_por_in_c1t ,stg1_l2d4_clk_stop_in_c1t ,gl_l2_por_c1t , |
| 3024 | stg1_l2b4_clk_stop_in_c1t ,gl_l2b4_clk_stop, stg1_spc4_clk_stop_in_c1t, gl_spc4_clk_stop ); |
| 3025 | |
| 3026 | |
| 3027 | |
| 3028 | input gclk_l2b4 ; |
| 3029 | input stg1_spc4_clk_stop_in_c1t ; |
| 3030 | input stg1_l2_por_in_c1t ; |
| 3031 | input stg1_l2b4_clk_stop_in_c1t ; |
| 3032 | input stg1_l2d4_clk_stop_in_c1t ; |
| 3033 | output gl_spc4_clk_stop ; |
| 3034 | output gl_l2_por_c1t ; |
| 3035 | output gl_l2b4_clk_stop ; |
| 3036 | output gl_l2d4_clk_stop ; |
| 3037 | |
| 3038 | |
| 3039 | n2_clk_gl_cc_stage_4s4 xc1t_s4_1 ( |
| 3040 | .stg1_in ({stg1_spc4_clk_stop_in_c1t, stg1_l2b4_clk_stop_in_c1t , |
| 3041 | stg1_l2d4_clk_stop_in_c1t ,stg1_l2_por_in_c1t } ), |
| 3042 | .stg5_out ({gl_spc4_clk_stop,gl_l2b4_clk_stop , |
| 3043 | gl_l2d4_clk_stop ,gl_l2_por_c1t } ), |
| 3044 | .gclk (gclk_l2b4 ) ); |
| 3045 | endmodule |
| 3046 | |
| 3047 | |
| 3048 | |
| 3049 | // ************************************************************************ |
| 3050 | // 10 module n2_clk_gl_cc_stg_c1t_s4_2 (3x4) |
| 3051 | // ************************************************************************ |
| 3052 | // |
| 3053 | module n2_clk_gl_cc_stg_c1t_s4_2 (gl_l2d5_clk_stop , |
| 3054 | gl_l2b5_clk_stop ,stg1_l2d5_clk_stop_in_c1t , |
| 3055 | stg1_mio_clk_stop_in_c1t ,gl_mio_clk_stop_c1t , |
| 3056 | stg1_l2b5_clk_stop_in_c1t ,gclk_l2d5 ); |
| 3057 | |
| 3058 | |
| 3059 | input gclk_l2d5 ; |
| 3060 | input stg1_l2b5_clk_stop_in_c1t ; |
| 3061 | input stg1_l2d5_clk_stop_in_c1t ; |
| 3062 | input stg1_mio_clk_stop_in_c1t ; |
| 3063 | output gl_l2b5_clk_stop ; |
| 3064 | output gl_l2d5_clk_stop ; |
| 3065 | output gl_mio_clk_stop_c1t ; |
| 3066 | |
| 3067 | wire net51; |
| 3068 | |
| 3069 | n2_clk_gl_cc_stage_4s4 xc1t_s4_2 ( |
| 3070 | .stg1_in ({1'b0,stg1_l2b5_clk_stop_in_c1t , |
| 3071 | stg1_l2d5_clk_stop_in_c1t ,stg1_mio_clk_stop_in_c1t } ), |
| 3072 | .stg5_out ({net51 ,gl_l2b5_clk_stop , |
| 3073 | gl_l2d5_clk_stop,gl_mio_clk_stop_c1t } ), |
| 3074 | .gclk (gclk_l2d5 ) ); |
| 3075 | endmodule |
| 3076 | |
| 3077 | |
| 3078 | // ************************************************************************ |
| 3079 | // 11 module n2_clk_gl_cc_stg_c1t_s1_1 (7x1) |
| 3080 | // ************************************************************************ |
| 3081 | |
| 3082 | module n2_clk_gl_cc_stg_c1t_s1_1 ( // stg2_mcu1_dr_clk_stop_out_c1t , |
| 3083 | // stg1_mcu0_dr_clk_stop_in_c1t , |
| 3084 | stg1_mcu0_io_clk_stop_in_c1t , |
| 3085 | stg1_mcu0_clk_stop_in_c1t , // stg1_mcu1_dr_clk_stop_in_c1t , |
| 3086 | gclk_l2t4 , |
| 3087 | stg1_mcu1_clk_stop_in_c1t ,stg1_mcu1_io_clk_stop_in_c1t , |
| 3088 | // stg2_mcu0_dr_clk_stop_out_c1t , |
| 3089 | stg1_mio_clk_stop_in_c1t , |
| 3090 | stg2_mcu0_io_clk_stop_out_c1t ,stg2_mcu0_clk_stop_out_c1t , |
| 3091 | stg2_mio_clk_stop_out_c1t ,stg2_mcu1_io_clk_stop_out_c1t , |
| 3092 | stg2_mcu1_clk_stop_out_c1t ); |
| 3093 | |
| 3094 | |
| 3095 | |
| 3096 | input gclk_l2t4 ; |
| 3097 | input stg1_mcu0_clk_stop_in_c1t ; |
| 3098 | // input stg1_mcu0_dr_clk_stop_in_c1t ; |
| 3099 | input stg1_mcu0_io_clk_stop_in_c1t ; |
| 3100 | input stg1_mcu1_clk_stop_in_c1t ; |
| 3101 | // input stg1_mcu1_dr_clk_stop_in_c1t ; |
| 3102 | input stg1_mcu1_io_clk_stop_in_c1t ; |
| 3103 | input stg1_mio_clk_stop_in_c1t ; |
| 3104 | output stg2_mcu0_clk_stop_out_c1t ; |
| 3105 | // output stg2_mcu0_dr_clk_stop_out_c1t ; |
| 3106 | output stg2_mcu0_io_clk_stop_out_c1t ; |
| 3107 | output stg2_mcu1_clk_stop_out_c1t ; |
| 3108 | // output stg2_mcu1_dr_clk_stop_out_c1t ; |
| 3109 | output stg2_mcu1_io_clk_stop_out_c1t ; |
| 3110 | output stg2_mio_clk_stop_out_c1t ; |
| 3111 | |
| 3112 | wire [11:0] unused; |
| 3113 | |
| 3114 | n2_clk_gl_cc_stage_17s1 xc1t_s1_1 ( |
| 3115 | .stg0_in ({12'b0,stg1_mio_clk_stop_in_c1t , |
| 3116 | // stg1_mcu1_dr_clk_stop_in_c1t ,stg1_mcu0_dr_clk_stop_in_c1t , |
| 3117 | stg1_mcu1_io_clk_stop_in_c1t ,stg1_mcu0_io_clk_stop_in_c1t , |
| 3118 | stg1_mcu1_clk_stop_in_c1t ,stg1_mcu0_clk_stop_in_c1t } ), |
| 3119 | .stg1_out ({unused,stg2_mio_clk_stop_out_c1t , |
| 3120 | // stg2_mcu1_dr_clk_stop_out_c1t ,stg2_mcu0_dr_clk_stop_out_c1t, |
| 3121 | stg2_mcu1_io_clk_stop_out_c1t , |
| 3122 | stg2_mcu0_io_clk_stop_out_c1t ,stg2_mcu1_clk_stop_out_c1t , |
| 3123 | stg2_mcu0_clk_stop_out_c1t } ), |
| 3124 | .gclk (gclk_l2t4 ) ); |
| 3125 | endmodule |
| 3126 | |
| 3127 | |
| 3128 | // ************************************************************************ |
| 3129 | // 12 module n2_clk_gl_cc_stg_c1b_s4_0 (4x4) |
| 3130 | // ************************************************************************ |
| 3131 | |
| 3132 | module n2_clk_gl_cc_stg_c1b_s4_0 (gl_l2_wmr_c1b ,gclk_l2b6 , |
| 3133 | gl_io_cmp_sync_en_c1b ,stg1_io_cmp_sync_en_in_c1b , |
| 3134 | stg1_cmp_io_sync_en_in_c1b , |
| 3135 | stg1_l2_por_in_c1b, gl_l2_por_c1b, // added for int6.1 |
| 3136 | gl_cmp_io_sync_en_c1b ,stg1_l2_wmr_in_c1b |
| 3137 | ); |
| 3138 | |
| 3139 | |
| 3140 | |
| 3141 | input gclk_l2b6 ; |
| 3142 | |
| 3143 | input stg1_cmp_io_sync_en_in_c1b ; |
| 3144 | input stg1_io_cmp_sync_en_in_c1b ; |
| 3145 | // input stg1_l2_por_in_c1b ; // removed prior to int6.1 |
| 3146 | input stg1_l2_wmr_in_c1b ; |
| 3147 | input stg1_l2_por_in_c1b ; // added for int6.1 |
| 3148 | |
| 3149 | output gl_cmp_io_sync_en_c1b ; |
| 3150 | output gl_io_cmp_sync_en_c1b ; |
| 3151 | output gl_l2_wmr_c1b ; |
| 3152 | // output gl_mio_io2x_sync_en_c1b ; // removed prior to int6.1 |
| 3153 | output gl_l2_por_c1b ; // added for int6.1 |
| 3154 | |
| 3155 | |
| 3156 | n2_clk_gl_cc_stage_4s4 xc1b_s4_0 ( |
| 3157 | .stg1_in ( { stg1_cmp_io_sync_en_in_c1b , |
| 3158 | stg1_io_cmp_sync_en_in_c1b , |
| 3159 | stg1_l2_por_in_c1b, // added for int6.1 |
| 3160 | stg1_l2_wmr_in_c1b } ), |
| 3161 | .stg5_out ({ gl_cmp_io_sync_en_c1b , |
| 3162 | gl_io_cmp_sync_en_c1b , |
| 3163 | gl_l2_por_c1b, // added for int6.1 |
| 3164 | gl_l2_wmr_c1b } ), |
| 3165 | .gclk (gclk_l2b6 ) ); |
| 3166 | endmodule |
| 3167 | |
| 3168 | |
| 3169 | // ************************************************************************ |
| 3170 | // 13 module n2_clk_gl_cc_stg_c1b_s4_1 (4x4) |
| 3171 | // ************************************************************************ |
| 3172 | |
| 3173 | module n2_clk_gl_cc_stg_c1b_s4_1 (gclk_l2d6 , |
| 3174 | gl_l2d7_clk_stop ,stg1_spc6_clk_stop_in_c1b, |
| 3175 | gl_spc6_clk_stop ,stg1_l2d7_clk_stop_in_c1b ); |
| 3176 | |
| 3177 | // n2_clk_gl_cc_stg_c1b_s4_1 (spare2_c1b ,gclk_l2b4 ,spare3_c1b , |
| 3178 | // spare2_c1b_in ,gl_l2d7_clk_stop ,stg1_spc6_clk_stop_c1t_in , |
| 3179 | // gl_spc6_clk_stop ,spare3_c1b_in ,stg1_l2d7_clk_stop_c1b_in ); |
| 3180 | |
| 3181 | |
| 3182 | |
| 3183 | input gclk_l2d6 ; |
| 3184 | // input spare2_c1b_in ; |
| 3185 | // input spare3_c1b_in ; |
| 3186 | input stg1_l2d7_clk_stop_in_c1b; |
| 3187 | input stg1_spc6_clk_stop_in_c1b; |
| 3188 | output gl_l2d7_clk_stop ; |
| 3189 | output gl_spc6_clk_stop ; |
| 3190 | // output spare2_c1b ; |
| 3191 | // output spare3_c1b ; |
| 3192 | |
| 3193 | |
| 3194 | /* |
| 3195 | n2_clk_gl_cc_stage_4s4 xc1b_s4_1 ( |
| 3196 | .stg1_in ({spare2_c1b_in ,stg1_l2d7_clk_stop_c1b_in , |
| 3197 | stg1_spc6_clk_stop_c1t_in ,spare3_c1b_in } ), |
| 3198 | .stg5_out ({spare2_c1b ,gl_l2d7_clk_stop , |
| 3199 | gl_spc6_clk_stop ,spare3_c1b } ), |
| 3200 | .gclk (gclk_l2b4 ) ); |
| 3201 | */ |
| 3202 | wire [1:0] unused; |
| 3203 | |
| 3204 | n2_clk_gl_cc_stage_4s4 xc1b_s4_1 ( |
| 3205 | .stg1_in ({2'b0, stg1_l2d7_clk_stop_in_c1b, |
| 3206 | stg1_spc6_clk_stop_in_c1b} ), |
| 3207 | .stg5_out ({unused,gl_l2d7_clk_stop , |
| 3208 | gl_spc6_clk_stop } ), |
| 3209 | .gclk (gclk_l2d6 ) ); |
| 3210 | |
| 3211 | endmodule |
| 3212 | |
| 3213 | |
| 3214 | // ************************************************************************ |
| 3215 | // 14 module n2_clk_gl_cc_stg_c1b_s4_2 (4x4) |
| 3216 | // ************************************************************************ |
| 3217 | |
| 3218 | module n2_clk_gl_cc_stg_c1b_s4_2 (gl_rdp_io_clk_stop , |
| 3219 | gl_rtx_io_clk_stop ,stg1_rdp_io_clk_stop_in_c1b , |
| 3220 | stg1_mac_io_clk_stop_in_c1b ,stg1_rtx_io_clk_stop_in_c1b , |
| 3221 | gl_mac_io_clk_stop ,stg1_tds_io_clk_stop_in_c1b ,gclk_spc6 , |
| 3222 | gl_tds_io_clk_stop ); |
| 3223 | |
| 3224 | input gclk_spc6 ; |
| 3225 | input stg1_mac_io_clk_stop_in_c1b ; |
| 3226 | input stg1_rdp_io_clk_stop_in_c1b ; |
| 3227 | input stg1_tds_io_clk_stop_in_c1b ; |
| 3228 | input stg1_rtx_io_clk_stop_in_c1b ; |
| 3229 | output gl_mac_io_clk_stop ; |
| 3230 | output gl_rdp_io_clk_stop ; |
| 3231 | output gl_tds_io_clk_stop ; |
| 3232 | output gl_rtx_io_clk_stop ; |
| 3233 | |
| 3234 | |
| 3235 | |
| 3236 | n2_clk_gl_cc_stage_4s4 xc1b_s4_2 ( |
| 3237 | .stg1_in ({stg1_rdp_io_clk_stop_in_c1b, stg1_tds_io_clk_stop_in_c1b, |
| 3238 | stg1_rtx_io_clk_stop_in_c1b, stg1_mac_io_clk_stop_in_c1b } ), |
| 3239 | .stg5_out ({gl_rdp_io_clk_stop ,gl_tds_io_clk_stop, |
| 3240 | gl_rtx_io_clk_stop ,gl_mac_io_clk_stop } ), |
| 3241 | .gclk (gclk_spc6 ) ); |
| 3242 | endmodule |
| 3243 | |
| 3244 | |
| 3245 | |
| 3246 | // ************************************************************************ |
| 3247 | // 15 module n2_clk_gl_cc_stg_c1b_s4_3 (4x4) |
| 3248 | // ************************************************************************ |
| 3249 | |
| 3250 | |
| 3251 | module n2_clk_gl_cc_stg_c1b_s4_3 (gl_io2x_out_c1b ,gl_io_out_c1b , |
| 3252 | stg1_io_out_in_c1b ,stg1_rst_niu_wmr_in_c1b ,stg1_rst_mac_in_c1b , |
| 3253 | stg1_io2x_out_in_c1b ,gl_rst_mac_c1b ,gclk_mac ,gl_rst_niu_wmr_c1b |
| 3254 | ); |
| 3255 | |
| 3256 | input gclk_mac ; |
| 3257 | input stg1_io2x_out_in_c1b ; |
| 3258 | input stg1_io_out_in_c1b ; |
| 3259 | input stg1_rst_mac_in_c1b ; |
| 3260 | input stg1_rst_niu_wmr_in_c1b ; |
| 3261 | output gl_io2x_out_c1b ; |
| 3262 | output gl_io_out_c1b ; |
| 3263 | output gl_rst_mac_c1b ; |
| 3264 | output gl_rst_niu_wmr_c1b ; |
| 3265 | |
| 3266 | |
| 3267 | |
| 3268 | n2_clk_gl_cc_stage_4s4 x35 ( |
| 3269 | .stg1_in ({stg1_io_out_in_c1b ,stg1_io2x_out_in_c1b , |
| 3270 | stg1_rst_mac_in_c1b ,stg1_rst_niu_wmr_in_c1b } ), |
| 3271 | .stg5_out ({gl_io_out_c1b ,gl_io2x_out_c1b ,gl_rst_mac_c1b , |
| 3272 | gl_rst_niu_wmr_c1b } ), |
| 3273 | .gclk (gclk_mac ) ); |
| 3274 | endmodule |
| 3275 | |
| 3276 | |
| 3277 | |
| 3278 | // ************************************************************************ |
| 3279 | // 16 module n2_clk_gl_cc_stg_c2b_s1_0 (17x1) |
| 3280 | // ************************************************************************ |
| 3281 | |
| 3282 | |
| 3283 | module n2_clk_gl_cc_stg_c2b_s1_0 (gclk_spc7 ,stg3_l2t2_clk_stop_out_c2b , |
| 3284 | stg3_l2t3_clk_stop_out_c2b ,stg2_l2t3_clk_stop_in_c2bz , |
| 3285 | stg3_io_cmp_sync_en_out_c2b ,stg3_io_out_out_c2b ,stg3_l2_wmr_out_c2b |
| 3286 | ,stg3_l2_por_out_c2b ,stg3_dmu_peu_por_out_c2b , |
| 3287 | stg3_dmu_peu_wmr_out_c2b ,stg3_spc2_clk_stop_out_c2b , |
| 3288 | stg3_spc3_clk_stop_out_c2b ,stg3_spc7_clk_stop_out_c2b , |
| 3289 | stg3_l2b2_clk_stop_out_c2b ,stg3_db0_clk_stop_out_c2b , |
| 3290 | stg3_l2d2_clk_stop_out_c2b ,stg3_l2d3_clk_stop_out_c2b , |
| 3291 | stg3_l2b3_clk_stop_out_c2b ,stg2_io_cmp_sync_en_in_c2b , |
| 3292 | stg2_io_out_in_c2b ,stg2_l2_wmr_in_c2b ,stg2_l2_por_in_c2b , |
| 3293 | stg2_dmu_peu_por_in_c2b ,stg2_dmu_peu_wmr_in_c2b , |
| 3294 | stg2_spc2_clk_stop_in_c2b ,stg2_spc3_clk_stop_in_c2b , |
| 3295 | stg2_spc7_clk_stop_in_c2b ,stg2_db0_clk_stop_in_c2b , |
| 3296 | stg2_l2d2_clk_stop_in_c2b ,stg2_l2d3_clk_stop_in_c2b , |
| 3297 | stg2_l2b2_clk_stop_in_c2b ,stg2_l2b3_clk_stop_in_c2b , |
| 3298 | stg3_cmp_io_sync_en_out_c2b ,stg2_cmp_io_sync_en_in_c2b , |
| 3299 | stg2_l2t2_clk_stop_in_c2b ); |
| 3300 | |
| 3301 | |
| 3302 | |
| 3303 | input gclk_spc7 ; |
| 3304 | input stg2_cmp_io_sync_en_in_c2b ; |
| 3305 | input stg2_db0_clk_stop_in_c2b ; |
| 3306 | input stg2_dmu_peu_por_in_c2b ; |
| 3307 | input stg2_dmu_peu_wmr_in_c2b ; |
| 3308 | input stg2_io_cmp_sync_en_in_c2b ; |
| 3309 | input stg2_l2_por_in_c2b ; |
| 3310 | input stg2_l2_wmr_in_c2b ; |
| 3311 | input stg2_l2b2_clk_stop_in_c2b ; |
| 3312 | input stg2_l2b3_clk_stop_in_c2b ; |
| 3313 | input stg2_l2d2_clk_stop_in_c2b ; |
| 3314 | input stg2_l2d3_clk_stop_in_c2b ; |
| 3315 | input stg2_l2t2_clk_stop_in_c2b ; |
| 3316 | input stg2_l2t3_clk_stop_in_c2bz ; |
| 3317 | input stg2_io_out_in_c2b ; |
| 3318 | input stg2_spc2_clk_stop_in_c2b ; |
| 3319 | input stg2_spc3_clk_stop_in_c2b ; |
| 3320 | input stg2_spc7_clk_stop_in_c2b ; |
| 3321 | output stg3_cmp_io_sync_en_out_c2b ; |
| 3322 | output stg3_db0_clk_stop_out_c2b ; |
| 3323 | output stg3_dmu_peu_por_out_c2b ; |
| 3324 | output stg3_dmu_peu_wmr_out_c2b ; |
| 3325 | output stg3_io_cmp_sync_en_out_c2b ; |
| 3326 | output stg3_l2_por_out_c2b ; |
| 3327 | output stg3_l2_wmr_out_c2b ; |
| 3328 | output stg3_l2b2_clk_stop_out_c2b ; |
| 3329 | output stg3_l2b3_clk_stop_out_c2b ; |
| 3330 | output stg3_l2d2_clk_stop_out_c2b ; |
| 3331 | output stg3_l2d3_clk_stop_out_c2b ; |
| 3332 | output stg3_l2t2_clk_stop_out_c2b ; |
| 3333 | output stg3_l2t3_clk_stop_out_c2b ; |
| 3334 | output stg3_io_out_out_c2b ; |
| 3335 | output stg3_spc2_clk_stop_out_c2b ; |
| 3336 | output stg3_spc3_clk_stop_out_c2b ; |
| 3337 | output stg3_spc7_clk_stop_out_c2b ; |
| 3338 | |
| 3339 | |
| 3340 | |
| 3341 | n2_clk_gl_cc_stage_17s1 xc2b_s1_0 ( |
| 3342 | .stg0_in ({stg2_l2t3_clk_stop_in_c2bz , |
| 3343 | stg2_l2t2_clk_stop_in_c2b ,stg2_l2b3_clk_stop_in_c2b , |
| 3344 | stg2_l2b2_clk_stop_in_c2b ,stg2_l2d3_clk_stop_in_c2b , |
| 3345 | stg2_l2d2_clk_stop_in_c2b ,stg2_db0_clk_stop_in_c2b , |
| 3346 | stg2_spc7_clk_stop_in_c2b ,stg2_spc3_clk_stop_in_c2b , |
| 3347 | stg2_spc2_clk_stop_in_c2b ,stg2_dmu_peu_wmr_in_c2b , |
| 3348 | stg2_dmu_peu_por_in_c2b ,stg2_l2_por_in_c2b , |
| 3349 | stg2_l2_wmr_in_c2b ,stg2_io_out_in_c2b , |
| 3350 | stg2_io_cmp_sync_en_in_c2b ,stg2_cmp_io_sync_en_in_c2b } ), |
| 3351 | .stg1_out ({stg3_l2t3_clk_stop_out_c2b , |
| 3352 | stg3_l2t2_clk_stop_out_c2b ,stg3_l2b3_clk_stop_out_c2b , |
| 3353 | stg3_l2b2_clk_stop_out_c2b ,stg3_l2d3_clk_stop_out_c2b , |
| 3354 | stg3_l2d2_clk_stop_out_c2b ,stg3_db0_clk_stop_out_c2b , |
| 3355 | stg3_spc7_clk_stop_out_c2b ,stg3_spc3_clk_stop_out_c2b , |
| 3356 | stg3_spc2_clk_stop_out_c2b ,stg3_dmu_peu_wmr_out_c2b , |
| 3357 | stg3_dmu_peu_por_out_c2b ,stg3_l2_por_out_c2b , |
| 3358 | stg3_l2_wmr_out_c2b ,stg3_io_out_out_c2b , |
| 3359 | stg3_io_cmp_sync_en_out_c2b ,stg3_cmp_io_sync_en_out_c2b } ) |
| 3360 | , |
| 3361 | .gclk (gclk_spc7 ) ); |
| 3362 | endmodule |
| 3363 | |
| 3364 | // ************************************************************************ |
| 3365 | // 17 module n2_clk_gl_cc_stage_8s2 (8x2) |
| 3366 | // ************************************************************************ |
| 3367 | |
| 3368 | module n2_clk_gl_cc_stage_8s2 (stg5_out ,stg3_in ,gclk ); |
| 3369 | |
| 3370 | output [7:0] stg5_out ; |
| 3371 | input [7:0] stg3_in ; |
| 3372 | input gclk ; |
| 3373 | |
| 3374 | wire [7:0] stg5_out ; |
| 3375 | wire [7:0] stg3_in ; |
| 3376 | wire gclk ; |
| 3377 | |
| 3378 | reg [7:0] q1; |
| 3379 | reg [7:0] q2; |
| 3380 | |
| 3381 | always @(posedge gclk) begin |
| 3382 | q1 <= stg3_in; |
| 3383 | q2 <= q1; |
| 3384 | end |
| 3385 | |
| 3386 | //ifdef FLOP_STAGES_ON |
| 3387 | assign stg5_out = q2; |
| 3388 | //else |
| 3389 | // assign stg5_out = stg3_in; |
| 3390 | //endif |
| 3391 | |
| 3392 | endmodule |
| 3393 | |
| 3394 | |
| 3395 | |
| 3396 | // ************************************************************************ |
| 3397 | // 18 module n2_clk_gl_cc_stg_c2b_s2_0 (8x2) |
| 3398 | // ************************************************************************ |
| 3399 | |
| 3400 | module n2_clk_gl_cc_stg_c2b_s2_0 (gclk_l2t3 , |
| 3401 | gl_l2_wmr_c2b ,stg3_ccx_clk_stop_in_c2b ,stg3_l2t3_clk_stop_in_c2b |
| 3402 | ,stg3_l2_por_in_c2b ,stg3_l2_wmr_in_c2b , |
| 3403 | stg3_io_cmp_sync_en_in_c2b ,stg3_cmp_io_sync_en_in_c2b , |
| 3404 | stg3_l2t7_clk_stop_in_c2b ,gl_ccx_clk_stop , |
| 3405 | gl_l2t3_clk_stop ,gl_l2t7_clk_stop ,gl_l2_por_c2b , |
| 3406 | gl_cmp_io_sync_en_c2b ,gl_io_cmp_sync_en_c2b ); |
| 3407 | |
| 3408 | /* |
| 3409 | n2_clk_gl_cc_stg_c2b_s2_0 (gclk_l2t3 ,spare_c2b_s2_out6 , |
| 3410 | gl_l2_wmr_c2b ,stg3_ccx_clk_stop_in_c2b ,stg3_l2t3_clk_stop_in_c2b |
| 3411 | ,stg3_l2_por_in_c2b ,stg3_l2_wmr_in_c2b , |
| 3412 | stg3_io_cmp_sync_en_in_c2b ,stg3_cmp_io_sync_en_in_c2b , |
| 3413 | stg3_l2t7_clk_stop_in_c2b ,gl_ccx_clk_stop , |
| 3414 | gl_l2t3_clk_stop ,gl_l2t7_clk_stop ,gl_l2_por_c2b , |
| 3415 | spare_c2b_s2_in6 ,gl_cmp_io_sync_en_c2b ,gl_io_cmp_sync_en_c2b ); |
| 3416 | */ |
| 3417 | |
| 3418 | input gclk_l2t3 ; |
| 3419 | // input spare_c2b_s2_in6 ; |
| 3420 | input stg3_ccx_clk_stop_in_c2b ; |
| 3421 | input stg3_cmp_io_sync_en_in_c2b ; |
| 3422 | input stg3_io_cmp_sync_en_in_c2b ; |
| 3423 | input stg3_l2_por_in_c2b ; |
| 3424 | input stg3_l2_wmr_in_c2b ; |
| 3425 | input stg3_l2t3_clk_stop_in_c2b ; |
| 3426 | input stg3_l2t7_clk_stop_in_c2b ; |
| 3427 | output gl_ccx_clk_stop ; |
| 3428 | output gl_cmp_io_sync_en_c2b ; |
| 3429 | output gl_io_cmp_sync_en_c2b ; |
| 3430 | output gl_l2_por_c2b ; |
| 3431 | output gl_l2_wmr_c2b ; |
| 3432 | output gl_l2t3_clk_stop ; |
| 3433 | output gl_l2t7_clk_stop ; |
| 3434 | // output spare_c2b_s2_out6 ; |
| 3435 | |
| 3436 | wire unused; |
| 3437 | |
| 3438 | n2_clk_gl_cc_stage_8s2 xc2t_s2_0 ( |
| 3439 | .stg5_out ({unused,gl_ccx_clk_stop , |
| 3440 | gl_l2t7_clk_stop ,gl_l2t3_clk_stop ,gl_l2_por_c2b , |
| 3441 | gl_l2_wmr_c2b ,gl_io_cmp_sync_en_c2b ,gl_cmp_io_sync_en_c2b |
| 3442 | } ), |
| 3443 | .stg3_in ({1'b0,stg3_ccx_clk_stop_in_c2b , |
| 3444 | stg3_l2t7_clk_stop_in_c2b ,stg3_l2t3_clk_stop_in_c2b , |
| 3445 | stg3_l2_por_in_c2b ,stg3_l2_wmr_in_c2b , |
| 3446 | stg3_io_cmp_sync_en_in_c2b ,stg3_cmp_io_sync_en_in_c2b } ), |
| 3447 | .gclk (gclk_l2t3 ) ); |
| 3448 | endmodule |
| 3449 | |
| 3450 | |
| 3451 | // ************************************************************************ |
| 3452 | // 19 module n2_clk_gl_cc_stg_c2b_s2_1 (2x2) |
| 3453 | // ************************************************************************ |
| 3454 | |
| 3455 | |
| 3456 | module n2_clk_gl_cc_stg_c2b_s2_1 (gclk_spc3 ,gl_spc3_clk_stop , |
| 3457 | gl_spc7_clk_stop ,stg3_spc7_clk_stop_in_c2b , |
| 3458 | stg3_spc3_clk_stop_in_c2b ); |
| 3459 | |
| 3460 | input gclk_spc3 ; |
| 3461 | input stg3_spc7_clk_stop_in_c2b ; |
| 3462 | input stg3_spc3_clk_stop_in_c2b ; |
| 3463 | output gl_spc3_clk_stop ; |
| 3464 | output gl_spc7_clk_stop ; |
| 3465 | |
| 3466 | wire [5:0] unused; |
| 3467 | |
| 3468 | |
| 3469 | n2_clk_gl_cc_stage_8s2 xc2t_s2_0 ( |
| 3470 | .stg5_out ({unused, |
| 3471 | gl_spc7_clk_stop ,gl_spc3_clk_stop } ), |
| 3472 | .stg3_in ({6'b0, |
| 3473 | stg3_spc7_clk_stop_in_c2b ,stg3_spc3_clk_stop_in_c2b } ), |
| 3474 | .gclk (gclk_spc3 ) ); |
| 3475 | endmodule |
| 3476 | |
| 3477 | |
| 3478 | |
| 3479 | // ************************************************************************ |
| 3480 | // 20 module n2_clk_gl_cc_stg_c2t_s1_0 (17x1) |
| 3481 | // ************************************************************************ |
| 3482 | |
| 3483 | module n2_clk_gl_cc_stg_c2t_s1_0 (gclk_spc5 ,stg3_l2t5_clk_stop_out_c2t , |
| 3484 | stg3_l2t1_clk_stop_out_c2t ,stg3_l2t0_clk_stop_out_c2t , |
| 3485 | stg3_l2b1_clk_stop_out_c2t ,stg3_l2b0_clk_stop_out_c2t , |
| 3486 | stg3_l2d1_clk_stop_out_c2t ,stg3_l2d0_clk_stop_out_c2t , |
| 3487 | stg3_spc5_clk_stop_out_c2t ,stg3_spc1_clk_stop_out_c2t , |
| 3488 | stg3_spc0_clk_stop_out_c2t ,stg3_l2_por_out_c2t , |
| 3489 | stg3_io_out_out_c2t ,stg3_dr_sync_en_out_c2t , |
| 3490 | stg3_mio_io2x_sync_en_out_c2t ,stg3_io_cmp_sync_en_out_c2t , |
| 3491 | stg3_cmp_io_sync_en_out_c2t ,stg2_cmp_io_sync_en_in_c2t , |
| 3492 | stg2_io_cmp_sync_en_in_c2t ,stg2_mio_io2x_sync_en_in_c2t , |
| 3493 | stg2_dr_sync_en_in_c2t ,stg2_io_out_in_c2t ,stg3_l2_wmr_out_c2t , |
| 3494 | stg2_l2_wmr_in_c2t ,stg2_l2_por_in_c2t ,stg2_spc0_clk_stop_in_c2t , |
| 3495 | stg2_spc1_clk_stop_in_c2t ,stg2_spc5_clk_stop_in_c2t , |
| 3496 | stg2_l2d0_clk_stop_in_c2t ,stg2_l2d1_clk_stop_in_c2t , |
| 3497 | stg2_l2b0_clk_stop_in_c2t ,stg2_l2b1_clk_stop_in_c2t , |
| 3498 | stg2_l2t0_clk_stop_in_c2t ,stg2_l2t5_clk_stop_in_c2t , |
| 3499 | stg2_l2t1_clk_stop_in_c2t ); |
| 3500 | |
| 3501 | |
| 3502 | |
| 3503 | |
| 3504 | input gclk_spc5 ; |
| 3505 | input stg2_cmp_io_sync_en_in_c2t ; |
| 3506 | input stg2_dr_sync_en_in_c2t ; |
| 3507 | input stg2_io_cmp_sync_en_in_c2t ; |
| 3508 | input stg2_io_out_in_c2t ; |
| 3509 | input stg2_l2_por_in_c2t ; |
| 3510 | input stg2_l2_wmr_in_c2t ; |
| 3511 | input stg2_l2b0_clk_stop_in_c2t ; |
| 3512 | input stg2_l2b1_clk_stop_in_c2t ; |
| 3513 | input stg2_l2d0_clk_stop_in_c2t ; |
| 3514 | input stg2_l2d1_clk_stop_in_c2t ; |
| 3515 | input stg2_l2t0_clk_stop_in_c2t ; |
| 3516 | input stg2_l2t1_clk_stop_in_c2t ; |
| 3517 | input stg2_l2t5_clk_stop_in_c2t ; |
| 3518 | input stg2_mio_io2x_sync_en_in_c2t ; |
| 3519 | input stg2_spc0_clk_stop_in_c2t ; |
| 3520 | input stg2_spc1_clk_stop_in_c2t ; |
| 3521 | input stg2_spc5_clk_stop_in_c2t ; |
| 3522 | output stg3_cmp_io_sync_en_out_c2t ; |
| 3523 | output stg3_dr_sync_en_out_c2t ; |
| 3524 | output stg3_io_cmp_sync_en_out_c2t ; |
| 3525 | output stg3_io_out_out_c2t ; |
| 3526 | output stg3_l2_por_out_c2t ; |
| 3527 | output stg3_l2_wmr_out_c2t ; |
| 3528 | output stg3_l2b0_clk_stop_out_c2t ; |
| 3529 | output stg3_l2b1_clk_stop_out_c2t ; |
| 3530 | output stg3_l2d0_clk_stop_out_c2t ; |
| 3531 | output stg3_l2d1_clk_stop_out_c2t ; |
| 3532 | output stg3_l2t0_clk_stop_out_c2t ; |
| 3533 | output stg3_l2t1_clk_stop_out_c2t ; |
| 3534 | output stg3_l2t5_clk_stop_out_c2t ; |
| 3535 | output stg3_mio_io2x_sync_en_out_c2t ; |
| 3536 | output stg3_spc0_clk_stop_out_c2t ; |
| 3537 | output stg3_spc1_clk_stop_out_c2t ; |
| 3538 | output stg3_spc5_clk_stop_out_c2t ; |
| 3539 | |
| 3540 | |
| 3541 | n2_clk_gl_cc_stage_17s1 xc2t_s1_0 ( |
| 3542 | .stg0_in ({stg2_l2t5_clk_stop_in_c2t , |
| 3543 | stg2_l2t1_clk_stop_in_c2t ,stg2_l2t0_clk_stop_in_c2t , |
| 3544 | stg2_l2b1_clk_stop_in_c2t ,stg2_l2b0_clk_stop_in_c2t , |
| 3545 | stg2_l2d1_clk_stop_in_c2t ,stg2_l2d0_clk_stop_in_c2t , |
| 3546 | stg2_spc5_clk_stop_in_c2t ,stg2_spc1_clk_stop_in_c2t , |
| 3547 | stg2_spc0_clk_stop_in_c2t ,stg2_l2_por_in_c2t , |
| 3548 | stg2_l2_wmr_in_c2t ,stg2_io_out_in_c2t , |
| 3549 | stg2_dr_sync_en_in_c2t ,stg2_mio_io2x_sync_en_in_c2t , |
| 3550 | stg2_io_cmp_sync_en_in_c2t ,stg2_cmp_io_sync_en_in_c2t } ), |
| 3551 | .stg1_out ({stg3_l2t5_clk_stop_out_c2t , |
| 3552 | stg3_l2t1_clk_stop_out_c2t ,stg3_l2t0_clk_stop_out_c2t , |
| 3553 | stg3_l2b1_clk_stop_out_c2t ,stg3_l2b0_clk_stop_out_c2t , |
| 3554 | stg3_l2d1_clk_stop_out_c2t ,stg3_l2d0_clk_stop_out_c2t , |
| 3555 | stg3_spc5_clk_stop_out_c2t ,stg3_spc1_clk_stop_out_c2t , |
| 3556 | stg3_spc0_clk_stop_out_c2t ,stg3_l2_por_out_c2t , |
| 3557 | stg3_l2_wmr_out_c2t ,stg3_io_out_out_c2t , |
| 3558 | stg3_dr_sync_en_out_c2t ,stg3_mio_io2x_sync_en_out_c2t , |
| 3559 | stg3_io_cmp_sync_en_out_c2t ,stg3_cmp_io_sync_en_out_c2t } ) |
| 3560 | , |
| 3561 | .gclk (gclk_spc5 ) ); |
| 3562 | endmodule |
| 3563 | |
| 3564 | |
| 3565 | // ************************************************************************ |
| 3566 | // 21 module n2_clk_gl_cc_stg_c2t_s2_0 (6x2) |
| 3567 | // ************************************************************************ |
| 3568 | |
| 3569 | module n2_clk_gl_cc_stg_c2t_s2_0 (stg3_l2t5_clk_stop_in_c2t , |
| 3570 | gl_l2_por_c2t ,stg3_io_cmp_sync_en_in_c2t ,stg3_l2_wmr_in_c2t , |
| 3571 | stg3_l2_por_in_c2t ,stg3_l2t1_clk_stop_in_c2t , |
| 3572 | stg3_cmp_io_sync_en_in_c2t ,gclk_l2t1 ,gl_l2_wmr_c2t , |
| 3573 | gl_cmp_io_sync_en_c2t ,gl_l2t5_clk_stop ,gl_io_cmp_sync_en_c2t |
| 3574 | ,gl_l2t1_clk_stop ); |
| 3575 | |
| 3576 | input gclk_l2t1 ; |
| 3577 | input stg3_cmp_io_sync_en_in_c2t ; |
| 3578 | input stg3_io_cmp_sync_en_in_c2t ; |
| 3579 | input stg3_l2_por_in_c2t ; |
| 3580 | input stg3_l2_wmr_in_c2t ; |
| 3581 | input stg3_l2t1_clk_stop_in_c2t ; |
| 3582 | input stg3_l2t5_clk_stop_in_c2t ; |
| 3583 | output gl_cmp_io_sync_en_c2t ; |
| 3584 | output gl_io_cmp_sync_en_c2t ; |
| 3585 | output gl_l2_por_c2t ; |
| 3586 | output gl_l2_wmr_c2t ; |
| 3587 | output gl_l2t1_clk_stop ; |
| 3588 | output gl_l2t5_clk_stop ; |
| 3589 | |
| 3590 | wire [1:0] unused; |
| 3591 | |
| 3592 | n2_clk_gl_cc_stage_8s2 xc2t_s2_0 ( |
| 3593 | .stg5_out ({unused, gl_l2t5_clk_stop , |
| 3594 | gl_l2t1_clk_stop ,gl_l2_por_c2t ,gl_l2_wmr_c2t , |
| 3595 | gl_io_cmp_sync_en_c2t ,gl_cmp_io_sync_en_c2t } ), |
| 3596 | .stg3_in ({2'b0, stg3_l2t5_clk_stop_in_c2t , |
| 3597 | stg3_l2t1_clk_stop_in_c2t ,stg3_l2_por_in_c2t , |
| 3598 | stg3_l2_wmr_in_c2t ,stg3_io_cmp_sync_en_in_c2t , |
| 3599 | stg3_cmp_io_sync_en_in_c2t } ), |
| 3600 | .gclk (gclk_l2t1 ) ); |
| 3601 | endmodule |
| 3602 | |
| 3603 | |
| 3604 | // ************************************************************************ |
| 3605 | // 22 module n2_clk_gl_cc_stg_c2t_s2_1 (4x2) |
| 3606 | // ************************************************************************ |
| 3607 | |
| 3608 | module n2_clk_gl_cc_stg_c2t_s2_1 (gclk_spc1 ,stg3_spc1_clk_stop_in_c2t , |
| 3609 | stg3_mio_clk_stop_in_c2t ,gl_mio_clk_stop_c2t , |
| 3610 | gl_spc5_clk_stop ,gl_io2x_sync_en_c2t , |
| 3611 | gl_spc1_clk_stop ,stg3_io2x_sync_en_in_c2t , |
| 3612 | stg3_spc5_clk_stop_in_c2t ); |
| 3613 | |
| 3614 | input gclk_spc1 ; |
| 3615 | input stg3_io2x_sync_en_in_c2t ; |
| 3616 | input stg3_mio_clk_stop_in_c2t ; |
| 3617 | input stg3_spc1_clk_stop_in_c2t ; |
| 3618 | input stg3_spc5_clk_stop_in_c2t ; |
| 3619 | output gl_io2x_sync_en_c2t; |
| 3620 | output gl_mio_clk_stop_c2t ; |
| 3621 | output gl_spc1_clk_stop ; |
| 3622 | output gl_spc5_clk_stop ; |
| 3623 | |
| 3624 | wire [3:0] unused; |
| 3625 | |
| 3626 | n2_clk_gl_cc_stage_8s2 xc2t_s2_0 ( |
| 3627 | .stg5_out ({unused, |
| 3628 | gl_mio_clk_stop_c2t, gl_spc5_clk_stop , |
| 3629 | gl_spc1_clk_stop, gl_io2x_sync_en_c2t } ), |
| 3630 | .stg3_in ({4'b0, |
| 3631 | stg3_mio_clk_stop_in_c2t ,stg3_spc5_clk_stop_in_c2t , |
| 3632 | stg3_spc1_clk_stop_in_c2t ,stg3_io2x_sync_en_in_c2t } ), |
| 3633 | .gclk (gclk_spc1 ) ); |
| 3634 | endmodule |
| 3635 | |
| 3636 | |
| 3637 | // ************************************************************************ |
| 3638 | // 23 module n2_clk_gl_cc_stg_c3t_s1_0 (13x1) |
| 3639 | // ************************************************************************ |
| 3640 | |
| 3641 | module n2_clk_gl_cc_stg_c3t_s1_0 (stg3_cmp_io_sync_en_in_c3t , |
| 3642 | stg4_mio_io2x_sync_en_out_c3t ,stg4_io_out_out_c3t , |
| 3643 | stg4_l2_wmr_out_c3t ,stg4_l2_por_out_c3t , |
| 3644 | stg4_spc0_clk_stop_out_c3t ,stg4_l2d0_clk_stop_out_c3t , |
| 3645 | stg4_l2d1_clk_stop_out_c3t ,stg4_l2b0_clk_stop_out_c3t , |
| 3646 | stg4_l2b1_clk_stop_out_c3t ,stg4_l2t0_clk_stop_out_c3t , |
| 3647 | stg3_mio_io2x_sync_en_in_c3t ,stg3_dr_sync_en_in_c3t , |
| 3648 | stg3_io_out_in_c3t ,stg3_l2_wmr_in_c3t ,stg3_l2_por_in_c3t , |
| 3649 | stg3_spc0_clk_stop_in_c3t ,stg3_l2d0_clk_stop_in_c3t , |
| 3650 | stg3_l2d1_clk_stop_in_c3t ,stg3_l2b0_clk_stop_in_c3t , |
| 3651 | stg3_l2b1_clk_stop_in_c3t ,stg3_l2t0_clk_stop_in_c3t , |
| 3652 | stg4_cmp_io_sync_en_out_c3t ,stg4_dr_sync_en_out_c3t ,gclk_spc0 , |
| 3653 | stg3_io_cmp_sync_en_in_c3t ,stg4_io_cmp_sync_en_out_c3t ); |
| 3654 | |
| 3655 | |
| 3656 | input gclk_spc0 ; |
| 3657 | input stg3_cmp_io_sync_en_in_c3t ; |
| 3658 | input stg3_dr_sync_en_in_c3t ; |
| 3659 | input stg3_io_cmp_sync_en_in_c3t ; |
| 3660 | input stg3_io_out_in_c3t ; |
| 3661 | input stg3_l2_por_in_c3t ; |
| 3662 | input stg3_l2_wmr_in_c3t ; |
| 3663 | input stg3_l2b0_clk_stop_in_c3t ; |
| 3664 | input stg3_l2b1_clk_stop_in_c3t ; |
| 3665 | input stg3_l2d0_clk_stop_in_c3t ; |
| 3666 | input stg3_l2d1_clk_stop_in_c3t ; |
| 3667 | input stg3_l2t0_clk_stop_in_c3t ; |
| 3668 | input stg3_mio_io2x_sync_en_in_c3t ; |
| 3669 | input stg3_spc0_clk_stop_in_c3t ; |
| 3670 | output stg4_cmp_io_sync_en_out_c3t ; |
| 3671 | output stg4_dr_sync_en_out_c3t ; |
| 3672 | output stg4_io_cmp_sync_en_out_c3t ; |
| 3673 | output stg4_io_out_out_c3t ; |
| 3674 | output stg4_l2_por_out_c3t ; |
| 3675 | output stg4_l2_wmr_out_c3t ; |
| 3676 | output stg4_l2b0_clk_stop_out_c3t ; |
| 3677 | output stg4_l2b1_clk_stop_out_c3t ; |
| 3678 | output stg4_l2d0_clk_stop_out_c3t ; |
| 3679 | output stg4_l2d1_clk_stop_out_c3t ; |
| 3680 | output stg4_l2t0_clk_stop_out_c3t ; |
| 3681 | output stg4_mio_io2x_sync_en_out_c3t ; |
| 3682 | output stg4_spc0_clk_stop_out_c3t ; |
| 3683 | |
| 3684 | wire [3:0] unused; |
| 3685 | |
| 3686 | n2_clk_gl_cc_stage_17s1 xc3t_s1_0 ( |
| 3687 | .stg0_in ({4'b0, |
| 3688 | stg3_l2t0_clk_stop_in_c3t ,stg3_l2b1_clk_stop_in_c3t , |
| 3689 | stg3_l2b0_clk_stop_in_c3t ,stg3_l2d1_clk_stop_in_c3t , |
| 3690 | stg3_l2d0_clk_stop_in_c3t ,stg3_spc0_clk_stop_in_c3t , |
| 3691 | stg3_l2_por_in_c3t ,stg3_l2_wmr_in_c3t ,stg3_io_out_in_c3t , |
| 3692 | stg3_dr_sync_en_in_c3t ,stg3_mio_io2x_sync_en_in_c3t , |
| 3693 | stg3_io_cmp_sync_en_in_c3t ,stg3_cmp_io_sync_en_in_c3t } ), |
| 3694 | .stg1_out ({unused, |
| 3695 | stg4_l2t0_clk_stop_out_c3t ,stg4_l2b1_clk_stop_out_c3t , |
| 3696 | stg4_l2b0_clk_stop_out_c3t ,stg4_l2d1_clk_stop_out_c3t , |
| 3697 | stg4_l2d0_clk_stop_out_c3t ,stg4_spc0_clk_stop_out_c3t , |
| 3698 | stg4_l2_por_out_c3t ,stg4_l2_wmr_out_c3t , |
| 3699 | stg4_io_out_out_c3t ,stg4_dr_sync_en_out_c3t , |
| 3700 | stg4_mio_io2x_sync_en_out_c3t ,stg4_io_cmp_sync_en_out_c3t , |
| 3701 | stg4_cmp_io_sync_en_out_c3t } ), |
| 3702 | .gclk (gclk_spc0 ) ); |
| 3703 | endmodule |
| 3704 | |
| 3705 | |
| 3706 | // ************************************************************************ |
| 3707 | // 24 module n2_clk_gl_cc_stg_c3t_s1_1 (7x1) |
| 3708 | // ************************************************************************ |
| 3709 | |
| 3710 | |
| 3711 | module n2_clk_gl_cc_stg_c3t_s1_1 (gclk_l2t0 ,stg3_mcu1_clk_stop_in_c3t , |
| 3712 | stg3_mcu0_io_clk_stop_in_c3t ,stg3_mcu1_io_clk_stop_in_c3t , |
| 3713 | // stg3_mcu0_dr_clk_stop_in_c3t ,stg3_mcu1_dr_clk_stop_in_c3t , |
| 3714 | stg3_mio_clk_stop_in_c3t ,stg4_mcu0_clk_stop_out_c3t , |
| 3715 | stg4_mcu1_clk_stop_out_c3t ,stg4_mcu0_io_clk_stop_out_c3t , |
| 3716 | stg4_mcu1_io_clk_stop_out_c3t , // stg4_mcu0_dr_clk_stop_out_c3t , |
| 3717 | // stg4_mcu1_dr_clk_stop_out_c3t , |
| 3718 | stg4_mio_clk_stop_out_c3t , |
| 3719 | stg3_mcu0_clk_stop_in_c3t ); |
| 3720 | |
| 3721 | input gclk_l2t0 ; |
| 3722 | input stg3_mcu0_clk_stop_in_c3t ; |
| 3723 | // input stg3_mcu0_dr_clk_stop_in_c3t ; |
| 3724 | input stg3_mcu0_io_clk_stop_in_c3t ; |
| 3725 | input stg3_mcu1_clk_stop_in_c3t ; |
| 3726 | // input stg3_mcu1_dr_clk_stop_in_c3t ; |
| 3727 | input stg3_mcu1_io_clk_stop_in_c3t ; |
| 3728 | input stg3_mio_clk_stop_in_c3t ; |
| 3729 | output stg4_mcu0_clk_stop_out_c3t ; |
| 3730 | // output stg4_mcu0_dr_clk_stop_out_c3t ; |
| 3731 | output stg4_mcu0_io_clk_stop_out_c3t ; |
| 3732 | output stg4_mcu1_clk_stop_out_c3t ; |
| 3733 | // output stg4_mcu1_dr_clk_stop_out_c3t ; |
| 3734 | output stg4_mcu1_io_clk_stop_out_c3t ; |
| 3735 | output stg4_mio_clk_stop_out_c3t ; |
| 3736 | |
| 3737 | wire [11:0] unused; |
| 3738 | |
| 3739 | n2_clk_gl_cc_stage_17s1 xc2t_s1_0 ( |
| 3740 | .stg0_in ({12'b0 ,stg3_mio_clk_stop_in_c3t , |
| 3741 | // stg3_mcu1_dr_clk_stop_in_c3t ,stg3_mcu0_dr_clk_stop_in_c3t , |
| 3742 | stg3_mcu1_io_clk_stop_in_c3t ,stg3_mcu0_io_clk_stop_in_c3t , |
| 3743 | stg3_mcu1_clk_stop_in_c3t ,stg3_mcu0_clk_stop_in_c3t } ), |
| 3744 | .stg1_out ({unused ,stg4_mio_clk_stop_out_c3t , |
| 3745 | // stg4_mcu1_dr_clk_stop_out_c3t ,stg4_mcu0_dr_clk_stop_out_c3t, |
| 3746 | stg4_mcu1_io_clk_stop_out_c3t , stg4_mcu0_io_clk_stop_out_c3t , |
| 3747 | stg4_mcu1_clk_stop_out_c3t , stg4_mcu0_clk_stop_out_c3t } ), |
| 3748 | .gclk (gclk_l2t0 ) ); |
| 3749 | endmodule |
| 3750 | |
| 3751 | |
| 3752 | // ************************************************************************ |
| 3753 | // 25 module n2_clk_gl_cc_stg_c3t_s1_3 (14x1) |
| 3754 | // ************************************************************************ |
| 3755 | |
| 3756 | |
| 3757 | module n2_clk_gl_cc_stg_c3t_s1_3 (gclk_ncu ,stg4_cmp_io_sync_en_in_c3t , |
| 3758 | gl_io2x_sync_en_c3t ,gl_io_out_c3t ,gl_l2_wmr_c3t ,gl_l2_por_c3t , |
| 3759 | gl_l2t0_clk_stop ,gl_mcu0_clk_stop ,gl_mcu1_clk_stop , |
| 3760 | // gl_mcu0_dr_clk_stop ,gl_mcu1_dr_clk_stop , |
| 3761 | gl_mcu0_io_clk_stop ,gl_mcu1_io_clk_stop , |
| 3762 | stg4_dr_sync_en_in_c3t ,stg4_io_out_in_c3t ,stg4_l2_wmr_in_c3t , |
| 3763 | stg4_l2_por_in_c3t ,stg4_l2t0_clk_stop_in_c3t , |
| 3764 | stg4_mcu0_clk_stop_in_c3t ,stg4_mcu1_clk_stop_in_c3t , |
| 3765 | // stg4_mcu0_dr_clk_stop_in_c3t ,stg4_mcu1_dr_clk_stop_in_c3t , |
| 3766 | stg4_mcu0_io_clk_stop_in_c3t ,stg4_mcu1_io_clk_stop_in_c3t , |
| 3767 | gl_cmp_io_sync_en_c3t ,gl_dr_sync_en_c3t , |
| 3768 | stg4_io_cmp_sync_en_in_c3t ,stg4_io2x_sync_en_in_c3t , |
| 3769 | gl_io_cmp_sync_en_c3t ); |
| 3770 | |
| 3771 | input gclk_ncu ; |
| 3772 | input stg4_cmp_io_sync_en_in_c3t ; |
| 3773 | input stg4_dr_sync_en_in_c3t ; |
| 3774 | input stg4_io2x_sync_en_in_c3t ; |
| 3775 | input stg4_io_cmp_sync_en_in_c3t ; |
| 3776 | input stg4_io_out_in_c3t ; |
| 3777 | input stg4_l2_por_in_c3t ; |
| 3778 | input stg4_l2_wmr_in_c3t ; |
| 3779 | input stg4_l2t0_clk_stop_in_c3t ; |
| 3780 | // input stg4_mcu1_dr_clk_stop_in_c3t ; |
| 3781 | input stg4_mcu0_clk_stop_in_c3t ; |
| 3782 | // input stg4_mcu0_dr_clk_stop_in_c3t ; |
| 3783 | input stg4_mcu0_io_clk_stop_in_c3t ; |
| 3784 | input stg4_mcu1_clk_stop_in_c3t ; |
| 3785 | input stg4_mcu1_io_clk_stop_in_c3t ; |
| 3786 | |
| 3787 | output gl_cmp_io_sync_en_c3t ; |
| 3788 | output gl_dr_sync_en_c3t ; |
| 3789 | output gl_io2x_sync_en_c3t ; |
| 3790 | output gl_io_cmp_sync_en_c3t ; |
| 3791 | output gl_io_out_c3t ; |
| 3792 | output gl_l2_por_c3t ; |
| 3793 | output gl_l2_wmr_c3t ; |
| 3794 | output gl_l2t0_clk_stop ; |
| 3795 | // output gl_mcu1_dr_clk_stop ; |
| 3796 | output gl_mcu0_clk_stop ; |
| 3797 | // output gl_mcu0_dr_clk_stop ; |
| 3798 | output gl_mcu0_io_clk_stop ; |
| 3799 | output gl_mcu1_clk_stop ; |
| 3800 | output gl_mcu1_io_clk_stop ; |
| 3801 | |
| 3802 | wire [4:0] unused; |
| 3803 | |
| 3804 | n2_clk_gl_cc_stage_17s1 xc2t_s1_0 ( |
| 3805 | .stg0_in ({5'b0, |
| 3806 | stg4_mcu1_io_clk_stop_in_c3t ,stg4_mcu0_io_clk_stop_in_c3t , |
| 3807 | // stg4_mcu1_dr_clk_stop_in_c3t ,stg4_mcu0_dr_clk_stop_in_c3t , |
| 3808 | stg4_mcu1_clk_stop_in_c3t ,stg4_mcu0_clk_stop_in_c3t , |
| 3809 | stg4_l2t0_clk_stop_in_c3t ,stg4_l2_por_in_c3t , |
| 3810 | stg4_l2_wmr_in_c3t ,stg4_io_out_in_c3t , |
| 3811 | stg4_dr_sync_en_in_c3t ,stg4_io2x_sync_en_in_c3t , |
| 3812 | stg4_io_cmp_sync_en_in_c3t ,stg4_cmp_io_sync_en_in_c3t } ), |
| 3813 | .stg1_out ({unused, |
| 3814 | gl_mcu1_io_clk_stop , gl_mcu0_io_clk_stop , |
| 3815 | // gl_mcu1_dr_clk_stop , gl_mcu0_dr_clk_stop , |
| 3816 | gl_mcu1_clk_stop , gl_mcu0_clk_stop , |
| 3817 | gl_l2t0_clk_stop ,gl_l2_por_c3t , |
| 3818 | gl_l2_wmr_c3t ,gl_io_out_c3t, |
| 3819 | gl_dr_sync_en_c3t , gl_io2x_sync_en_c3t , |
| 3820 | gl_io_cmp_sync_en_c3t , gl_cmp_io_sync_en_c3t } ), |
| 3821 | .gclk (gclk_ncu ) ); |
| 3822 | |
| 3823 | endmodule |
| 3824 | |
| 3825 | |
| 3826 | // ************************************************************************ |
| 3827 | // 26 module n2_clk_gl_cc_stg_c3t_s1_2 (11x1) |
| 3828 | // ************************************************************************ |
| 3829 | |
| 3830 | module n2_clk_gl_cc_stg_c3t_s1_2(gclk_l2b0 ,gl_l2_por_c3t , |
| 3831 | gl_l2d1_clk_stop ,gl_l2b0_clk_stop ,gl_l2b1_clk_stop , |
| 3832 | gl_mio_clk_stop_c3t ,stg4_spc0_clk_stop_in_c3t , |
| 3833 | stg4_cmp_io_sync_en_in_c3t ,stg4_io_cmp_sync_en_in_c3t , |
| 3834 | stg4_l2_wmr_in_c3t ,stg4_l2_por_in_c3t ,stg4_l2d0_clk_stop_in_c3t , |
| 3835 | stg4_l2d1_clk_stop_in_c3t ,stg4_l2b0_clk_stop_in_c3t , |
| 3836 | stg4_l2b1_clk_stop_in_c3t ,stg4_mio_clk_stop_in_c3t , |
| 3837 | gl_io2x_sync_en_c3t ,gl_spc0_clk_stop ,gl_cmp_io_sync_en_c3t , |
| 3838 | gl_io_cmp_sync_en_c3t ,gl_l2d0_clk_stop , |
| 3839 | stg4_io2x_sync_en_in_c3t ,gl_l2_wmr_c3t ); |
| 3840 | output gl_l2_por_c3t ; |
| 3841 | output gl_l2d1_clk_stop ; |
| 3842 | output gl_l2b0_clk_stop ; |
| 3843 | output gl_l2b1_clk_stop ; |
| 3844 | output gl_mio_clk_stop_c3t ; |
| 3845 | output gl_io2x_sync_en_c3t ; |
| 3846 | output gl_spc0_clk_stop ; |
| 3847 | output gl_cmp_io_sync_en_c3t ; |
| 3848 | output gl_io_cmp_sync_en_c3t ; |
| 3849 | output gl_l2d0_clk_stop ; |
| 3850 | output gl_l2_wmr_c3t ; |
| 3851 | input gclk_l2b0 ; |
| 3852 | input stg4_spc0_clk_stop_in_c3t ; |
| 3853 | input stg4_cmp_io_sync_en_in_c3t ; |
| 3854 | input stg4_io_cmp_sync_en_in_c3t ; |
| 3855 | input stg4_l2_wmr_in_c3t ; |
| 3856 | input stg4_l2_por_in_c3t ; |
| 3857 | input stg4_l2d0_clk_stop_in_c3t ; |
| 3858 | input stg4_l2d1_clk_stop_in_c3t ; |
| 3859 | input stg4_l2b0_clk_stop_in_c3t ; |
| 3860 | input stg4_l2b1_clk_stop_in_c3t ; |
| 3861 | input stg4_mio_clk_stop_in_c3t ; |
| 3862 | input stg4_io2x_sync_en_in_c3t ; |
| 3863 | |
| 3864 | wire [5:0] unused; |
| 3865 | |
| 3866 | n2_clk_gl_cc_stage_17s1 xc2t_s1_0 ( |
| 3867 | .stg0_in ({6'b0, |
| 3868 | stg4_mio_clk_stop_in_c3t ,stg4_l2b1_clk_stop_in_c3t , |
| 3869 | stg4_l2b0_clk_stop_in_c3t ,stg4_l2d1_clk_stop_in_c3t , |
| 3870 | stg4_l2d0_clk_stop_in_c3t ,stg4_l2_por_in_c3t , |
| 3871 | stg4_l2_wmr_in_c3t ,stg4_io_cmp_sync_en_in_c3t , |
| 3872 | stg4_cmp_io_sync_en_in_c3t ,stg4_spc0_clk_stop_in_c3t , |
| 3873 | stg4_io2x_sync_en_in_c3t } ), |
| 3874 | .stg1_out ({unused, |
| 3875 | gl_mio_clk_stop_c3t ,gl_l2b1_clk_stop, |
| 3876 | gl_l2b0_clk_stop ,gl_l2d1_clk_stop , |
| 3877 | gl_l2d0_clk_stop ,gl_l2_por_c3t ,gl_l2_wmr_c3t , |
| 3878 | gl_io_cmp_sync_en_c3t ,gl_cmp_io_sync_en_c3t , |
| 3879 | gl_spc0_clk_stop ,gl_io2x_sync_en_c3t } ), |
| 3880 | .gclk (gclk_l2b0 ) ); |
| 3881 | endmodule |
| 3882 | |
| 3883 | |
| 3884 | // ************************************************************************ |
| 3885 | // 27 module n2_clk_gl_cc_stg_c3b_s1_0 (14x1) |
| 3886 | // ************************************************************************ |
| 3887 | |
| 3888 | |
| 3889 | module n2_clk_gl_cc_stg_c3b_s1_0 (stg4_io_out_out_c3b , |
| 3890 | stg4_l2_wmr_out_c3b ,stg4_l2_por_out_c3b ,stg4_dmu_peu_por_out_c3b |
| 3891 | ,stg4_dmu_peu_wmr_out_c3b ,stg4_spc2_clk_stop_out_c3b , |
| 3892 | stg4_db0_clk_stop_out_c3b ,stg4_l2d2_clk_stop_out_c3b , |
| 3893 | stg4_l2d3_clk_stop_out_c3b ,stg4_l2b2_clk_stop_out_c3b , |
| 3894 | stg4_l2b3_clk_stop_out_c3b ,stg4_l2t2_clk_stop_out_c3b , |
| 3895 | stg3_cmp_io_sync_en_in_c3b ,stg3_io_cmp_sync_en_in_c3b , |
| 3896 | stg3_io_out_in_c3b ,stg3_l2_wmr_in_c3b ,stg3_l2_por_in_c3b , |
| 3897 | stg3_dmu_peu_por_in_c3b ,stg3_dmu_peu_wmr_in_c3b , |
| 3898 | stg3_spc2_clk_stop_in_c3b ,stg3_db0_clk_stop_in_c3b , |
| 3899 | stg3_l2d2_clk_stop_in_c3b ,stg3_l2d3_clk_stop_in_c3b , |
| 3900 | stg3_l2b2_clk_stop_in_c3b ,stg3_l2b3_clk_stop_in_c3b , |
| 3901 | stg3_l2t2_clk_stop_in_c3b ,stg4_io_cmp_sync_en_out_c3b ,gclk_spc2 , |
| 3902 | stg4_cmp_io_sync_en_out_c3b ); |
| 3903 | |
| 3904 | input gclk_spc2 ; |
| 3905 | input stg3_cmp_io_sync_en_in_c3b ; |
| 3906 | input stg3_db0_clk_stop_in_c3b ; |
| 3907 | input stg3_dmu_peu_por_in_c3b ; |
| 3908 | input stg3_dmu_peu_wmr_in_c3b ; |
| 3909 | input stg3_io_cmp_sync_en_in_c3b ; |
| 3910 | input stg3_io_out_in_c3b ; |
| 3911 | input stg3_l2_por_in_c3b ; |
| 3912 | input stg3_l2_wmr_in_c3b ; |
| 3913 | input stg3_l2b2_clk_stop_in_c3b ; |
| 3914 | input stg3_l2b3_clk_stop_in_c3b ; |
| 3915 | input stg3_l2d2_clk_stop_in_c3b ; |
| 3916 | input stg3_l2d3_clk_stop_in_c3b ; |
| 3917 | input stg3_spc2_clk_stop_in_c3b ; |
| 3918 | input stg3_l2t2_clk_stop_in_c3b ; |
| 3919 | output stg4_cmp_io_sync_en_out_c3b ; |
| 3920 | output stg4_db0_clk_stop_out_c3b ; |
| 3921 | output stg4_dmu_peu_por_out_c3b ; |
| 3922 | output stg4_dmu_peu_wmr_out_c3b ; |
| 3923 | output stg4_io_cmp_sync_en_out_c3b ; |
| 3924 | output stg4_io_out_out_c3b ; |
| 3925 | output stg4_l2_por_out_c3b ; |
| 3926 | output stg4_l2_wmr_out_c3b ; |
| 3927 | output stg4_l2b2_clk_stop_out_c3b ; |
| 3928 | output stg4_l2b3_clk_stop_out_c3b ; |
| 3929 | output stg4_l2d2_clk_stop_out_c3b ; |
| 3930 | output stg4_l2d3_clk_stop_out_c3b ; |
| 3931 | output stg4_spc2_clk_stop_out_c3b ; |
| 3932 | output stg4_l2t2_clk_stop_out_c3b ; |
| 3933 | |
| 3934 | wire [2:0] unused; |
| 3935 | |
| 3936 | |
| 3937 | |
| 3938 | |
| 3939 | n2_clk_gl_cc_stage_17s1 xc3b_s1_0 ( |
| 3940 | .stg0_in ({3'b0, |
| 3941 | stg3_cmp_io_sync_en_in_c3b, stg3_db0_clk_stop_in_c3b, |
| 3942 | stg3_dmu_peu_por_in_c3b, stg3_dmu_peu_wmr_in_c3b, |
| 3943 | stg3_io_cmp_sync_en_in_c3b, stg3_io_out_in_c3b, |
| 3944 | stg3_l2_por_in_c3b, stg3_l2_wmr_in_c3b, |
| 3945 | stg3_l2b2_clk_stop_in_c3b, stg3_l2b3_clk_stop_in_c3b, |
| 3946 | stg3_l2d2_clk_stop_in_c3b, stg3_l2d3_clk_stop_in_c3b, |
| 3947 | stg3_spc2_clk_stop_in_c3b, stg3_l2t2_clk_stop_in_c3b} ), |
| 3948 | .stg1_out ({unused, |
| 3949 | stg4_cmp_io_sync_en_out_c3b, stg4_db0_clk_stop_out_c3b, |
| 3950 | stg4_dmu_peu_por_out_c3b, stg4_dmu_peu_wmr_out_c3b, |
| 3951 | stg4_io_cmp_sync_en_out_c3b, stg4_io_out_out_c3b, |
| 3952 | stg4_l2_por_out_c3b, stg4_l2_wmr_out_c3b, |
| 3953 | stg4_l2b2_clk_stop_out_c3b, stg4_l2b3_clk_stop_out_c3b, |
| 3954 | stg4_l2d2_clk_stop_out_c3b, stg4_l2d3_clk_stop_out_c3b, |
| 3955 | stg4_spc2_clk_stop_out_c3b, stg4_l2t2_clk_stop_out_c3b} ), |
| 3956 | .gclk (gclk_spc2 ) ); |
| 3957 | endmodule |
| 3958 | |
| 3959 | |
| 3960 | // ************************************************************************ |
| 3961 | // 28 module n2_clk_gl_cc_stg_c3b_s1_1 (6x1) |
| 3962 | // ************************************************************************ |
| 3963 | |
| 3964 | |
| 3965 | module n2_clk_gl_cc_stg_c3b_s1_1 (gclk_l2t2 ,stg3_ncu_clk_stop_in_c3b , |
| 3966 | stg3_sii_io_clk_stop_in_c3b ,stg3_ncu_io_clk_stop_in_c3b , |
| 3967 | stg3_dmu_io_clk_stop_in_c3b ,stg3_peu_io_clk_stop_in_c3b , |
| 3968 | stg4_sii_clk_stop_out_c3b ,stg4_ncu_clk_stop_out_c3b , |
| 3969 | stg4_sii_io_clk_stop_out_c3b ,stg4_ncu_io_clk_stop_out_c3b , |
| 3970 | stg4_dmu_io_clk_stop_out_c3b ,stg4_peu_io_clk_stop_out_c3b , |
| 3971 | stg3_sii_clk_stop_in_c3b ); |
| 3972 | |
| 3973 | input gclk_l2t2 ; |
| 3974 | input stg3_dmu_io_clk_stop_in_c3b ; |
| 3975 | input stg3_ncu_clk_stop_in_c3b ; |
| 3976 | input stg3_ncu_io_clk_stop_in_c3b ; |
| 3977 | input stg3_peu_io_clk_stop_in_c3b ; |
| 3978 | input stg3_sii_clk_stop_in_c3b ; |
| 3979 | input stg3_sii_io_clk_stop_in_c3b ; |
| 3980 | output stg4_dmu_io_clk_stop_out_c3b ; |
| 3981 | output stg4_ncu_clk_stop_out_c3b ; |
| 3982 | output stg4_ncu_io_clk_stop_out_c3b ; |
| 3983 | output stg4_peu_io_clk_stop_out_c3b ; |
| 3984 | output stg4_sii_clk_stop_out_c3b ; |
| 3985 | output stg4_sii_io_clk_stop_out_c3b ; |
| 3986 | |
| 3987 | wire [10:0] unused; |
| 3988 | |
| 3989 | n2_clk_gl_cc_stage_17s1 xc3b_s1_1 ( |
| 3990 | .stg0_in ({11'b0, |
| 3991 | stg3_dmu_io_clk_stop_in_c3b, stg3_ncu_clk_stop_in_c3b, |
| 3992 | stg3_ncu_io_clk_stop_in_c3b, stg3_peu_io_clk_stop_in_c3b, |
| 3993 | stg3_sii_clk_stop_in_c3b, stg3_sii_io_clk_stop_in_c3b }), |
| 3994 | .stg1_out ({unused, |
| 3995 | stg4_dmu_io_clk_stop_out_c3b, stg4_ncu_clk_stop_out_c3b, |
| 3996 | stg4_ncu_io_clk_stop_out_c3b, stg4_peu_io_clk_stop_out_c3b, |
| 3997 | stg4_sii_clk_stop_out_c3b, stg4_sii_io_clk_stop_out_c3b }), |
| 3998 | .gclk (gclk_l2t2 ) ); |
| 3999 | endmodule |
| 4000 | |
| 4001 | |
| 4002 | // ************************************************************************ |
| 4003 | // 29 module n2_clk_gl_cc_stg_c3b_s1_3 (7x1) |
| 4004 | // ************************************************************************ |
| 4005 | |
| 4006 | |
| 4007 | module n2_clk_gl_cc_stg_c3b_s1_3 (gclk_dmu ,stg4_dmu_peu_por_in_c3b , |
| 4008 | stg4_dmu_peu_wmr_in_c3b ,stg4_spc2_clk_stop_in_c3b , |
| 4009 | stg4_db0_clk_stop_c3b ,stg4_dmu_io_clk_stop_in_c3b , |
| 4010 | stg4_peu_io_clk_stop_in_c3b ,gl_io_out_c3b ,gl_dmu_peu_por_c3b , |
| 4011 | gl_dmu_peu_wmr_c3b ,gl_spc2_clk_stop ,gl_db0_clk_stop , |
| 4012 | gl_dmu_io_clk_stop ,gl_peu_io_clk_stop ,stg4_io_out_in_c3b |
| 4013 | ); |
| 4014 | |
| 4015 | input gclk_dmu ; |
| 4016 | input stg4_db0_clk_stop_c3b ; |
| 4017 | input stg4_dmu_io_clk_stop_in_c3b ; |
| 4018 | input stg4_dmu_peu_por_in_c3b ; |
| 4019 | input stg4_dmu_peu_wmr_in_c3b ; |
| 4020 | input stg4_io_out_in_c3b ; |
| 4021 | input stg4_peu_io_clk_stop_in_c3b ; |
| 4022 | input stg4_spc2_clk_stop_in_c3b ; |
| 4023 | output gl_db0_clk_stop ; |
| 4024 | output gl_dmu_io_clk_stop ; |
| 4025 | output gl_dmu_peu_por_c3b ; |
| 4026 | output gl_dmu_peu_wmr_c3b ; |
| 4027 | output gl_io_out_c3b ; |
| 4028 | output gl_peu_io_clk_stop ; |
| 4029 | output gl_spc2_clk_stop ; |
| 4030 | |
| 4031 | wire [9:0] unused; |
| 4032 | |
| 4033 | n2_clk_gl_cc_stage_17s1 xc2t_s1_0 ( |
| 4034 | .stg0_in ({10'b0,stg4_peu_io_clk_stop_in_c3b , |
| 4035 | stg4_dmu_io_clk_stop_in_c3b ,stg4_db0_clk_stop_c3b , |
| 4036 | stg4_spc2_clk_stop_in_c3b ,stg4_dmu_peu_wmr_in_c3b , |
| 4037 | stg4_dmu_peu_por_in_c3b ,stg4_io_out_in_c3b } ), |
| 4038 | .stg1_out ({unused,gl_peu_io_clk_stop , |
| 4039 | gl_dmu_io_clk_stop ,gl_db0_clk_stop , |
| 4040 | gl_spc2_clk_stop ,gl_dmu_peu_wmr_c3b , |
| 4041 | gl_dmu_peu_por_c3b,gl_io_out_c3b } ), |
| 4042 | .gclk (gclk_dmu ) ); |
| 4043 | endmodule |
| 4044 | |
| 4045 | |
| 4046 | |
| 4047 | // ************************************************************************ |
| 4048 | // 30 module n2_clk_gl_cc_stg_c3b_s1_2 (14x1) |
| 4049 | // ************************************************************************ |
| 4050 | |
| 4051 | module n2_clk_gl_cc_stg_c3b_s1_2 (stg4_sii_io_clk_stop_in_c3b , |
| 4052 | gl_io_out_c3b ,gl_l2_wmr_c3b ,gl_l2_por_c3b ,gl_l2d2_clk_stop , |
| 4053 | gl_l2d3_clk_stop ,gl_l2b2_clk_stop ,gl_l2b3_clk_stop , |
| 4054 | gl_l2t2_clk_stop ,gl_sii_clk_stop ,gl_ncu_clk_stop , |
| 4055 | gl_sii_io_clk_stop ,gl_ncu_io_clk_stop ,gclk_l2d2 , |
| 4056 | stg4_ncu_clk_stop_in_c3b ,stg4_sii_clk_stop_in_c3b , |
| 4057 | stg4_l2t2_clk_stop_in_c3b ,stg4_l2b3_clk_stop_in_c3b , |
| 4058 | stg4_l2b2_clk_stop_in_c3b ,stg4_cmp_io_sync_en_in_c3b , |
| 4059 | stg4_l2d3_clk_stop_in_c3b ,stg4_l2d2_clk_stop_in_c3b , |
| 4060 | stg4_l2_por_in_c3b ,stg4_l2_wmr_in_c3b ,stg4_io_out_in_c3b , |
| 4061 | stg4_io_cmp_sync_en_in_c3b ,gl_io_cmp_sync_en_c3b , |
| 4062 | gl_cmp_io_sync_en_c3b ,stg4_ncu_io_clk_stop_c3b ); |
| 4063 | |
| 4064 | |
| 4065 | input gclk_l2d2 ; |
| 4066 | input stg4_cmp_io_sync_en_in_c3b ; |
| 4067 | input stg4_io_cmp_sync_en_in_c3b ; |
| 4068 | input stg4_io_out_in_c3b ; |
| 4069 | input stg4_l2_por_in_c3b ; |
| 4070 | input stg4_l2_wmr_in_c3b ; |
| 4071 | input stg4_l2b2_clk_stop_in_c3b ; |
| 4072 | input stg4_l2b3_clk_stop_in_c3b ; |
| 4073 | input stg4_l2d2_clk_stop_in_c3b ; |
| 4074 | input stg4_l2d3_clk_stop_in_c3b ; |
| 4075 | input stg4_l2t2_clk_stop_in_c3b ; |
| 4076 | input stg4_ncu_clk_stop_in_c3b ; |
| 4077 | input stg4_ncu_io_clk_stop_c3b ; |
| 4078 | input stg4_sii_clk_stop_in_c3b ; |
| 4079 | input stg4_sii_io_clk_stop_in_c3b ; |
| 4080 | output gl_cmp_io_sync_en_c3b ; |
| 4081 | output gl_io_cmp_sync_en_c3b ; |
| 4082 | output gl_io_out_c3b ; |
| 4083 | output gl_l2_por_c3b ; |
| 4084 | output gl_l2_wmr_c3b ; |
| 4085 | output gl_l2b2_clk_stop ; |
| 4086 | output gl_l2b3_clk_stop ; |
| 4087 | output gl_l2d2_clk_stop ; |
| 4088 | output gl_l2d3_clk_stop ; |
| 4089 | output gl_l2t2_clk_stop ; |
| 4090 | output gl_ncu_clk_stop ; |
| 4091 | output gl_ncu_io_clk_stop ; |
| 4092 | output gl_sii_clk_stop ; |
| 4093 | output gl_sii_io_clk_stop ; |
| 4094 | |
| 4095 | wire [2:0] unused; |
| 4096 | n2_clk_gl_cc_stage_17s1 xc3b_s1_2 ( |
| 4097 | .stg0_in ({3'b0, |
| 4098 | stg4_cmp_io_sync_en_in_c3b, stg4_io_cmp_sync_en_in_c3b, |
| 4099 | stg4_io_out_in_c3b, stg4_l2_por_in_c3b, |
| 4100 | stg4_l2_wmr_in_c3b, stg4_l2b2_clk_stop_in_c3b, |
| 4101 | stg4_l2b3_clk_stop_in_c3b, stg4_l2d2_clk_stop_in_c3b, |
| 4102 | stg4_l2d3_clk_stop_in_c3b, stg4_l2t2_clk_stop_in_c3b, |
| 4103 | stg4_ncu_clk_stop_in_c3b, stg4_ncu_io_clk_stop_c3b, |
| 4104 | stg4_sii_clk_stop_in_c3b, stg4_sii_io_clk_stop_in_c3b} ), |
| 4105 | .stg1_out ({unused, |
| 4106 | gl_cmp_io_sync_en_c3b, gl_io_cmp_sync_en_c3b, |
| 4107 | gl_io_out_c3b, gl_l2_por_c3b, |
| 4108 | gl_l2_wmr_c3b, gl_l2b2_clk_stop, |
| 4109 | gl_l2b3_clk_stop, gl_l2d2_clk_stop, |
| 4110 | gl_l2d3_clk_stop, gl_l2t2_clk_stop, |
| 4111 | gl_ncu_clk_stop, gl_ncu_io_clk_stop, |
| 4112 | gl_sii_clk_stop, gl_sii_io_clk_stop} ), |
| 4113 | .gclk (gclk_l2d2 ) ); |
| 4114 | endmodule |
| 4115 | |
| 4116 | |
| 4117 | |
| 4118 | // ************************************************************************ |
| 4119 | // 31 module n2_clk_gl_cc_stg_c1b_s1_0 (17x1) |
| 4120 | // ************************************************************************ |
| 4121 | |
| 4122 | module n2_clk_gl_cc_stg_c1b_s1_0 (gclk_l2t6 ,stg1_l2b2_clk_stop_in_c1b , |
| 4123 | stg2_l2t2_clk_stop_out_c1b ,stg1_spc7_clk_stop_in_c1b , |
| 4124 | stg2_db0_clk_stop_out_c1b ,stg2_l2_por_out_c1b , |
| 4125 | stg2_dmu_peu_wmr_out_c1b ,stg2_dmu_peu_por_out_c1b , |
| 4126 | stg2_l2d3_clk_stop_out_c1b ,stg2_io_cmp_sync_en_out_c1b , |
| 4127 | stg2_spc2_clk_stop_out_c1b , |
| 4128 | stg2_l2t3_clk_stop_out_c1b ,stg2_cmp_io_sync_en_out_c1b , |
| 4129 | stg2_l2_wmr_out_c1b ,stg2_spc3_clk_stop_out_c1b , |
| 4130 | stg2_l2b2_clk_stop_out_c1b ,stg2_spc7_clk_stop_out_c1b , |
| 4131 | stg1_l2d3_clk_stop_in_c1b ,stg1_l2t3_clk_stop_in_c1b , |
| 4132 | stg1_l2t2_clk_stop_in_c1b ,stg1_dmu_peu_wmr_in_c1b , |
| 4133 | stg1_io_out_in_c1b, stg2_io_out_out_c1b, |
| 4134 | stg1_dmu_peu_por_in_c1b , stg1_l2b3_clk_stop_in_c1b |
| 4135 | ,stg1_db0_clk_stop_in_c1b ,stg1_l2_por_in_c1b ,stg1_l2_wmr_in_c1b |
| 4136 | ,stg1_cmp_io_sync_en_in_c1b ,stg2_l2d2_clk_stop_out_c1b , |
| 4137 | stg1_l2d2_clk_stop_in_c1b ,stg1_io_cmp_sync_en_in_c1b , |
| 4138 | stg1_spc2_clk_stop_in_c1b ,stg2_l2b3_clk_stop_out_c1b , |
| 4139 | stg1_spc3_clk_stop_in_c1b ); |
| 4140 | |
| 4141 | |
| 4142 | |
| 4143 | input gclk_l2t6 ; |
| 4144 | input stg1_cmp_io_sync_en_in_c1b ; |
| 4145 | input stg1_db0_clk_stop_in_c1b ; |
| 4146 | input stg1_dmu_peu_por_in_c1b ; |
| 4147 | input stg1_dmu_peu_wmr_in_c1b ; |
| 4148 | input stg1_io_cmp_sync_en_in_c1b ; |
| 4149 | input stg1_l2_por_in_c1b ; |
| 4150 | input stg1_l2_wmr_in_c1b ; |
| 4151 | input stg1_l2b2_clk_stop_in_c1b ; |
| 4152 | input stg1_l2b3_clk_stop_in_c1b ; |
| 4153 | input stg1_l2d2_clk_stop_in_c1b ; |
| 4154 | input stg1_l2d3_clk_stop_in_c1b ; |
| 4155 | input stg1_l2t2_clk_stop_in_c1b ; |
| 4156 | input stg1_l2t3_clk_stop_in_c1b ; |
| 4157 | input stg1_spc2_clk_stop_in_c1b ; |
| 4158 | input stg1_spc3_clk_stop_in_c1b ; |
| 4159 | input stg1_spc7_clk_stop_in_c1b ; |
| 4160 | input stg1_io_out_in_c1b; |
| 4161 | output stg2_cmp_io_sync_en_out_c1b ; |
| 4162 | output stg2_db0_clk_stop_out_c1b ; |
| 4163 | output stg2_dmu_peu_por_out_c1b ; |
| 4164 | output stg2_dmu_peu_wmr_out_c1b ; |
| 4165 | output stg2_io_cmp_sync_en_out_c1b ; |
| 4166 | output stg2_l2_por_out_c1b ; |
| 4167 | output stg2_l2_wmr_out_c1b ; |
| 4168 | output stg2_l2b2_clk_stop_out_c1b ; |
| 4169 | output stg2_l2b3_clk_stop_out_c1b ; |
| 4170 | output stg2_l2d2_clk_stop_out_c1b ; |
| 4171 | output stg2_l2d3_clk_stop_out_c1b ; |
| 4172 | output stg2_l2t2_clk_stop_out_c1b ; |
| 4173 | output stg2_l2t3_clk_stop_out_c1b ; |
| 4174 | output stg2_spc2_clk_stop_out_c1b ; |
| 4175 | output stg2_spc3_clk_stop_out_c1b ; |
| 4176 | output stg2_spc7_clk_stop_out_c1b ; |
| 4177 | output stg2_io_out_out_c1b; |
| 4178 | |
| 4179 | |
| 4180 | n2_clk_gl_cc_stage_17s1 xc1b_s1_0 ( |
| 4181 | .stg0_in ({stg1_l2t3_clk_stop_in_c1b , |
| 4182 | stg1_l2t2_clk_stop_in_c1b ,stg1_l2b3_clk_stop_in_c1b , |
| 4183 | stg1_l2b2_clk_stop_in_c1b ,stg1_l2d3_clk_stop_in_c1b , |
| 4184 | stg1_l2d2_clk_stop_in_c1b ,stg1_db0_clk_stop_in_c1b , |
| 4185 | stg1_spc7_clk_stop_in_c1b ,stg1_spc3_clk_stop_in_c1b , |
| 4186 | stg1_spc2_clk_stop_in_c1b ,stg1_dmu_peu_wmr_in_c1b , |
| 4187 | stg1_dmu_peu_por_in_c1b ,stg1_l2_por_in_c1b , |
| 4188 | stg1_l2_wmr_in_c1b ,stg1_io_out_in_c1b , |
| 4189 | stg1_io_cmp_sync_en_in_c1b ,stg1_cmp_io_sync_en_in_c1b } ), |
| 4190 | .stg1_out ({stg2_l2t3_clk_stop_out_c1b , |
| 4191 | stg2_l2t2_clk_stop_out_c1b ,stg2_l2b3_clk_stop_out_c1b , |
| 4192 | stg2_l2b2_clk_stop_out_c1b ,stg2_l2d3_clk_stop_out_c1b , |
| 4193 | stg2_l2d2_clk_stop_out_c1b ,stg2_db0_clk_stop_out_c1b , |
| 4194 | stg2_spc7_clk_stop_out_c1b ,stg2_spc3_clk_stop_out_c1b , |
| 4195 | stg2_spc2_clk_stop_out_c1b ,stg2_dmu_peu_wmr_out_c1b , |
| 4196 | stg2_dmu_peu_por_out_c1b ,stg2_l2_por_out_c1b , |
| 4197 | stg2_l2_wmr_out_c1b ,stg2_io_out_out_c1b , |
| 4198 | stg2_io_cmp_sync_en_out_c1b ,stg2_cmp_io_sync_en_out_c1b } ) |
| 4199 | , |
| 4200 | .gclk (gclk_l2t6 ) ); |
| 4201 | endmodule |
| 4202 | |
| 4203 | |
| 4204 | // ************************************************************************ |
| 4205 | // 32 module n2_clk_gl_cc_stg_c1b_s1_1 (8x1) |
| 4206 | // ************************************************************************ |
| 4207 | |
| 4208 | module n2_clk_gl_cc_stg_c1b_s1_1 (gclk_spc6 ,stg2_ncu_io_clk_stop_out_c1b |
| 4209 | ,stg2_ccx_clk_stop_out_c1b ,stg1_ncu_clk_stop_in_c1b , |
| 4210 | stg1_sii_io_clk_stop_in_c1b ,stg1_ncu_io_clk_stop_in_c1b , |
| 4211 | stg1_sii_clk_stop_in_c1b ,stg1_ccx_clk_stop_in_c1b , |
| 4212 | stg1_dmu_io_clk_stop_in_c1b ,stg2_peu_io_clk_stop_out_c1b , |
| 4213 | stg2_sii_clk_stop_out_c1b ,stg2_ncu_clk_stop_out_c1b , |
| 4214 | stg2_l2t7_clk_stop_out_c1b ,stg2_dmu_io_clk_stop_out_c1b , |
| 4215 | stg1_peu_io_clk_stop_in_c1b ,stg1_l2t7_clk_stop_in_c1b , |
| 4216 | stg2_sii_io_clk_stop_out_c1b ); |
| 4217 | |
| 4218 | input gclk_spc6 ; |
| 4219 | input stg1_ccx_clk_stop_in_c1b ; |
| 4220 | input stg1_dmu_io_clk_stop_in_c1b ; |
| 4221 | input stg1_l2t7_clk_stop_in_c1b ; |
| 4222 | input stg1_ncu_clk_stop_in_c1b ; |
| 4223 | input stg1_ncu_io_clk_stop_in_c1b ; |
| 4224 | input stg1_peu_io_clk_stop_in_c1b ; |
| 4225 | input stg1_sii_clk_stop_in_c1b ; |
| 4226 | input stg1_sii_io_clk_stop_in_c1b ; |
| 4227 | output stg2_ccx_clk_stop_out_c1b ; |
| 4228 | output stg2_dmu_io_clk_stop_out_c1b ; |
| 4229 | output stg2_l2t7_clk_stop_out_c1b ; |
| 4230 | output stg2_ncu_clk_stop_out_c1b ; |
| 4231 | output stg2_ncu_io_clk_stop_out_c1b ; |
| 4232 | output stg2_peu_io_clk_stop_out_c1b ; |
| 4233 | output stg2_sii_clk_stop_out_c1b ; |
| 4234 | output stg2_sii_io_clk_stop_out_c1b ; |
| 4235 | |
| 4236 | wire [8:0] unused; |
| 4237 | |
| 4238 | |
| 4239 | n2_clk_gl_cc_stage_17s1 xc1b_s1_1 ( |
| 4240 | .stg0_in ({9'b0,stg1_peu_io_clk_stop_in_c1b , |
| 4241 | stg1_dmu_io_clk_stop_in_c1b ,stg1_ncu_io_clk_stop_in_c1b , |
| 4242 | stg1_sii_io_clk_stop_in_c1b ,stg1_ncu_clk_stop_in_c1b , |
| 4243 | stg1_sii_clk_stop_in_c1b ,stg1_ccx_clk_stop_in_c1b , |
| 4244 | stg1_l2t7_clk_stop_in_c1b } ), |
| 4245 | .stg1_out ({unused,stg2_peu_io_clk_stop_out_c1b , |
| 4246 | stg2_dmu_io_clk_stop_out_c1b ,stg2_ncu_io_clk_stop_out_c1b , |
| 4247 | stg2_sii_io_clk_stop_out_c1b ,stg2_ncu_clk_stop_out_c1b , |
| 4248 | stg2_sii_clk_stop_out_c1b ,stg2_ccx_clk_stop_out_c1b , |
| 4249 | stg2_l2t7_clk_stop_out_c1b } ), |
| 4250 | .gclk (gclk_spc6 ) ); |
| 4251 | endmodule |
| 4252 | |
| 4253 | |
| 4254 | |
| 4255 | |
| 4256 | // ************************************************************************ |
| 4257 | // 33 module n2_clk_gl_cc_stg_c2t_s1_1 (5x1) |
| 4258 | // ************************************************************************ |
| 4259 | |
| 4260 | module n2_clk_gl_cc_stg_c2t_s1_1 (stg2_io2x_sync_en_in_c2t , |
| 4261 | // stg3_spc1_clk_stop_in_c2b, stg3_spc5_clk_stop_in_c2b , |
| 4262 | stg3_io2x_sync_en_out_c2t , |
| 4263 | // stg4_spc1_clk_stop_out_c2b , stg4_spc5_clk_stop_out_c2b , |
| 4264 | gclk_l2t5 , |
| 4265 | stg2_mcu0_clk_stop_in_c2t, |
| 4266 | stg2_mcu1_clk_stop_in_c2t, |
| 4267 | stg3_mcu0_clk_stop_out_c2t, |
| 4268 | stg3_mcu1_clk_stop_out_c2t, |
| 4269 | stg2_mcu0_io_clk_stop_in_c2t, |
| 4270 | // stg2_mcu0_dr_clk_stop_in_c2t, // FOR INT6.1 |
| 4271 | // stg2_mcu1_dr_clk_stop_in_c2t, // FOR INT6.1 |
| 4272 | stg2_mcu1_io_clk_stop_in_c2t, |
| 4273 | // stg3_mcu0_dr_clk_stop_out_c2t, // FOR INT6.1 |
| 4274 | stg3_mcu0_io_clk_stop_out_c2t, |
| 4275 | // stg3_mcu1_dr_clk_stop_out_c2t, // FOR INT6.1 |
| 4276 | stg3_mcu1_io_clk_stop_out_c2t, |
| 4277 | stg2_mio_clk_stop_in_c2t , stg3_mio_clk_stop_out_c2t |
| 4278 | |
| 4279 | ); |
| 4280 | |
| 4281 | input gclk_l2t5 ; |
| 4282 | input stg2_io2x_sync_en_in_c2t ; |
| 4283 | // input stg3_spc1_clk_stop_in_c2b ; |
| 4284 | // input stg3_spc5_clk_stop_in_c2b ; |
| 4285 | input stg2_mio_clk_stop_in_c2t ; |
| 4286 | output stg3_mio_clk_stop_out_c2t ; |
| 4287 | output stg3_io2x_sync_en_out_c2t ; |
| 4288 | // output stg4_spc1_clk_stop_out_c2b ; |
| 4289 | // output stg4_spc5_clk_stop_out_c2b ; |
| 4290 | |
| 4291 | input stg2_mcu0_clk_stop_in_c2t; |
| 4292 | input stg2_mcu1_clk_stop_in_c2t; |
| 4293 | output stg3_mcu0_clk_stop_out_c2t; |
| 4294 | output stg3_mcu1_clk_stop_out_c2t; |
| 4295 | |
| 4296 | |
| 4297 | input stg2_mcu0_io_clk_stop_in_c2t; |
| 4298 | //input stg2_mcu0_dr_clk_stop_in_c2t; |
| 4299 | //input stg2_mcu1_dr_clk_stop_in_c2t; |
| 4300 | input stg2_mcu1_io_clk_stop_in_c2t; |
| 4301 | //output stg3_mcu0_dr_clk_stop_out_c2t; |
| 4302 | output stg3_mcu0_io_clk_stop_out_c2t; |
| 4303 | //output stg3_mcu1_dr_clk_stop_out_c2t; |
| 4304 | output stg3_mcu1_io_clk_stop_out_c2t; |
| 4305 | |
| 4306 | wire [10:0] unused; |
| 4307 | |
| 4308 | n2_clk_gl_cc_stage_17s1 xc2t_s1_1 ( |
| 4309 | .stg0_in ({11'b0, |
| 4310 | stg2_mio_clk_stop_in_c2t, |
| 4311 | stg2_mcu0_clk_stop_in_c2t, |
| 4312 | stg2_mcu0_io_clk_stop_in_c2t, |
| 4313 | // stg2_mcu0_dr_clk_stop_in_c2t, |
| 4314 | stg2_mcu1_clk_stop_in_c2t, |
| 4315 | stg2_mcu1_io_clk_stop_in_c2t, |
| 4316 | // stg2_mcu1_dr_clk_stop_in_c2t, |
| 4317 | // stg3_spc5_clk_stop_in_c2b , |
| 4318 | // stg3_spc1_clk_stop_in_c2b , |
| 4319 | stg2_io2x_sync_en_in_c2t } ), |
| 4320 | .stg1_out ({unused, |
| 4321 | stg3_mio_clk_stop_out_c2t, |
| 4322 | stg3_mcu0_clk_stop_out_c2t, |
| 4323 | stg3_mcu0_io_clk_stop_out_c2t, |
| 4324 | // stg3_mcu0_dr_clk_stop_out_c2t, |
| 4325 | stg3_mcu1_clk_stop_out_c2t, |
| 4326 | stg3_mcu1_io_clk_stop_out_c2t, |
| 4327 | // stg3_mcu1_dr_clk_stop_out_c2t, |
| 4328 | // stg4_spc5_clk_stop_out_c2b , |
| 4329 | // stg4_spc1_clk_stop_out_c2b , |
| 4330 | stg3_io2x_sync_en_out_c2t } ), |
| 4331 | .gclk (gclk_l2t5 ) ); |
| 4332 | endmodule |
| 4333 | |
| 4334 | // ************************************************************************ |
| 4335 | // 35 module n2_clk_gl_cc_stage_align |
| 4336 | // ************************************************************************ |
| 4337 | |
| 4338 | // n2_clk_gl_cc_stage_ccu_align ( |
| 4339 | module n2_clk_gl_cc_stage_align ( |
| 4340 | gclk_a , gclk_b ,gclk_aligned , gclk_c, ccu_vco_aligned |
| 4341 | ); |
| 4342 | output gclk_aligned ; |
| 4343 | input gclk_a ; |
| 4344 | input gclk_b ; |
| 4345 | input gclk_c ; |
| 4346 | input ccu_vco_aligned ; |
| 4347 | |
| 4348 | reg q2; |
| 4349 | reg q3; |
| 4350 | wire gclk_b; |
| 4351 | wire gclk_c; |
| 4352 | wire gclk_aligned; |
| 4353 | wire ccu_vco_aligned; |
| 4354 | |
| 4355 | // special aligned signal |
| 4356 | |
| 4357 | |
| 4358 | // delayed clocking scheme |
| 4359 | // following causes functional mismatch |
| 4360 | // uncomment this for equivalency |
| 4361 | // always @(posedge gclk_b) begin |
| 4362 | // q2 <= ccu_vco_aligned; |
| 4363 | // end |
| 4364 | // |
| 4365 | // always @(posedge gclk_c) begin |
| 4366 | // |
| 4367 | // q3 <= q2; |
| 4368 | // end |
| 4369 | // assign gclk_aligned = q3; |
| 4370 | |
| 4371 | assign gclk_aligned = ccu_vco_aligned; |
| 4372 | |
| 4373 | endmodule |
| 4374 | |
| 4375 | |
| 4376 | // ************************************************************************ |
| 4377 | // 36 n2_clk_gl_cc_stg_mcu_dr - FOR INT6.1 |
| 4378 | // ************************************************************************ |
| 4379 | module n2_clk_gl_cc_stg_mcu_dr(stg1_mcu1_dr_clk_stop_in , |
| 4380 | stg2_mcu0_dr_clk_stop_out ,stg2_mcu1_dr_clk_stop_out ,dr_gclk , |
| 4381 | stg1_mcu0_dr_clk_stop_in ); |
| 4382 | output stg2_mcu0_dr_clk_stop_out ; |
| 4383 | output stg2_mcu1_dr_clk_stop_out ; |
| 4384 | input stg1_mcu1_dr_clk_stop_in ; |
| 4385 | input dr_gclk ; |
| 4386 | input stg1_mcu0_dr_clk_stop_in ; |
| 4387 | |
| 4388 | wire [14:0] unused; |
| 4389 | |
| 4390 | n2_clk_gl_cc_stage_17s1 xmcu_dr_0 ( |
| 4391 | .gclk ( dr_gclk ), |
| 4392 | .stg0_in ({15'b0, stg1_mcu1_dr_clk_stop_in, stg1_mcu0_dr_clk_stop_in}), |
| 4393 | .stg1_out ({unused, stg2_mcu1_dr_clk_stop_out, stg2_mcu0_dr_clk_stop_out}) |
| 4394 | ); |
| 4395 | |
| 4396 | endmodule |
| 4397 | |
| 4398 | // ************************************************************************ |
| 4399 | // 34 module n2_clk_gl_cc_stage_top |
| 4400 | // ************************************************************************ |
| 4401 | |
| 4402 | module n2_clk_gl_cc_stage_top ( |
| 4403 | // for int6.1 (set 3) |
| 4404 | gclk_spc6s, |
| 4405 | stg1_cmp_io_sync_en_in_c1bg, |
| 4406 | stg1_cmp_io_sync_en_in_c1tg, |
| 4407 | stg1_io_cmp_sync_en_in_c1bg, |
| 4408 | stg1_io_cmp_sync_en_in_c1tg, |
| 4409 | stg1_io_out_in_c1bg, |
| 4410 | stg1_l2_por_in_c1bg, |
| 4411 | stg1_l2_por_in_c1tg, |
| 4412 | stg1_l2_wmr_in_c1bg, |
| 4413 | stg1_l2_wmr_in_c1tg, |
| 4414 | stg1_mio_clk_stop_in_c1tg, |
| 4415 | stg1_mio_io2x_sync_en_in_c1tg, |
| 4416 | stg4_cmp_io_sync_en_in_c3t0, |
| 4417 | stg4_io_cmp_sync_en_in_c3t0, |
| 4418 | stg4_io_out_in_c3b0, |
| 4419 | stg4_l2_por_in_c3t0, |
| 4420 | stg4_l2_wmr_in_c3t0, |
| 4421 | |
| 4422 | stg2_mcu0_clk_stop_in_c2t, |
| 4423 | stg2_mcu1_clk_stop_in_c2t, |
| 4424 | stg3_mcu0_clk_stop_out_c2t, |
| 4425 | stg3_mcu1_clk_stop_out_c2t, |
| 4426 | stg2_mcu0_io_clk_stop_in_c2t, |
| 4427 | // stg2_mcu0_dr_clk_stop_in_c2t, |
| 4428 | // stg2_mcu1_dr_clk_stop_in_c2t, |
| 4429 | stg2_mcu1_io_clk_stop_in_c2t, |
| 4430 | // stg3_mcu0_dr_clk_stop_out_c2t, |
| 4431 | stg3_mcu0_io_clk_stop_out_c2t, |
| 4432 | // stg3_mcu1_dr_clk_stop_out_c2t, |
| 4433 | stg3_mcu1_io_clk_stop_out_c2t, |
| 4434 | stg2_io_out_out_c1b , |
| 4435 | stg2_io2x_sync_en_in_c2t, |
| 4436 | stg3_io2x_sync_en_out_c2t, |
| 4437 | stg2_mio_clk_stop_in_c2t, stg3_mio_clk_stop_out_c2t, |
| 4438 | gclk_aligned, ccu_vco_aligned, gclk_a, gclk_b, gclk_c, |
| 4439 | stg1_l2d2_clk_stop_in_c1b , |
| 4440 | stg2_l2d2_clk_stop_out_c1b ,gl_io_out_c3b0 ,gl_l2_por_c3b0 , |
| 4441 | gl_io_cmp_sync_en_c2t ,gl_l2_por_c2t ,gl_cmp_io_sync_en_c2t , |
| 4442 | gl_cmp_io_sync_en_c3t0 ,gl_l2t5_clk_stop , |
| 4443 | stg3_l2t1_clk_stop_in_c2t ,stg3_l2_wmr_in_c2t ,gclk_spc3 ,gclk_l2t3, |
| 4444 | gclk_l2t7 ,gclk_spc7 ,stg3_l2t5_clk_stop_in_c2t , |
| 4445 | stg3_io_cmp_sync_en_in_c2t ,gl_io2x_sync_en_c3t0 , |
| 4446 | gl_io_cmp_sync_en_c3t0 ,gl_l2_por_c3t0 ,gl_spc0_clk_stop , |
| 4447 | gl_mio_clk_stop_c1t ,gl_l2d5_clk_stop,gl_l2t1_clk_stop, |
| 4448 | gclk_dmu ,gclk_l2d2 ,gclk_mac ,gclk_l2d6 ,gl_spc5_clk_stop, |
| 4449 | stg3_l2_por_in_c2t ,stg3_cmp_io_sync_en_in_c2t , |
| 4450 | gl_io2x_sync_en_c2t ,gl_spc1_clk_stop, |
| 4451 | stg4_cmp_io_sync_en_out_c3b ,stg4_l2t2_clk_stop_out_c3b , |
| 4452 | stg4_io_out_out_c3b ,stg4_l2_wmr_out_c3b ,stg4_l2_por_out_c3b , |
| 4453 | stg4_dmu_peu_por_out_c3b ,stg4_dmu_peu_wmr_out_c3b , |
| 4454 | stg4_spc2_clk_stop_out_c3b ,stg4_db0_clk_stop_out_c3b , |
| 4455 | stg4_l2d2_clk_stop_out_c3b ,stg4_l2d3_clk_stop_out_c3b , |
| 4456 | stg4_l2b2_clk_stop_out_c3b ,stg4_l2b3_clk_stop_out_c3b , |
| 4457 | stg4_io_cmp_sync_en_out_c3b ,stg3_l2b2_clk_stop_in_c3b , |
| 4458 | stg3_l2b3_clk_stop_in_c3b ,stg3_l2t2_clk_stop_in_c3b , |
| 4459 | stg3_io_cmp_sync_en_in_c3b ,stg3_io_out_in_c3b ,stg3_l2_wmr_in_c3b |
| 4460 | ,stg3_l2_por_in_c3b ,stg3_dmu_peu_por_in_c3b , |
| 4461 | stg3_dmu_peu_wmr_in_c3b ,stg3_spc2_clk_stop_in_c3b , |
| 4462 | stg3_cmp_io_sync_en_in_c3b ,stg3_db0_clk_stop_in_c3b , |
| 4463 | stg3_l2d2_clk_stop_in_c3b ,stg3_l2d3_clk_stop_in_c3b , |
| 4464 | stg4_sii_clk_stop_out_c3b ,stg4_ncu_clk_stop_out_c3b , |
| 4465 | stg4_sii_io_clk_stop_out_c3b ,stg4_ncu_io_clk_stop_out_c3b , |
| 4466 | stg4_dmu_io_clk_stop_out_c3b ,stg4_peu_io_clk_stop_out_c3b , |
| 4467 | stg3_sii_clk_stop_in_c3b ,stg3_ncu_clk_stop_in_c3b , |
| 4468 | stg3_sii_io_clk_stop_in_c3b ,stg3_ncu_io_clk_stop_in_c3b , |
| 4469 | stg3_dmu_io_clk_stop_in_c3b ,stg3_peu_io_clk_stop_in_c3b , |
| 4470 | gl_cmp_io_sync_en_c3b ,gl_io_cmp_sync_en_c3b ,gl_ncu_clk_stop , |
| 4471 | gl_sii_io_clk_stop ,gl_ncu_io_clk_stop ,gl_l2_wmr_c3b , |
| 4472 | gl_l2d2_clk_stop ,gl_l2d3_clk_stop ,gl_l2b2_clk_stop , |
| 4473 | gl_l2b3_clk_stop ,gl_l2t2_clk_stop ,gl_io_out_c3b , |
| 4474 | gl_sii_clk_stop ,stg4_l2_wmr_in_c3b ,stg4_io_out_in_c3b , |
| 4475 | stg4_io_cmp_sync_en_in_c3b ,stg4_ncu_io_clk_stop_c3b , |
| 4476 | stg4_sii_io_clk_stop_in_c3b ,stg4_ncu_clk_stop_in_c3b , |
| 4477 | stg4_sii_clk_stop_in_c3b ,stg4_l2t2_clk_stop_in_c3b , |
| 4478 | stg4_l2b3_clk_stop_in_c3b ,stg4_l2b2_clk_stop_in_c3b , |
| 4479 | stg4_cmp_io_sync_en_in_c3b ,stg4_l2d3_clk_stop_in_c3b , |
| 4480 | stg4_l2d2_clk_stop_in_c3b ,stg4_l2_por_in_c3b ,gl_db0_clk_stop |
| 4481 | ,gl_dmu_io_clk_stop ,gl_peu_io_clk_stop , |
| 4482 | gl_dmu_peu_por_c3b ,gl_dmu_peu_wmr_c3b ,gl_spc2_clk_stop , |
| 4483 | stg4_dmu_peu_por_in_c3b ,stg4_dmu_peu_wmr_in_c3b , |
| 4484 | stg4_spc2_clk_stop_in_c3b ,stg4_db0_clk_stop_c3b , |
| 4485 | stg4_dmu_io_clk_stop_in_c3b ,stg4_peu_io_clk_stop_in_c3b , |
| 4486 | stg4_cmp_io_sync_en_out_c3t ,stg4_io_cmp_sync_en_out_c3t , |
| 4487 | stg4_mio_io2x_sync_en_out_c3t ,stg4_dr_sync_en_out_c3t , |
| 4488 | stg4_io_out_out_c3t ,stg4_l2_wmr_out_c3t ,stg4_l2_por_out_c3t , |
| 4489 | stg4_spc0_clk_stop_out_c3t ,stg4_l2d0_clk_stop_out_c3t , |
| 4490 | stg4_l2d1_clk_stop_out_c3t ,stg4_l2b0_clk_stop_out_c3t , |
| 4491 | stg4_l2b1_clk_stop_out_c3t ,stg4_l2t0_clk_stop_out_c3t , |
| 4492 | stg3_l2b1_clk_stop_in_c3t ,stg3_l2t0_clk_stop_in_c3t , |
| 4493 | stg3_io_cmp_sync_en_in_c3t ,stg3_mio_io2x_sync_en_in_c3t , |
| 4494 | stg3_dr_sync_en_in_c3t ,stg3_io_out_in_c3t ,stg3_l2_wmr_in_c3t , |
| 4495 | stg3_l2_por_in_c3t ,stg3_spc0_clk_stop_in_c3t , |
| 4496 | stg3_cmp_io_sync_en_in_c3t ,stg3_l2d0_clk_stop_in_c3t , |
| 4497 | stg3_l2d1_clk_stop_in_c3t ,stg3_l2b0_clk_stop_in_c3t , |
| 4498 | // stg4_mcu1_dr_clk_stop_out_c3t , |
| 4499 | stg4_mio_clk_stop_out_c3t , |
| 4500 | stg4_mcu0_clk_stop_out_c3t ,stg4_mcu1_clk_stop_out_c3t , |
| 4501 | stg4_mcu0_io_clk_stop_out_c3t ,stg4_mcu1_io_clk_stop_out_c3t , |
| 4502 | // stg4_mcu0_dr_clk_stop_out_c3t , |
| 4503 | stg3_mcu0_clk_stop_in_c3t , |
| 4504 | stg3_mcu1_clk_stop_in_c3t ,stg3_mcu0_io_clk_stop_in_c3t , |
| 4505 | stg3_mcu1_io_clk_stop_in_c3t , |
| 4506 | // stg3_mcu0_dr_clk_stop_in_c3t , stg3_mcu1_dr_clk_stop_in_c3t , |
| 4507 | stg3_mio_clk_stop_in_c3t , |
| 4508 | gl_l2_wmr_c3t0 ,gl_cmp_io_sync_en_c3t ,gl_io_cmp_sync_en_c3t , |
| 4509 | gl_l2_wmr_c3t ,gl_l2_por_c3t ,gl_l2d0_clk_stop , |
| 4510 | gl_l2d1_clk_stop ,gl_l2b0_clk_stop ,gl_l2b1_clk_stop , |
| 4511 | gl_mio_clk_stop_c3t ,gl_io2x_sync_en_c3t , |
| 4512 | stg4_cmp_io_sync_en_in_c3t ,stg4_io2x_sync_en_in_c3t , |
| 4513 | stg4_spc0_clk_stop_in_c3t ,stg4_io_cmp_sync_en_in_c3t , |
| 4514 | stg4_l2_wmr_in_c3t ,gl_io_cmp_sync_en_c1t ,stg4_l2_por_in_c3t , |
| 4515 | gl_cmp_io_sync_en_c1t ,stg4_l2d0_clk_stop_in_c3t , |
| 4516 | stg4_l2d1_clk_stop_in_c3t ,stg3_mio_clk_stop_in_c2t , |
| 4517 | // stg4_spc1_clk_stop_out_c2b , |
| 4518 | stg4_l2b0_clk_stop_in_c3t ,stg4_l2b1_clk_stop_in_c3t , |
| 4519 | stg4_mio_clk_stop_in_c3t ,gclk_l2b4 ,stg3_io2x_sync_en_in_c2t , |
| 4520 | gclk_l2b5 ,gclk_l2b6 , stg2_ncu_io_clk_stop_in_c2b ,stg3_ccx_clk_stop_out_c2b , |
| 4521 | stg2_spc3_clk_stop_in_c2b ,stg3_l2b0_clk_stop_out_c2t , |
| 4522 | stg3_sii_clk_stop_out_c2b , |
| 4523 | stg2_l2t2_clk_stop_in_c2b ,stg3_cmp_io_sync_en_out_c2t , |
| 4524 | gl_l2_wmr_c1t ,gl_mio_io2x_sync_en_c1t ,gclk_l2t4 , |
| 4525 | stg1_cmp_io_sync_en_in_c1t,gclk_spc6 ,stg1_l2d5_clk_stop_in_c1t , |
| 4526 | stg3_l2b3_clk_stop_out_c2b ,stg2_l2t5_clk_stop_in_c2t , |
| 4527 | stg2_cmp_io_sync_en_in_c2t ,stg2_l2t3_clk_stop_in_c2bz , |
| 4528 | stg2_l2_wmr_in_c2b ,stg2_dmu_peu_wmr_in_c2b , |
| 4529 | stg2_spc2_clk_stop_in_c2b ,stg3_peu_io_clk_stop_out_c2b , |
| 4530 | stg3_ncu_io_clk_stop_out_c2b ,stg2_l2t7_clk_stop_in_c2b , |
| 4531 | stg2_ccx_clk_stop_in_c2b ,stg2_ncu_clk_stop_in_c2b , |
| 4532 | stg2_sii_io_clk_stop_in_c2b ,stg2_peu_io_clk_stop_in_c2b , |
| 4533 | stg3_l2_por_in_c2b ,stg3_l2_wmr_in_c2b ,stg3_cmp_io_sync_en_in_c2b, |
| 4534 | gl_spc3_clk_stop ,stg3_spc7_clk_stop_in_c2b ,gl_spc4_clk_stop , |
| 4535 | stg1_spc4_clk_stop_in_c1t, |
| 4536 | stg3_l2t5_clk_stop_out_c2t ,stg3_l2t0_clk_stop_out_c2t , |
| 4537 | stg3_l2b1_clk_stop_out_c2t ,stg3_l2d0_clk_stop_out_c2t , |
| 4538 | stg3_spc5_clk_stop_out_c2t ,stg3_io_out_out_c2t , |
| 4539 | stg3_io_cmp_sync_en_out_c2t ,stg3_l2_por_out_c2t , |
| 4540 | stg2_mio_clk_stop_out_c1t ,stg2_mcu0_clk_stop_out_c1t , |
| 4541 | // stg1_mcu0_dr_clk_stop_in_c1t , |
| 4542 | stg1_mio_clk_stop_in_c1t , |
| 4543 | stg2_dmu_peu_por_in_c2b ,stg2_spc7_clk_stop_in_c2b , |
| 4544 | stg2_db0_clk_stop_in_c2b ,stg3_sii_io_clk_stop_out_c2b , |
| 4545 | stg3_l2t7_clk_stop_out_c2b ,stg2_sii_clk_stop_in_c2b , |
| 4546 | stg2_dmu_io_clk_stop_in_c2b ,stg3_l2t3_clk_stop_in_c2b , |
| 4547 | stg3_io_cmp_sync_en_in_c2b ,stg3_spc3_clk_stop_in_c2b , |
| 4548 | stg3_l2t1_clk_stop_out_c2t ,stg3_l2d1_clk_stop_out_c2t , |
| 4549 | stg3_spc0_clk_stop_out_c2t ,stg3_l2_wmr_out_c2t , |
| 4550 | stg3_mio_io2x_sync_en_out_c2t ,stg2_l2b2_clk_stop_in_c2b , |
| 4551 | stg2_l2b3_clk_stop_in_c2b ,gl_l2b4_clk_stop , |
| 4552 | stg1_l2b4_clk_stop_in_c1t ,stg3_l2t2_clk_stop_out_c2b , |
| 4553 | stg3_l2d2_clk_stop_out_c2b ,stg3_l2d3_clk_stop_out_c2b , |
| 4554 | stg3_io_cmp_sync_en_out_c2b ,stg3_io_out_out_c2b , |
| 4555 | stg3_dmu_peu_wmr_out_c2b ,stg3_spc2_clk_stop_out_c2b , |
| 4556 | stg2_l2d2_clk_stop_in_c2b ,stg2_l2d3_clk_stop_in_c2b ,gl_l2_por_c1t |
| 4557 | ,stg1_l2d4_clk_stop_in_c1t ,stg3_l2t3_clk_stop_out_c2b , |
| 4558 | gl_l2b5_clk_stop ,stg3_db0_clk_stop_out_c2b , |
| 4559 | stg3_cmp_io_sync_en_out_c2b ,stg3_dmu_peu_por_out_c2b , |
| 4560 | stg3_spc3_clk_stop_out_c2b ,stg3_spc1_clk_stop_in_c2t , |
| 4561 | stg3_spc5_clk_stop_in_c2t ,stg2_dr_sync_en_in_c2t , |
| 4562 | stg2_l2_por_in_c2t ,stg2_spc5_clk_stop_in_c2t , |
| 4563 | stg2_l2b0_clk_stop_in_c2t ,stg2_l2t1_clk_stop_in_c2t , |
| 4564 | stg2_io_cmp_sync_en_in_c2t , |
| 4565 | stg2_mio_io2x_sync_en_in_c2t ,stg2_io_out_in_c2t , |
| 4566 | stg2_l2_wmr_in_c2t ,stg2_spc0_clk_stop_in_c2t , |
| 4567 | stg2_spc1_clk_stop_in_c2t ,stg2_l2d0_clk_stop_in_c2t , |
| 4568 | stg2_l2d1_clk_stop_in_c2t ,stg2_l2b1_clk_stop_in_c2t , |
| 4569 | stg2_l2t0_clk_stop_in_c2t ,gl_l2_wmr_c2t , |
| 4570 | // stg4_spc5_clk_stop_out_c2b , |
| 4571 | stg4_io_out_in_c3t , |
| 4572 | gl_mcu1_dr_clk_stop ,gclk_spc4 ,gl_mcu0_io_clk_stop , |
| 4573 | stg4_dr_sync_en_in_c3t ,stg4_io2x_sync_en_c3t , |
| 4574 | stg4_mcu1_io_clk_stop_in_c3t ,stg4_mcu0_io_clk_stop_in_c3t , |
| 4575 | // stg4_mcu1_dr_clk_stop_in_c3t , |
| 4576 | stg4_mcu1_clk_stop_in_c3t , |
| 4577 | gl_mcu0_dr_clk_stop ,gl_mcu1_clk_stop ,gl_mcu0_clk_stop |
| 4578 | ,gl_l2t0_clk_stop ,gl_io_out_c3t ,gl_dr_sync_en_c3t , |
| 4579 | gl_mcu1_io_clk_stop ,gclk_l2t6 ,// stg4_mcu0_dr_clk_stop_in_c3t , |
| 4580 | stg4_mcu0_clk_stop_in_c3t ,stg4_l2t0_clk_stop_in_c3t ,gclk_l2t2 , |
| 4581 | gclk_ncu ,gclk_spc2 ,gclk_l2b0 ,gclk_spc0 ,gclk_l2t0 ,gclk_spc5 , |
| 4582 | gclk_spc1 ,gclk_l2t5 ,gclk_l2t1 ,stg2_mcu1_clk_stop_out_c1t , |
| 4583 | stg1_mcu1_clk_stop_in_c1t ,stg1_mcu0_io_clk_stop_in_c1t , |
| 4584 | // stg2_mcu0_dr_clk_stop_out_c1t ,stg2_mcu1_dr_clk_stop_out_c1t , |
| 4585 | stg2_mcu1_io_clk_stop_out_c1t ,stg1_mcu1_io_clk_stop_in_c1t , |
| 4586 | // stg1_mcu1_dr_clk_stop_in_c1t , |
| 4587 | stg1_mcu0_clk_stop_in_c1t , |
| 4588 | stg2_mcu0_io_clk_stop_out_c1t ,stg3_dr_sync_en_out_c2t , |
| 4589 | stg3_spc1_clk_stop_out_c2t ,stg3_ccx_clk_stop_in_c2b , |
| 4590 | stg3_l2t7_clk_stop_in_c2b ,stg3_dmu_io_clk_stop_out_c2b , |
| 4591 | stg3_ncu_clk_stop_out_c2b ,stg2_l2_por_in_c2b , |
| 4592 | stg2_io_cmp_sync_en_in_c2b ,stg2_cmp_io_sync_en_in_c2b , |
| 4593 | stg3_l2_wmr_out_c2b , |
| 4594 | stg3_l2_por_out_c2b , |
| 4595 | stg3_l2b2_clk_stop_out_c2b ,stg1_l2b5_clk_stop_in_c1t , |
| 4596 | gl_l2d4_clk_stop ,gclk_l2d5 , |
| 4597 | stg1_mio_io2x_sync_en_in_c1t ,stg1_l2_wmr_in_c1t , |
| 4598 | stg1_l2_por_in_c1t ,stg1_spc1_clk_stop_in_c1t , |
| 4599 | stg1_l2b0_clk_stop_in_c1t ,stg1_l2t5_clk_stop_in_c1t , |
| 4600 | stg1_l2t1_clk_stop_in_c1t ,stg1_l2d1_clk_stop_in_c1t , |
| 4601 | stg1_io_cmp_sync_en_in_c1t ,stg1_io_out_in_c1t , |
| 4602 | stg1_l2d0_clk_stop_in_c1t ,stg1_l2t0_clk_stop_in_c1t , |
| 4603 | stg1_l2b1_clk_stop_in_c1t ,stg1_dr_sync_en_in_c1t , |
| 4604 | stg1_spc0_clk_stop_in_c1t ,stg1_spc5_clk_stop_in_c1t , |
| 4605 | stg2_spc1_clk_stop_out_c1t ,stg2_cmp_io_sync_en_out_c1t , |
| 4606 | stg2_l2_wmr_out_c1t ,stg2_mio_io2x_sync_en_out_c1t , |
| 4607 | stg2_dr_sync_en_out_c1t ,stg2_spc0_clk_stop_out_c1t , |
| 4608 | stg2_spc5_clk_stop_out_c1t ,stg2_l2d0_clk_stop_out_c1t , |
| 4609 | stg2_l2d1_clk_stop_out_c1t ,stg2_l2b1_clk_stop_out_c1t , |
| 4610 | stg2_l2b0_clk_stop_out_c1t ,stg2_l2t0_clk_stop_out_c1t , |
| 4611 | stg2_l2t5_clk_stop_out_c1t ,stg2_l2t1_clk_stop_out_c1t , |
| 4612 | stg2_io_out_out_c1t ,stg2_l2_por_out_c1t , |
| 4613 | stg2_io_cmp_sync_en_out_c1t ,gl_io_out_c1b ,gl_io2x_out_c1b , |
| 4614 | gl_rst_niu_wmr_c1b ,gl_rst_mac_c1b ,stg1_io2x_out_in_c1b , |
| 4615 | stg1_io_out_in_c1b ,stg1_rst_mac_in_c1b ,stg1_rst_niu_wmr_in_c1b , |
| 4616 | gl_rtx_io_clk_stop ,gl_rdp_io_clk_stop ,gl_tds_io_clk_stop , |
| 4617 | gl_mac_io_clk_stop ,stg1_tds_io_clk_stop_in_c1b , |
| 4618 | stg1_rdp_io_clk_stop_in_c1b ,stg1_rtx_io_clk_stop_in_c1b , |
| 4619 | stg1_mac_io_clk_stop_in_c1b ,gl_spc6_clk_stop , |
| 4620 | gl_l2d7_clk_stop , |
| 4621 | stg1_l2d7_clk_stop_in_c1b ,stg1_spc6_clk_stop_in_c1b |
| 4622 | ,gl_io_cmp_sync_en_c1b ,gl_l2_wmr_c1b , |
| 4623 | gl_cmp_io_sync_en_c1b ,stg2_ccx_clk_stop_out_c1b , |
| 4624 | stg2_l2t7_clk_stop_out_c1b ,stg2_ncu_clk_stop_out_c1b , |
| 4625 | stg2_sii_clk_stop_out_c1b ,stg2_peu_io_clk_stop_out_c1b , |
| 4626 | stg2_ncu_io_clk_stop_out_c1b ,stg2_sii_io_clk_stop_out_c1b , |
| 4627 | stg2_dmu_io_clk_stop_out_c1b ,stg1_peu_io_clk_stop_in_c1b , |
| 4628 | stg1_dmu_io_clk_stop_in_c1b ,stg1_ccx_clk_stop_in_c1b , |
| 4629 | stg1_sii_clk_stop_in_c1b ,stg1_ncu_io_clk_stop_in_c1b , |
| 4630 | stg1_sii_io_clk_stop_in_c1b ,stg1_ncu_clk_stop_in_c1b , |
| 4631 | stg1_l2t7_clk_stop_in_c1b ,stg2_spc7_clk_stop_out_c1b , |
| 4632 | stg2_spc2_clk_stop_out_c1b ,stg2_io_cmp_sync_en_out_c1b , |
| 4633 | stg2_l2d3_clk_stop_out_c1b , |
| 4634 | stg2_dmu_peu_por_out_c1b ,stg2_dmu_peu_wmr_out_c1b , |
| 4635 | stg2_l2_por_out_c1b ,stg2_db0_clk_stop_out_c1b , |
| 4636 | stg2_cmp_io_sync_en_out_c1b ,stg2_spc3_clk_stop_out_c1b , |
| 4637 | stg2_l2_wmr_out_c1b ,stg2_l2t3_clk_stop_out_c1b , |
| 4638 | stg2_l2t2_clk_stop_out_c1b ,stg2_l2b3_clk_stop_out_c1b , |
| 4639 | stg2_l2b2_clk_stop_out_c1b , stg1_l2_por_in_c1b , |
| 4640 | stg1_db0_clk_stop_in_c1b ,stg1_l2b3_clk_stop_in_c1b , |
| 4641 | stg1_dmu_peu_por_in_c1b ,stg1_dmu_peu_wmr_in_c1b , |
| 4642 | stg1_l2t2_clk_stop_in_c1b ,stg1_l2d3_clk_stop_in_c1b , |
| 4643 | stg1_spc2_clk_stop_in_c1b ,stg1_spc7_clk_stop_in_c1b , |
| 4644 | stg1_spc3_clk_stop_in_c1b ,stg1_io_cmp_sync_en_in_c1b , |
| 4645 | stg1_cmp_io_sync_en_in_c1b ,stg1_l2b2_clk_stop_in_c1b , |
| 4646 | stg1_l2_wmr_in_c1b ,stg1_l2t3_clk_stop_in_c1b ,gclk_tcu ,gclk_ccu , |
| 4647 | gclk_rst , dr_gclk_stg_tcu, dr_gclk_fsr7_stg, dr_gclk_c4_mcu1, |
| 4648 | gl_mio_clk_stop_c2t ,gl_spc7_clk_stop,gl_l2_por_c2b , |
| 4649 | gl_l2t7_clk_stop ,gl_l2t3_clk_stop ,gl_l2_wmr_c2b , |
| 4650 | gl_io_cmp_sync_en_c2b ,gl_cmp_io_sync_en_c2b , |
| 4651 | gl_ccx_clk_stop ,ccu_io2x_sync_en ,ccu_cmp_io_sync_en , |
| 4652 | ccu_dr_sync_en ,ccu_io2x_out ,rst_niu_mac_ ,rst_dmu_peu_wmr_ , |
| 4653 | rst_niu_wmr_ ,rst_dmu_peu_por_ ,stg1_mio_clk_stop_out_c1t , |
| 4654 | stg1_spc5_clk_stop_out_c1t ,stg1_spc4_clk_stop_out_c1t , |
| 4655 | stg1_spc1_clk_stop_out_c1t ,stg1_spc0_clk_stop_out_c1t , |
| 4656 | stg1_mcu1_io_clk_stop_out_c1t ,stg1_mcu1_dr_clk_stop_out_c1t , |
| 4657 | stg1_mcu1_clk_stop_out_c1t ,stg1_mcu0_io_clk_stop_out_c1t , |
| 4658 | stg1_mcu0_dr_clk_stop_out_c1t ,stg1_mcu0_clk_stop_out_c1t , |
| 4659 | stg1_l2t1_clk_stop_out_c1t ,stg1_l2t0_clk_stop_out_c1t , |
| 4660 | stg1_l2d5_clk_stop_out_c1t ,stg1_l2d4_clk_stop_out_c1t , |
| 4661 | stg1_l2d1_clk_stop_out_c1t ,stg1_l2d0_clk_stop_out_c1t , |
| 4662 | stg1_l2b5_clk_stop_out_c1t ,stg1_l2b4_clk_stop_out_c1t , |
| 4663 | stg1_l2b0_clk_stop_out_c1t ,stg1_l2t5_clk_stop_out_c1t , |
| 4664 | gl_l2t4_clk_stop ,gl_ccu_clk_stop ,gl_ccu_io_clk_stop , |
| 4665 | gl_mcu2_io_clk_stop ,gl_mcu2_dr_clk_stop ,gl_mcu2_clk_stop , |
| 4666 | gl_mcu3_io_clk_stop ,gl_mcu3_dr_clk_stop ,gl_mcu3_clk_stop , |
| 4667 | gl_l2b7_clk_stop ,gl_l2d6_clk_stop ,gl_l2b6_clk_stop , |
| 4668 | gl_l2t6_clk_stop ,gl_sio_clk_stop ,gl_sio_io_clk_stop , |
| 4669 | gl_db1_clk_stop ,gl_rst_clk_stop ,gl_rst_io_clk_stop , |
| 4670 | gl_efu_clk_stop ,gl_efu_io_clk_stop ,stg1_ncu_clk_stop_out_c1b , |
| 4671 | stg1_mcu0_dr_clk_stop_in_c2b, stg1_mcu1_dr_clk_stop_in_c2b, |
| 4672 | stg2_mcu0_dr_clk_stop_in_c4t, stg2_mcu1_dr_clk_stop_in_c4t, |
| 4673 | stg2_mcu0_dr_clk_stop_out_c2b, stg2_mcu1_dr_clk_stop_out_c2b, |
| 4674 | stg1_ncu_io_clk_stop_out_c1b ,stg1_dmu_io_clk_stop_out_c1b , |
| 4675 | stg1_peu_io_clk_stop_out_c1b ,stg1_ccx_clk_stop_out_c1b , |
| 4676 | stg1_db0_clk_stop_out_c1b ,stg1_l2t7_clk_stop_out_c1b , |
| 4677 | stg1_sii_clk_stop_out_c1b ,stg1_sii_io_clk_stop_out_c1b , |
| 4678 | stg1_l2b2_clk_stop_out_c1b ,stg1_l2b3_clk_stop_out_c1b , |
| 4679 | stg1_l2d7_clk_stop_out_c1b ,stg1_l2d2_clk_stop_out_c1b , |
| 4680 | stg1_l2d3_clk_stop_out_c1b ,stg1_l2t2_clk_stop_out_c1b , |
| 4681 | stg1_l2t3_clk_stop_out_c1b ,stg1_tds_io_clk_stop_out_c1b , |
| 4682 | stg1_rdp_io_clk_stop_out_c1b ,stg1_rtx_io_clk_stop_out_c1b , |
| 4683 | stg1_mac_io_clk_stop_out_c1b ,stg1_spc2_clk_stop_out_c1b , |
| 4684 | ccu_io_cmp_sync_en ,ccu_io_out ,gl_dr_sync_en_c1m ,rst_l2_por_ , |
| 4685 | stg1_spc3_clk_stop_out_c1b ,stg1_spc6_clk_stop_out_c1b , |
| 4686 | stg1_spc7_clk_stop_out_c1b ,rst_l2_wmr_ ,tcu_l2b1_clk_stop , |
| 4687 | tcu_l2b2_clk_stop ,tcu_l2b3_clk_stop ,tcu_l2b4_clk_stop , |
| 4688 | tcu_l2b5_clk_stop ,tcu_l2b6_clk_stop ,gl_io_out_c1m , |
| 4689 | tcu_l2b7_clk_stop ,tcu_mcu1_clk_stop ,tcu_mcu2_clk_stop , |
| 4690 | tcu_mcu3_clk_stop ,tcu_mcu0_io_clk_stop ,tcu_mcu1_io_clk_stop , |
| 4691 | tcu_mcu2_io_clk_stop ,tcu_mcu3_io_clk_stop ,tcu_spc5_clk_stop , |
| 4692 | tcu_l2t1_clk_stop ,tcu_l2t7_clk_stop ,tcu_mcu1_dr_clk_stop , |
| 4693 | tcu_mcu2_dr_clk_stop ,tcu_mcu3_dr_clk_stop ,tcu_dmu_io_clk_stop , |
| 4694 | tcu_peu_io_clk_stop ,tcu_mac_io_clk_stop ,tcu_tds_io_clk_stop , |
| 4695 | tcu_rtx_io_clk_stop ,tcu_rdp_io_clk_stop ,tcu_l2t0_clk_stop , |
| 4696 | tcu_efu_io_clk_stop ,tcu_ccx_clk_stop ,tcu_ncu_clk_stop , |
| 4697 | tcu_sii_clk_stop ,tcu_ncu_io_clk_stop ,tcu_sio_clk_stop , |
| 4698 | tcu_sii_io_clk_stop ,tcu_db0_clk_stop ,tcu_mio_clk_stop , |
| 4699 | tcu_rst_io_clk_stop ,tcu_sio_io_clk_stop ,tcu_mcu0_dr_clk_stop , |
| 4700 | tcu_mcu0_clk_stop ,tcu_ccu_io_clk_stop ,tcu_efu_clk_stop , |
| 4701 | tcu_rst_clk_stop ,tcu_ccu_clk_stop ,tcu_db1_clk_stop , |
| 4702 | tcu_l2d0_clk_stop ,tcu_l2d1_clk_stop ,tcu_l2d2_clk_stop , |
| 4703 | tcu_l2d3_clk_stop ,tcu_l2d4_clk_stop ,tcu_l2d5_clk_stop , |
| 4704 | tcu_l2d7_clk_stop ,tcu_l2d6_clk_stop ,tcu_l2b0_clk_stop , |
| 4705 | tcu_spc0_clk_stop ,tcu_spc1_clk_stop ,tcu_spc2_clk_stop , |
| 4706 | tcu_spc3_clk_stop ,stg1_rst_niu_wmr_out_c1b , |
| 4707 | stg1_l2b1_clk_stop_out_c1t ,tcu_spc4_clk_stop ,tcu_l2t6_clk_stop , |
| 4708 | tcu_spc6_clk_stop ,tcu_spc7_clk_stop ,tcu_l2t4_clk_stop , |
| 4709 | tcu_l2t3_clk_stop ,tcu_l2t2_clk_stop ,tcu_l2t5_clk_stop , |
| 4710 | stg1_io_out_out_c1b ,stg1_io2x_sync_en_out_c1b , |
| 4711 | stg1_io2x_sync_en_out_c1t ,stg1_dr_sync_en_out_c1t , |
| 4712 | gl_io_cmp_sync_en_c1m ,stg1_cmp_io_sync_en_out_c1b , |
| 4713 | gl_rst_l2_wmr_c1m ,stg1_io2x_out_out_c1b , |
| 4714 | stg3_spc7_clk_stop_out_c2b ,gl_cmp_io_sync_en_c1m , |
| 4715 | stg1_rst_l2_wmr_out_c1t ,stg1_io_cmp_sync_en_out_c1b , |
| 4716 | stg1_rst_l2_por_out_c1b ,stg1_rst_l2_wmr_out_c1b ,gl_rst_l2_por_c1m |
| 4717 | ,gl_io2x_sync_en_c1m ,stg1_dmu_peu_por_out_c1b , |
| 4718 | stg1_io_out_out_c1t ,stg1_io_cmp_sync_en_out_c1t , |
| 4719 | stg1_cmp_io_sync_en_out_c1t ,stg1_dmu_peu_wmr_out_c1b , |
| 4720 | stg2_io_out_in_c2b, gl_l2_por_c1b, // for int6.1 |
| 4721 | stg1_rst_l2_por_out_c1t ,stg1_rst_niu_mac_out_c1b ); |
| 4722 | |
| 4723 | // for int6.1 (set 3) |
| 4724 | input gclk_spc6s; |
| 4725 | input stg1_cmp_io_sync_en_in_c1bg; |
| 4726 | input stg1_cmp_io_sync_en_in_c1tg; |
| 4727 | input stg1_io_cmp_sync_en_in_c1bg; |
| 4728 | input stg1_io_cmp_sync_en_in_c1tg; |
| 4729 | input stg1_io_out_in_c1bg; |
| 4730 | input stg1_l2_por_in_c1bg; |
| 4731 | input stg1_l2_por_in_c1tg; |
| 4732 | input stg1_l2_wmr_in_c1bg; |
| 4733 | input stg1_l2_wmr_in_c1tg; |
| 4734 | input stg1_mio_clk_stop_in_c1tg; |
| 4735 | input stg1_mio_io2x_sync_en_in_c1tg; |
| 4736 | input stg4_cmp_io_sync_en_in_c3t0; |
| 4737 | input stg4_io_cmp_sync_en_in_c3t0; |
| 4738 | input stg4_io_out_in_c3b0; |
| 4739 | input stg4_l2_por_in_c3t0; |
| 4740 | input stg4_l2_wmr_in_c3t0; |
| 4741 | |
| 4742 | input stg2_io2x_sync_en_in_c2t; |
| 4743 | input ccu_vco_aligned ; |
| 4744 | input gclk_a ; |
| 4745 | input gclk_b ; |
| 4746 | input gclk_c ; |
| 4747 | input ccu_cmp_io_sync_en ; |
| 4748 | input ccu_dr_sync_en ; |
| 4749 | input ccu_io2x_out ; |
| 4750 | input ccu_io2x_sync_en ; |
| 4751 | input ccu_io_cmp_sync_en ; |
| 4752 | input ccu_io_out ; |
| 4753 | input gclk_ccu ; |
| 4754 | input gclk_dmu ; |
| 4755 | input gclk_l2b0 ; |
| 4756 | input gclk_l2b4 ; |
| 4757 | input gclk_l2b5 ; |
| 4758 | input gclk_l2b6 ; |
| 4759 | input gclk_l2d2 ; |
| 4760 | input gclk_l2d5 ; |
| 4761 | input gclk_l2d6 ; |
| 4762 | input gclk_l2t0 ; |
| 4763 | input gclk_l2t1 ; |
| 4764 | input gclk_l2t2 ; |
| 4765 | input gclk_l2t3 ; |
| 4766 | input gclk_l2t4 ; |
| 4767 | input gclk_l2t5 ; |
| 4768 | input gclk_l2t6 ; |
| 4769 | input gclk_l2t7 ; |
| 4770 | input gclk_mac ; |
| 4771 | input gclk_ncu ; |
| 4772 | input gclk_rst ; |
| 4773 | input gclk_spc0 ; |
| 4774 | input gclk_spc1 ; |
| 4775 | input gclk_spc2 ; |
| 4776 | input gclk_spc3 ; |
| 4777 | input gclk_spc4 ; |
| 4778 | input gclk_spc5 ; |
| 4779 | input gclk_spc6 ; |
| 4780 | input gclk_spc7 ; |
| 4781 | input gclk_tcu ; |
| 4782 | input dr_gclk_stg_tcu; |
| 4783 | input dr_gclk_fsr7_stg; |
| 4784 | input dr_gclk_c4_mcu1; |
| 4785 | input rst_dmu_peu_por_ ; |
| 4786 | input rst_dmu_peu_wmr_ ; |
| 4787 | input rst_l2_por_ ; |
| 4788 | input rst_l2_wmr_ ; |
| 4789 | input rst_niu_mac_ ; |
| 4790 | input rst_niu_wmr_ ; |
| 4791 | // input spare2_c1b_in ; |
| 4792 | // input spare3_c1b_in ; |
| 4793 | // input spare_c2b_s2_in6 ; |
| 4794 | input stg1_ccx_clk_stop_in_c1b ; |
| 4795 | input stg1_cmp_io_sync_en_in_c1t; |
| 4796 | input stg1_cmp_io_sync_en_in_c1b ; |
| 4797 | input stg1_db0_clk_stop_in_c1b ; |
| 4798 | input stg1_dmu_io_clk_stop_in_c1b ; |
| 4799 | input stg1_dmu_peu_por_in_c1b ; |
| 4800 | input stg1_dmu_peu_wmr_in_c1b ; |
| 4801 | input stg1_dr_sync_en_in_c1t ; |
| 4802 | input stg1_io2x_out_in_c1b ; |
| 4803 | input stg1_io_cmp_sync_en_in_c1t ; |
| 4804 | input stg1_io_cmp_sync_en_in_c1b ; |
| 4805 | input stg1_io_out_in_c1b ; |
| 4806 | input stg1_io_out_in_c1t ; |
| 4807 | input stg1_l2_por_in_c1b ; |
| 4808 | input stg1_l2_por_in_c1t ; |
| 4809 | input stg1_l2_wmr_in_c1b ; |
| 4810 | input stg1_l2_wmr_in_c1t ; |
| 4811 | input stg1_l2b0_clk_stop_in_c1t ; |
| 4812 | input stg1_l2b1_clk_stop_in_c1t ; |
| 4813 | input stg1_l2b2_clk_stop_in_c1b ; |
| 4814 | input stg1_l2b3_clk_stop_in_c1b ; |
| 4815 | input stg1_l2b4_clk_stop_in_c1t ; |
| 4816 | input stg1_l2b5_clk_stop_in_c1t ; |
| 4817 | input stg1_l2d0_clk_stop_in_c1t ; |
| 4818 | input stg1_l2d1_clk_stop_in_c1t ; |
| 4819 | input stg1_l2d2_clk_stop_in_c1b ; |
| 4820 | input stg1_l2d3_clk_stop_in_c1b ; |
| 4821 | input stg1_l2d4_clk_stop_in_c1t ; |
| 4822 | input stg1_l2d5_clk_stop_in_c1t ; |
| 4823 | input stg1_l2d7_clk_stop_in_c1b ; |
| 4824 | input stg1_l2t0_clk_stop_in_c1t ; |
| 4825 | input stg1_l2t1_clk_stop_in_c1t ; |
| 4826 | input stg1_l2t2_clk_stop_in_c1b ; |
| 4827 | input stg1_l2t3_clk_stop_in_c1b ; |
| 4828 | input stg1_l2t5_clk_stop_in_c1t ; |
| 4829 | input stg1_l2t7_clk_stop_in_c1b ; |
| 4830 | input stg1_mac_io_clk_stop_in_c1b ; |
| 4831 | input stg1_mcu0_clk_stop_in_c1t ; |
| 4832 | // input stg1_mcu0_dr_clk_stop_in_c1t ; |
| 4833 | input stg1_mcu0_io_clk_stop_in_c1t ; |
| 4834 | input stg1_mcu1_clk_stop_in_c1t ; |
| 4835 | // input stg1_mcu1_dr_clk_stop_in_c1t ; |
| 4836 | input stg1_mcu1_io_clk_stop_in_c1t ; |
| 4837 | input stg1_mio_clk_stop_in_c1t ; |
| 4838 | input stg1_mio_io2x_sync_en_in_c1t ; |
| 4839 | input stg1_ncu_clk_stop_in_c1b ; |
| 4840 | input stg1_ncu_io_clk_stop_in_c1b ; |
| 4841 | input stg1_peu_io_clk_stop_in_c1b ; |
| 4842 | input stg1_rdp_io_clk_stop_in_c1b ; |
| 4843 | input stg1_rst_mac_in_c1b ; |
| 4844 | input stg1_rst_niu_wmr_in_c1b ; |
| 4845 | input stg1_tds_io_clk_stop_in_c1b ; |
| 4846 | input stg1_rtx_io_clk_stop_in_c1b ; |
| 4847 | input stg1_sii_clk_stop_in_c1b ; |
| 4848 | input stg1_sii_io_clk_stop_in_c1b ; |
| 4849 | input stg1_spc0_clk_stop_in_c1t ; |
| 4850 | input stg1_spc1_clk_stop_in_c1t ; |
| 4851 | input stg1_spc2_clk_stop_in_c1b ; |
| 4852 | input stg1_spc3_clk_stop_in_c1b ; |
| 4853 | input stg1_spc5_clk_stop_in_c1t ; |
| 4854 | input stg1_spc6_clk_stop_in_c1b ; |
| 4855 | input stg1_spc7_clk_stop_in_c1b ; |
| 4856 | input stg2_ccx_clk_stop_in_c2b ; |
| 4857 | input stg2_cmp_io_sync_en_in_c2b ; |
| 4858 | input stg2_cmp_io_sync_en_in_c2t ; |
| 4859 | input stg2_db0_clk_stop_in_c2b ; |
| 4860 | input stg2_dmu_io_clk_stop_in_c2b ; |
| 4861 | input stg2_dmu_peu_por_in_c2b ; |
| 4862 | input stg2_dmu_peu_wmr_in_c2b ; |
| 4863 | input stg2_dr_sync_en_in_c2t ; |
| 4864 | input stg2_io_cmp_sync_en_in_c2b ; |
| 4865 | input stg2_io_cmp_sync_en_in_c2t ; |
| 4866 | input stg2_io_out_in_c2t ; |
| 4867 | input stg2_l2_por_in_c2b ; |
| 4868 | input stg2_l2_por_in_c2t ; |
| 4869 | input stg2_l2_wmr_in_c2b ; |
| 4870 | input stg2_l2_wmr_in_c2t ; |
| 4871 | input stg2_l2b0_clk_stop_in_c2t ; |
| 4872 | input stg2_l2b1_clk_stop_in_c2t ; |
| 4873 | input stg2_l2b2_clk_stop_in_c2b ; |
| 4874 | input stg2_l2b3_clk_stop_in_c2b ; |
| 4875 | input stg2_l2d0_clk_stop_in_c2t ; |
| 4876 | input stg2_l2d1_clk_stop_in_c2t ; |
| 4877 | input stg2_l2d2_clk_stop_in_c2b ; |
| 4878 | input stg2_l2d3_clk_stop_in_c2b ; |
| 4879 | input stg2_l2t0_clk_stop_in_c2t ; |
| 4880 | input stg2_l2t1_clk_stop_in_c2t ; |
| 4881 | input stg2_l2t2_clk_stop_in_c2b ; |
| 4882 | input stg2_l2t3_clk_stop_in_c2bz ; |
| 4883 | input stg2_l2t5_clk_stop_in_c2t ; |
| 4884 | input stg2_l2t7_clk_stop_in_c2b ; |
| 4885 | input stg2_mio_io2x_sync_en_in_c2t ; |
| 4886 | input stg2_ncu_clk_stop_in_c2b ; |
| 4887 | input stg2_ncu_io_clk_stop_in_c2b ; |
| 4888 | input stg2_peu_io_clk_stop_in_c2b ; |
| 4889 | input stg2_sii_clk_stop_in_c2b ; |
| 4890 | input stg2_sii_io_clk_stop_in_c2b ; |
| 4891 | input stg2_spc0_clk_stop_in_c2t ; |
| 4892 | input stg2_spc1_clk_stop_in_c2t ; |
| 4893 | input stg2_spc2_clk_stop_in_c2b ; |
| 4894 | input stg2_spc3_clk_stop_in_c2b ; |
| 4895 | input stg2_spc5_clk_stop_in_c2t ; |
| 4896 | input stg2_spc7_clk_stop_in_c2b ; |
| 4897 | input stg3_ccx_clk_stop_in_c2b ; |
| 4898 | input stg3_cmp_io_sync_en_in_c2b ; |
| 4899 | input stg3_cmp_io_sync_en_in_c2t ; |
| 4900 | input stg3_cmp_io_sync_en_in_c3b ; |
| 4901 | input stg3_cmp_io_sync_en_in_c3t ; |
| 4902 | input stg3_db0_clk_stop_in_c3b ; |
| 4903 | input stg3_dmu_io_clk_stop_in_c3b ; |
| 4904 | input stg3_dmu_peu_por_in_c3b ; |
| 4905 | input stg3_dmu_peu_wmr_in_c3b ; |
| 4906 | input stg3_dr_sync_en_in_c3t ; |
| 4907 | input stg3_io2x_sync_en_in_c2t ; |
| 4908 | input stg3_io_cmp_sync_en_in_c2b ; |
| 4909 | input stg3_io_cmp_sync_en_in_c2t ; |
| 4910 | input stg3_io_cmp_sync_en_in_c3b ; |
| 4911 | input stg3_io_cmp_sync_en_in_c3t ; |
| 4912 | input stg3_io_out_in_c3b ; |
| 4913 | input stg3_io_out_in_c3t ; |
| 4914 | input stg3_l2_por_in_c2b ; |
| 4915 | input stg3_l2_por_in_c2t ; |
| 4916 | input stg3_l2_por_in_c3b ; |
| 4917 | input stg3_l2_por_in_c3t ; |
| 4918 | input stg3_l2_wmr_in_c2b ; |
| 4919 | input stg3_l2_wmr_in_c2t ; |
| 4920 | input stg3_l2_wmr_in_c3b ; |
| 4921 | input stg3_l2_wmr_in_c3t ; |
| 4922 | input stg3_l2b0_clk_stop_in_c3t ; |
| 4923 | input stg3_l2b1_clk_stop_in_c3t ; |
| 4924 | input stg3_l2b2_clk_stop_in_c3b ; |
| 4925 | input stg3_l2b3_clk_stop_in_c3b ; |
| 4926 | input stg3_l2d0_clk_stop_in_c3t ; |
| 4927 | input stg3_l2d1_clk_stop_in_c3t ; |
| 4928 | input stg3_l2d2_clk_stop_in_c3b ; |
| 4929 | input stg3_l2d3_clk_stop_in_c3b ; |
| 4930 | input stg3_l2t0_clk_stop_in_c3t ; |
| 4931 | input stg3_l2t1_clk_stop_in_c2t ; |
| 4932 | input stg3_l2t3_clk_stop_in_c2b ; |
| 4933 | input stg3_l2t5_clk_stop_in_c2t ; |
| 4934 | input stg3_l2t7_clk_stop_in_c2b ; |
| 4935 | input stg3_mcu0_clk_stop_in_c3t ; |
| 4936 | // input stg3_mcu0_dr_clk_stop_in_c3t ; |
| 4937 | input stg3_mcu0_io_clk_stop_in_c3t ; |
| 4938 | input stg3_mcu1_clk_stop_in_c3t ; |
| 4939 | // input stg3_mcu1_dr_clk_stop_in_c3t ; |
| 4940 | input stg3_mcu1_io_clk_stop_in_c3t ; |
| 4941 | input stg3_mio_clk_stop_in_c2t ; |
| 4942 | input stg3_mio_clk_stop_in_c3t ; |
| 4943 | input stg3_mio_io2x_sync_en_in_c3t ; |
| 4944 | input stg3_ncu_clk_stop_in_c3b ; |
| 4945 | input stg3_ncu_io_clk_stop_in_c3b ; |
| 4946 | input stg3_peu_io_clk_stop_in_c3b ; |
| 4947 | input stg3_sii_clk_stop_in_c3b ; |
| 4948 | input stg3_sii_io_clk_stop_in_c3b ; |
| 4949 | input stg3_spc0_clk_stop_in_c3t ; |
| 4950 | input stg3_spc1_clk_stop_in_c2t ; // for int6.1 |
| 4951 | input stg3_spc2_clk_stop_in_c3b ; |
| 4952 | input stg3_spc3_clk_stop_in_c2b ; |
| 4953 | input stg3_spc5_clk_stop_in_c2t ; // for int6.1 |
| 4954 | input stg3_spc7_clk_stop_in_c2b ; |
| 4955 | input stg4_cmp_io_sync_en_in_c3b ; |
| 4956 | input stg4_cmp_io_sync_en_in_c3t ; |
| 4957 | input stg4_db0_clk_stop_c3b ; |
| 4958 | input stg4_dmu_io_clk_stop_in_c3b ; |
| 4959 | input stg4_dmu_peu_por_in_c3b ; |
| 4960 | input stg4_dmu_peu_wmr_in_c3b ; |
| 4961 | input stg4_dr_sync_en_in_c3t ; |
| 4962 | input stg4_io2x_sync_en_in_c3t ; |
| 4963 | input stg4_io_cmp_sync_en_in_c3b ; |
| 4964 | input stg4_io_cmp_sync_en_in_c3t ; |
| 4965 | input stg4_io_out_in_c3b ; |
| 4966 | input stg4_io_out_in_c3t ; |
| 4967 | input stg4_l2_por_in_c3b ; |
| 4968 | input stg4_l2_por_in_c3t ; |
| 4969 | input stg4_l2_wmr_in_c3b ; |
| 4970 | input stg4_l2_wmr_in_c3t ; |
| 4971 | input stg4_l2b0_clk_stop_in_c3t ; |
| 4972 | input stg4_l2b1_clk_stop_in_c3t ; |
| 4973 | input stg4_l2b2_clk_stop_in_c3b ; |
| 4974 | input stg4_l2b3_clk_stop_in_c3b ; |
| 4975 | input stg4_l2d0_clk_stop_in_c3t ; |
| 4976 | input stg4_l2d1_clk_stop_in_c3t ; |
| 4977 | input stg4_l2d2_clk_stop_in_c3b ; |
| 4978 | input stg4_l2d3_clk_stop_in_c3b ; |
| 4979 | input stg4_l2t0_clk_stop_in_c3t ; |
| 4980 | input stg4_l2t2_clk_stop_in_c3b ; |
| 4981 | // input stg4_mcu1_dr_clk_stop_in_c3t ; |
| 4982 | input stg4_mcu0_clk_stop_in_c3t ; |
| 4983 | // input stg4_mcu0_dr_clk_stop_in_c3t ; |
| 4984 | input stg4_mcu0_io_clk_stop_in_c3t ; |
| 4985 | input stg4_mcu1_clk_stop_in_c3t ; |
| 4986 | input stg4_mcu1_io_clk_stop_in_c3t ; |
| 4987 | input stg4_mio_clk_stop_in_c3t ; |
| 4988 | input stg4_ncu_clk_stop_in_c3b ; |
| 4989 | input stg4_ncu_io_clk_stop_c3b ; |
| 4990 | input stg4_peu_io_clk_stop_in_c3b ; |
| 4991 | input stg4_sii_clk_stop_in_c3b ; |
| 4992 | input stg4_sii_io_clk_stop_in_c3b ; |
| 4993 | input stg4_spc0_clk_stop_in_c3t ; |
| 4994 | input stg4_spc2_clk_stop_in_c3b ; |
| 4995 | input stg1_spc4_clk_stop_in_c1t; |
| 4996 | input tcu_ccu_clk_stop ; |
| 4997 | input tcu_ccu_io_clk_stop ; |
| 4998 | input tcu_ccx_clk_stop ; |
| 4999 | input tcu_db0_clk_stop ; |
| 5000 | input tcu_db1_clk_stop ; |
| 5001 | input tcu_dmu_io_clk_stop ; |
| 5002 | input tcu_efu_clk_stop ; |
| 5003 | input tcu_efu_io_clk_stop ; |
| 5004 | input tcu_l2b0_clk_stop ; |
| 5005 | input tcu_l2b1_clk_stop ; |
| 5006 | input tcu_l2b2_clk_stop ; |
| 5007 | input tcu_l2b3_clk_stop ; |
| 5008 | input tcu_l2b4_clk_stop ; |
| 5009 | input tcu_l2b5_clk_stop ; |
| 5010 | input tcu_l2b6_clk_stop ; |
| 5011 | input tcu_l2b7_clk_stop ; |
| 5012 | input tcu_l2d0_clk_stop ; |
| 5013 | input tcu_l2d1_clk_stop ; |
| 5014 | input tcu_l2d2_clk_stop ; |
| 5015 | input tcu_l2d3_clk_stop ; |
| 5016 | input tcu_l2d4_clk_stop ; |
| 5017 | input tcu_l2d5_clk_stop ; |
| 5018 | input tcu_l2d7_clk_stop ; |
| 5019 | input tcu_l2d6_clk_stop ; |
| 5020 | input tcu_l2t0_clk_stop ; |
| 5021 | input tcu_l2t1_clk_stop ; |
| 5022 | input tcu_l2t2_clk_stop ; |
| 5023 | input tcu_l2t3_clk_stop ; |
| 5024 | input tcu_l2t4_clk_stop ; |
| 5025 | input tcu_l2t5_clk_stop ; |
| 5026 | input tcu_l2t6_clk_stop ; |
| 5027 | input tcu_l2t7_clk_stop ; |
| 5028 | input tcu_mac_io_clk_stop ; |
| 5029 | input tcu_mcu0_clk_stop ; |
| 5030 | input tcu_mcu0_dr_clk_stop ; |
| 5031 | input tcu_mcu0_io_clk_stop ; |
| 5032 | input tcu_mcu1_clk_stop ; |
| 5033 | input tcu_mcu1_dr_clk_stop ; |
| 5034 | input tcu_mcu1_io_clk_stop ; |
| 5035 | input tcu_mcu2_clk_stop ; |
| 5036 | input tcu_mcu2_dr_clk_stop ; |
| 5037 | input tcu_mcu2_io_clk_stop ; |
| 5038 | input tcu_mcu3_clk_stop ; |
| 5039 | input tcu_mcu3_dr_clk_stop ; |
| 5040 | input tcu_mcu3_io_clk_stop ; |
| 5041 | input tcu_mio_clk_stop ; |
| 5042 | input tcu_ncu_clk_stop ; |
| 5043 | input tcu_ncu_io_clk_stop ; |
| 5044 | input tcu_peu_io_clk_stop ; |
| 5045 | input tcu_rdp_io_clk_stop ; |
| 5046 | input tcu_rst_clk_stop ; |
| 5047 | input tcu_rst_io_clk_stop ; |
| 5048 | input tcu_rtx_io_clk_stop ; |
| 5049 | input tcu_sii_clk_stop ; |
| 5050 | input tcu_sii_io_clk_stop ; |
| 5051 | input tcu_sio_clk_stop ; |
| 5052 | input tcu_sio_io_clk_stop ; |
| 5053 | input tcu_spc0_clk_stop ; |
| 5054 | input tcu_spc1_clk_stop ; |
| 5055 | input tcu_spc2_clk_stop ; |
| 5056 | input tcu_spc3_clk_stop ; |
| 5057 | input tcu_spc4_clk_stop ; |
| 5058 | input tcu_spc5_clk_stop ; |
| 5059 | input tcu_spc6_clk_stop ; |
| 5060 | input tcu_spc7_clk_stop ; |
| 5061 | input tcu_tds_io_clk_stop ; |
| 5062 | input stg3_l2t2_clk_stop_in_c3b ; |
| 5063 | input stg2_mio_clk_stop_in_c2t ; |
| 5064 | input stg2_mcu0_clk_stop_in_c2t; |
| 5065 | input stg2_mcu1_clk_stop_in_c2t; |
| 5066 | input stg2_mcu0_io_clk_stop_in_c2t; |
| 5067 | // input stg2_mcu0_dr_clk_stop_in_c2t; |
| 5068 | // input stg2_mcu1_dr_clk_stop_in_c2t; |
| 5069 | input stg2_mcu1_io_clk_stop_in_c2t; |
| 5070 | input stg1_mcu0_dr_clk_stop_in_c2b; |
| 5071 | input stg1_mcu1_dr_clk_stop_in_c2b; |
| 5072 | input stg2_mcu0_dr_clk_stop_in_c4t; |
| 5073 | input stg2_mcu1_dr_clk_stop_in_c4t; |
| 5074 | input stg2_io_out_in_c2b; |
| 5075 | |
| 5076 | output stg2_io_out_out_c1b; |
| 5077 | output stg2_mcu0_dr_clk_stop_out_c2b; |
| 5078 | output stg2_mcu1_dr_clk_stop_out_c2b; |
| 5079 | // output stg3_mcu0_dr_clk_stop_out_c2t; |
| 5080 | output stg3_mcu0_io_clk_stop_out_c2t; |
| 5081 | // output stg3_mcu1_dr_clk_stop_out_c2t; |
| 5082 | output stg3_mcu1_io_clk_stop_out_c2t; |
| 5083 | output stg3_mcu0_clk_stop_out_c2t; |
| 5084 | output stg3_mcu1_clk_stop_out_c2t; |
| 5085 | output stg3_io2x_sync_en_out_c2t; |
| 5086 | output stg3_mio_clk_stop_out_c2t ; |
| 5087 | output gclk_aligned ; |
| 5088 | output gl_ccu_clk_stop ; |
| 5089 | output gl_ccu_io_clk_stop ; |
| 5090 | output gl_ccx_clk_stop ; |
| 5091 | output gl_cmp_io_sync_en_c1b ; |
| 5092 | output gl_cmp_io_sync_en_c1m ; |
| 5093 | output gl_cmp_io_sync_en_c1t ; |
| 5094 | output gl_cmp_io_sync_en_c2b ; |
| 5095 | output gl_cmp_io_sync_en_c2t ; |
| 5096 | output gl_cmp_io_sync_en_c3b ; |
| 5097 | output gl_cmp_io_sync_en_c3t ; |
| 5098 | output gl_cmp_io_sync_en_c3t0 ; |
| 5099 | output gl_db0_clk_stop ; |
| 5100 | output gl_db1_clk_stop ; |
| 5101 | output gl_dmu_io_clk_stop ; |
| 5102 | output gl_dmu_peu_por_c3b ; |
| 5103 | output gl_dmu_peu_wmr_c3b ; |
| 5104 | output gl_dr_sync_en_c1m ; |
| 5105 | output gl_dr_sync_en_c3t ; |
| 5106 | output gl_efu_clk_stop ; |
| 5107 | output gl_efu_io_clk_stop ; |
| 5108 | output gl_io2x_out_c1b ; |
| 5109 | output gl_io2x_sync_en_c1m ; |
| 5110 | output gl_io2x_sync_en_c3t ; |
| 5111 | output gl_io2x_sync_en_c3t0 ; |
| 5112 | output gl_io2x_sync_en_c2t ; |
| 5113 | output gl_io_cmp_sync_en_c1b ; |
| 5114 | output gl_io_cmp_sync_en_c1m ; |
| 5115 | output gl_io_cmp_sync_en_c1t ; |
| 5116 | output gl_io_cmp_sync_en_c2b ; |
| 5117 | output gl_io_cmp_sync_en_c2t ; |
| 5118 | output gl_io_cmp_sync_en_c3b ; |
| 5119 | output gl_io_cmp_sync_en_c3t ; |
| 5120 | output gl_io_cmp_sync_en_c3t0 ; |
| 5121 | output gl_io_out_c1b ; |
| 5122 | output gl_io_out_c1m ; |
| 5123 | output gl_io_out_c3b ; |
| 5124 | output gl_io_out_c3b0 ; |
| 5125 | output gl_io_out_c3t ; |
| 5126 | output gl_l2_por_c1t ; |
| 5127 | output gl_l2_por_c1b ; // for int6.1 |
| 5128 | output gl_l2_por_c2b ; |
| 5129 | output gl_l2_por_c2t ; |
| 5130 | output gl_l2_por_c3b0 ; |
| 5131 | output gl_l2_por_c3t ; |
| 5132 | output gl_l2_por_c3t0 ; |
| 5133 | output gl_l2_wmr_c1b ; |
| 5134 | output gl_l2_wmr_c1t ; |
| 5135 | output gl_l2_wmr_c2b ; |
| 5136 | output gl_l2_wmr_c2t ; |
| 5137 | output gl_l2_wmr_c3b ; |
| 5138 | output gl_l2_wmr_c3t ; |
| 5139 | output gl_l2_wmr_c3t0 ; |
| 5140 | output gl_l2b0_clk_stop ; |
| 5141 | output gl_l2b1_clk_stop ; |
| 5142 | output gl_l2b2_clk_stop ; |
| 5143 | output gl_l2b3_clk_stop ; |
| 5144 | output gl_l2b4_clk_stop ; |
| 5145 | output gl_l2b5_clk_stop ; |
| 5146 | output gl_l2b6_clk_stop ; |
| 5147 | output gl_l2b7_clk_stop ; |
| 5148 | output gl_l2d0_clk_stop ; |
| 5149 | output gl_l2d1_clk_stop ; |
| 5150 | output gl_l2d2_clk_stop ; |
| 5151 | output gl_l2d3_clk_stop ; |
| 5152 | output gl_l2d4_clk_stop ; |
| 5153 | output gl_l2d5_clk_stop ; |
| 5154 | output gl_l2d7_clk_stop ; |
| 5155 | output gl_l2d6_clk_stop ; |
| 5156 | output gl_l2t0_clk_stop ; |
| 5157 | output gl_l2t1_clk_stop ; |
| 5158 | output gl_l2t2_clk_stop ; |
| 5159 | output gl_l2t3_clk_stop ; |
| 5160 | output gl_l2t4_clk_stop ; |
| 5161 | output gl_l2t5_clk_stop ; |
| 5162 | output gl_l2t6_clk_stop ; |
| 5163 | output gl_l2t7_clk_stop ; |
| 5164 | output gl_mac_io_clk_stop ; |
| 5165 | output gl_mcu1_dr_clk_stop ; |
| 5166 | output gl_mcu0_clk_stop ; |
| 5167 | output gl_mcu0_dr_clk_stop ; |
| 5168 | output gl_mcu0_io_clk_stop ; |
| 5169 | output gl_mcu1_clk_stop ; |
| 5170 | output gl_mcu1_io_clk_stop ; |
| 5171 | output gl_mcu2_clk_stop ; |
| 5172 | output gl_mcu2_dr_clk_stop ; |
| 5173 | output gl_mcu2_io_clk_stop ; |
| 5174 | output gl_mcu3_clk_stop ; |
| 5175 | output gl_mcu3_dr_clk_stop ; |
| 5176 | output gl_mcu3_io_clk_stop ; |
| 5177 | output gl_mio_clk_stop_c1t ; |
| 5178 | output gl_mio_clk_stop_c2t ; |
| 5179 | output gl_mio_clk_stop_c3t ; |
| 5180 | // output gl_mio_io2x_sync_en_c1b ; |
| 5181 | //output stg4_io2x_sync_en_c3t;//lijuan |
| 5182 | input stg4_io2x_sync_en_c3t;//lijuan |
| 5183 | output gl_mio_io2x_sync_en_c1t ; |
| 5184 | output gl_ncu_clk_stop ; |
| 5185 | output gl_ncu_io_clk_stop ; |
| 5186 | output gl_peu_io_clk_stop ; |
| 5187 | output gl_rdp_io_clk_stop ; |
| 5188 | output gl_rst_clk_stop ; |
| 5189 | output gl_rst_io_clk_stop ; |
| 5190 | output gl_rst_l2_por_c1m ; |
| 5191 | output gl_rst_l2_wmr_c1m ; |
| 5192 | output gl_rst_mac_c1b ; |
| 5193 | output gl_rst_niu_wmr_c1b ; |
| 5194 | output gl_tds_io_clk_stop ; |
| 5195 | output gl_rtx_io_clk_stop ; |
| 5196 | output gl_sii_clk_stop ; |
| 5197 | output gl_sii_io_clk_stop ; |
| 5198 | output gl_sio_clk_stop ; |
| 5199 | output gl_sio_io_clk_stop ; |
| 5200 | output gl_spc0_clk_stop ; |
| 5201 | output gl_spc1_clk_stop ; |
| 5202 | output gl_spc2_clk_stop ; |
| 5203 | output gl_spc3_clk_stop ; |
| 5204 | output gl_spc4_clk_stop ; |
| 5205 | output gl_spc5_clk_stop ; |
| 5206 | output gl_spc6_clk_stop ; |
| 5207 | output gl_spc7_clk_stop ; |
| 5208 | // output spare2_c1b ; |
| 5209 | // output spare3_c1b ; |
| 5210 | // output spare_c2b_s2_out6 ; |
| 5211 | output stg1_ccx_clk_stop_out_c1b ; |
| 5212 | output stg1_cmp_io_sync_en_out_c1b ; |
| 5213 | output stg1_cmp_io_sync_en_out_c1t ; |
| 5214 | output stg1_db0_clk_stop_out_c1b ; |
| 5215 | output stg1_dmu_io_clk_stop_out_c1b ; |
| 5216 | output stg1_dmu_peu_por_out_c1b ; |
| 5217 | output stg1_dmu_peu_wmr_out_c1b ; |
| 5218 | output stg1_dr_sync_en_out_c1t ; |
| 5219 | output stg1_io2x_out_out_c1b ; |
| 5220 | output stg1_io2x_sync_en_out_c1b ; |
| 5221 | output stg1_io2x_sync_en_out_c1t ; |
| 5222 | output stg1_io_cmp_sync_en_out_c1b ; |
| 5223 | output stg1_io_cmp_sync_en_out_c1t ; |
| 5224 | output stg1_io_out_out_c1b ; |
| 5225 | output stg1_io_out_out_c1t ; |
| 5226 | output stg1_l2b0_clk_stop_out_c1t ; |
| 5227 | output stg1_l2b1_clk_stop_out_c1t ; |
| 5228 | output stg1_l2b2_clk_stop_out_c1b ; |
| 5229 | output stg1_l2b3_clk_stop_out_c1b ; |
| 5230 | output stg1_l2b4_clk_stop_out_c1t ; |
| 5231 | output stg1_l2b5_clk_stop_out_c1t ; |
| 5232 | output stg1_l2d0_clk_stop_out_c1t ; |
| 5233 | output stg1_l2d1_clk_stop_out_c1t ; |
| 5234 | output stg1_l2d2_clk_stop_out_c1b ; |
| 5235 | output stg1_l2d3_clk_stop_out_c1b ; |
| 5236 | output stg1_l2d4_clk_stop_out_c1t ; |
| 5237 | output stg1_l2d5_clk_stop_out_c1t ; |
| 5238 | output stg1_l2d7_clk_stop_out_c1b ; |
| 5239 | output stg1_l2t0_clk_stop_out_c1t ; |
| 5240 | output stg1_l2t1_clk_stop_out_c1t ; |
| 5241 | output stg1_l2t2_clk_stop_out_c1b ; |
| 5242 | output stg1_l2t3_clk_stop_out_c1b ; |
| 5243 | output stg1_l2t5_clk_stop_out_c1t ; |
| 5244 | output stg1_l2t7_clk_stop_out_c1b ; |
| 5245 | output stg1_mac_io_clk_stop_out_c1b ; |
| 5246 | output stg1_mcu0_clk_stop_out_c1t ; |
| 5247 | output stg1_mcu0_dr_clk_stop_out_c1t ; |
| 5248 | output stg1_mcu0_io_clk_stop_out_c1t ; |
| 5249 | output stg1_mcu1_clk_stop_out_c1t ; |
| 5250 | output stg1_mcu1_dr_clk_stop_out_c1t ; |
| 5251 | output stg1_mcu1_io_clk_stop_out_c1t ; |
| 5252 | output stg1_mio_clk_stop_out_c1t ; |
| 5253 | output stg1_ncu_clk_stop_out_c1b ; |
| 5254 | output stg1_ncu_io_clk_stop_out_c1b ; |
| 5255 | output stg1_peu_io_clk_stop_out_c1b ; |
| 5256 | output stg1_rdp_io_clk_stop_out_c1b ; |
| 5257 | output stg1_rst_l2_por_out_c1b ; |
| 5258 | output stg1_rst_l2_por_out_c1t ; |
| 5259 | output stg1_rst_l2_wmr_out_c1b ; |
| 5260 | output stg1_rst_l2_wmr_out_c1t ; |
| 5261 | output stg1_rst_niu_mac_out_c1b ; |
| 5262 | output stg1_rst_niu_wmr_out_c1b ; |
| 5263 | output stg1_rtx_io_clk_stop_out_c1b ; |
| 5264 | output stg1_sii_clk_stop_out_c1b ; |
| 5265 | output stg1_sii_io_clk_stop_out_c1b ; |
| 5266 | output stg1_spc0_clk_stop_out_c1t ; |
| 5267 | output stg1_spc1_clk_stop_out_c1t ; |
| 5268 | output stg1_spc2_clk_stop_out_c1b ; |
| 5269 | output stg1_spc3_clk_stop_out_c1b ; |
| 5270 | output stg1_spc4_clk_stop_out_c1t ; |
| 5271 | output stg1_spc5_clk_stop_out_c1t ; |
| 5272 | output stg1_spc6_clk_stop_out_c1b ; |
| 5273 | output stg1_spc7_clk_stop_out_c1b ; |
| 5274 | output stg1_tds_io_clk_stop_out_c1b ; |
| 5275 | output stg2_ccx_clk_stop_out_c1b ; |
| 5276 | output stg2_cmp_io_sync_en_out_c1b ; |
| 5277 | output stg2_cmp_io_sync_en_out_c1t ; |
| 5278 | output stg2_db0_clk_stop_out_c1b ; |
| 5279 | output stg2_dmu_io_clk_stop_out_c1b ; |
| 5280 | output stg2_dmu_peu_por_out_c1b ; |
| 5281 | output stg2_dmu_peu_wmr_out_c1b ; |
| 5282 | output stg2_dr_sync_en_out_c1t ; |
| 5283 | output stg2_io_cmp_sync_en_out_c1b ; |
| 5284 | output stg2_io_cmp_sync_en_out_c1t ; |
| 5285 | output stg2_io_out_out_c1t ; |
| 5286 | output stg2_l2_por_out_c1b ; |
| 5287 | output stg2_l2_por_out_c1t ; |
| 5288 | output stg2_l2_wmr_out_c1b ; |
| 5289 | output stg2_l2_wmr_out_c1t ; |
| 5290 | output stg2_l2b0_clk_stop_out_c1t ; |
| 5291 | output stg2_l2b1_clk_stop_out_c1t ; |
| 5292 | output stg2_l2b2_clk_stop_out_c1b ; |
| 5293 | output stg2_l2b3_clk_stop_out_c1b ; |
| 5294 | output stg2_l2d0_clk_stop_out_c1t ; |
| 5295 | output stg2_l2d1_clk_stop_out_c1t ; |
| 5296 | output stg2_l2d2_clk_stop_out_c1b ; |
| 5297 | output stg2_l2d3_clk_stop_out_c1b ; |
| 5298 | output stg2_l2t0_clk_stop_out_c1t ; |
| 5299 | output stg2_l2t1_clk_stop_out_c1t ; |
| 5300 | output stg2_l2t2_clk_stop_out_c1b ; |
| 5301 | output stg2_l2t3_clk_stop_out_c1b ; |
| 5302 | output stg2_l2t5_clk_stop_out_c1t ; |
| 5303 | output stg2_l2t7_clk_stop_out_c1b ; |
| 5304 | output stg2_mcu0_clk_stop_out_c1t ; |
| 5305 | // output stg2_mcu0_dr_clk_stop_out_c1t ; |
| 5306 | output stg2_mcu0_io_clk_stop_out_c1t ; |
| 5307 | output stg2_mcu1_clk_stop_out_c1t ; |
| 5308 | // output stg2_mcu1_dr_clk_stop_out_c1t ; |
| 5309 | output stg2_mcu1_io_clk_stop_out_c1t ; |
| 5310 | output stg2_mio_clk_stop_out_c1t ; |
| 5311 | output stg2_mio_io2x_sync_en_out_c1t ; |
| 5312 | output stg2_ncu_clk_stop_out_c1b ; |
| 5313 | output stg2_ncu_io_clk_stop_out_c1b ; |
| 5314 | output stg2_peu_io_clk_stop_out_c1b ; |
| 5315 | output stg2_sii_clk_stop_out_c1b ; |
| 5316 | output stg2_sii_io_clk_stop_out_c1b ; |
| 5317 | output stg2_spc0_clk_stop_out_c1t ; |
| 5318 | output stg2_spc1_clk_stop_out_c1t ; |
| 5319 | output stg2_spc2_clk_stop_out_c1b ; |
| 5320 | output stg2_spc3_clk_stop_out_c1b ; |
| 5321 | output stg2_spc5_clk_stop_out_c1t ; |
| 5322 | output stg2_spc7_clk_stop_out_c1b ; |
| 5323 | output stg3_ccx_clk_stop_out_c2b ; |
| 5324 | output stg3_cmp_io_sync_en_out_c2b ; |
| 5325 | output stg3_cmp_io_sync_en_out_c2t ; |
| 5326 | output stg3_db0_clk_stop_out_c2b ; |
| 5327 | output stg3_dmu_io_clk_stop_out_c2b ; |
| 5328 | output stg3_dmu_peu_por_out_c2b ; |
| 5329 | output stg3_dmu_peu_wmr_out_c2b ; |
| 5330 | output stg3_dr_sync_en_out_c2t ; |
| 5331 | output stg3_io_cmp_sync_en_out_c2b ; |
| 5332 | output stg3_io_cmp_sync_en_out_c2t ; |
| 5333 | output stg3_io_out_out_c2t ; |
| 5334 | output stg3_l2_por_out_c2b ; |
| 5335 | output stg3_l2_por_out_c2t ; |
| 5336 | output stg3_l2_wmr_out_c2b ; |
| 5337 | output stg3_l2_wmr_out_c2t ; |
| 5338 | output stg3_l2b0_clk_stop_out_c2t ; |
| 5339 | output stg3_l2b1_clk_stop_out_c2t ; |
| 5340 | output stg3_l2b2_clk_stop_out_c2b ; |
| 5341 | output stg3_l2b3_clk_stop_out_c2b ; |
| 5342 | output stg3_l2d0_clk_stop_out_c2t ; |
| 5343 | output stg3_l2d1_clk_stop_out_c2t ; |
| 5344 | output stg3_l2d2_clk_stop_out_c2b ; |
| 5345 | output stg3_l2d3_clk_stop_out_c2b ; |
| 5346 | output stg3_l2t0_clk_stop_out_c2t ; |
| 5347 | output stg3_l2t1_clk_stop_out_c2t ; |
| 5348 | output stg3_l2t2_clk_stop_out_c2b ; |
| 5349 | output stg3_l2t3_clk_stop_out_c2b ; |
| 5350 | output stg3_l2t5_clk_stop_out_c2t ; |
| 5351 | output stg3_l2t7_clk_stop_out_c2b ; |
| 5352 | output stg3_mio_io2x_sync_en_out_c2t ; |
| 5353 | output stg3_ncu_clk_stop_out_c2b ; |
| 5354 | output stg3_ncu_io_clk_stop_out_c2b ; |
| 5355 | output stg3_io_out_out_c2b ; |
| 5356 | output stg3_peu_io_clk_stop_out_c2b ; |
| 5357 | output stg3_sii_clk_stop_out_c2b ; |
| 5358 | output stg3_sii_io_clk_stop_out_c2b ; |
| 5359 | output stg3_spc0_clk_stop_out_c2t ; |
| 5360 | output stg3_spc1_clk_stop_out_c2t ; |
| 5361 | output stg3_spc2_clk_stop_out_c2b ; |
| 5362 | output stg3_spc3_clk_stop_out_c2b ; |
| 5363 | output stg3_spc5_clk_stop_out_c2t ; |
| 5364 | output stg3_spc7_clk_stop_out_c2b ; |
| 5365 | output stg4_cmp_io_sync_en_out_c3b ; |
| 5366 | output stg4_cmp_io_sync_en_out_c3t ; |
| 5367 | output stg4_db0_clk_stop_out_c3b ; |
| 5368 | output stg4_dmu_io_clk_stop_out_c3b ; |
| 5369 | output stg4_dmu_peu_por_out_c3b ; |
| 5370 | output stg4_dmu_peu_wmr_out_c3b ; |
| 5371 | output stg4_dr_sync_en_out_c3t ; |
| 5372 | // output stg4_io2x_sync_en_out_c2b ; |
| 5373 | output stg4_io_cmp_sync_en_out_c3b ; |
| 5374 | output stg4_io_cmp_sync_en_out_c3t ; |
| 5375 | output stg4_io_out_out_c3b ; |
| 5376 | output stg4_io_out_out_c3t ; |
| 5377 | output stg4_l2_por_out_c3b ; |
| 5378 | output stg4_l2_por_out_c3t ; |
| 5379 | output stg4_l2_wmr_out_c3b ; |
| 5380 | output stg4_l2_wmr_out_c3t ; |
| 5381 | output stg4_l2b0_clk_stop_out_c3t ; |
| 5382 | output stg4_l2b1_clk_stop_out_c3t ; |
| 5383 | output stg4_l2b2_clk_stop_out_c3b ; |
| 5384 | output stg4_l2b3_clk_stop_out_c3b ; |
| 5385 | output stg4_l2d0_clk_stop_out_c3t ; |
| 5386 | output stg4_l2d1_clk_stop_out_c3t ; |
| 5387 | output stg4_l2d2_clk_stop_out_c3b ; |
| 5388 | output stg4_l2d3_clk_stop_out_c3b ; |
| 5389 | output stg4_l2t0_clk_stop_out_c3t ; |
| 5390 | output stg4_mcu0_clk_stop_out_c3t ; |
| 5391 | // output stg4_mcu0_dr_clk_stop_out_c3t ; |
| 5392 | output stg4_mcu0_io_clk_stop_out_c3t ; |
| 5393 | output stg4_mcu1_clk_stop_out_c3t ; |
| 5394 | // output stg4_mcu1_dr_clk_stop_out_c3t ; |
| 5395 | output stg4_mcu1_io_clk_stop_out_c3t ; |
| 5396 | output stg4_mio_clk_stop_out_c3t ; |
| 5397 | output stg4_mio_io2x_sync_en_out_c3t ; |
| 5398 | output stg4_ncu_clk_stop_out_c3b ; |
| 5399 | output stg4_ncu_io_clk_stop_out_c3b ; |
| 5400 | output stg4_peu_io_clk_stop_out_c3b ; |
| 5401 | output stg4_sii_clk_stop_out_c3b ; |
| 5402 | output stg4_sii_io_clk_stop_out_c3b ; |
| 5403 | output stg4_spc0_clk_stop_out_c3t ; |
| 5404 | // output stg4_spc1_clk_stop_out_c2b ; // for int6.1 |
| 5405 | output stg4_spc2_clk_stop_out_c3b ; |
| 5406 | // output stg4_spc5_clk_stop_out_c2b ; // for int6.1 |
| 5407 | output stg4_l2t2_clk_stop_out_c3b ; |
| 5408 | |
| 5409 | |
| 5410 | |
| 5411 | n2_clk_gl_cc_stg_c1t_s4_1 x2 ( |
| 5412 | .gl_l2d4_clk_stop (gl_l2d4_clk_stop ), |
| 5413 | .gclk_l2b4 (gclk_l2b4 ), |
| 5414 | .stg1_l2_por_in_c1t (stg1_l2_por_in_c1tg ), // for int6.1 (set 3) |
| 5415 | .stg1_l2d4_clk_stop_in_c1t (stg1_l2d4_clk_stop_in_c1t ), |
| 5416 | .gl_l2_por_c1t (gl_l2_por_c1t ), |
| 5417 | .stg1_l2b4_clk_stop_in_c1t (stg1_l2b4_clk_stop_in_c1t ), |
| 5418 | .stg1_spc4_clk_stop_in_c1t (stg1_spc4_clk_stop_in_c1t ), |
| 5419 | .gl_spc4_clk_stop (gl_spc4_clk_stop ), |
| 5420 | .gl_l2b4_clk_stop (gl_l2b4_clk_stop ) ); |
| 5421 | |
| 5422 | n2_clk_gl_cc_stg_c1t_s1_0 x3 ( |
| 5423 | .stg2_l2_por_out_c1t (stg2_l2_por_out_c1t ), |
| 5424 | .stg2_l2b1_clk_stop_out_c1t (stg2_l2b1_clk_stop_out_c1t ), |
| 5425 | .stg2_l2t0_clk_stop_out_c1t (stg2_l2t0_clk_stop_out_c1t ), |
| 5426 | .stg2_spc5_clk_stop_out_c1t (stg2_spc5_clk_stop_out_c1t ), |
| 5427 | .stg2_spc0_clk_stop_out_c1t (stg2_spc0_clk_stop_out_c1t ), |
| 5428 | .stg2_dr_sync_en_out_c1t (stg2_dr_sync_en_out_c1t ), |
| 5429 | .stg2_mio_io2x_sync_en_out_c1t (stg2_mio_io2x_sync_en_out_c1t ), |
| 5430 | .stg2_l2_wmr_out_c1t (stg2_l2_wmr_out_c1t ), |
| 5431 | .stg2_cmp_io_sync_en_out_c1t (stg2_cmp_io_sync_en_out_c1t ), |
| 5432 | .stg2_spc1_clk_stop_out_c1t (stg2_spc1_clk_stop_out_c1t ), |
| 5433 | .stg1_spc5_clk_stop_in_c1t (stg1_spc5_clk_stop_in_c1t ), |
| 5434 | .stg2_io_cmp_sync_en_out_c1t (stg2_io_cmp_sync_en_out_c1t ), |
| 5435 | .stg2_io_out_out_c1t (stg2_io_out_out_c1t ), |
| 5436 | .gclk_l2b5 (gclk_l2b5 ), |
| 5437 | .stg2_l2t1_clk_stop_out_c1t (stg2_l2t1_clk_stop_out_c1t ), |
| 5438 | .stg2_l2t5_clk_stop_out_c1t (stg2_l2t5_clk_stop_out_c1t ), |
| 5439 | .stg2_l2b0_clk_stop_out_c1t (stg2_l2b0_clk_stop_out_c1t ), |
| 5440 | .stg2_l2d1_clk_stop_out_c1t (stg2_l2d1_clk_stop_out_c1t ), |
| 5441 | .stg2_l2d0_clk_stop_out_c1t (stg2_l2d0_clk_stop_out_c1t ), |
| 5442 | .stg1_l2b1_clk_stop_in_c1t (stg1_l2b1_clk_stop_in_c1t ), |
| 5443 | .stg1_cmp_io_sync_en_in_c1t (stg1_cmp_io_sync_en_in_c1t ), |
| 5444 | .stg1_mio_io2x_sync_en_in_c1t (stg1_mio_io2x_sync_en_in_c1t ), |
| 5445 | .stg1_l2_wmr_in_c1t (stg1_l2_wmr_in_c1t ), |
| 5446 | .stg1_l2_por_in_c1t (stg1_l2_por_in_c1t ), |
| 5447 | .stg1_spc1_clk_stop_in_c1t (stg1_spc1_clk_stop_in_c1t ), |
| 5448 | .stg1_l2b0_clk_stop_in_c1t (stg1_l2b0_clk_stop_in_c1t ), |
| 5449 | .stg1_l2t5_clk_stop_in_c1t (stg1_l2t5_clk_stop_in_c1t ), |
| 5450 | .stg1_l2t1_clk_stop_in_c1t (stg1_l2t1_clk_stop_in_c1t ), |
| 5451 | .stg1_l2d1_clk_stop_in_c1t (stg1_l2d1_clk_stop_in_c1t ), |
| 5452 | .stg1_io_cmp_sync_en_in_c1t (stg1_io_cmp_sync_en_in_c1t ), |
| 5453 | .stg1_io_out_in_c1t (stg1_io_out_in_c1t ), |
| 5454 | .stg1_l2d0_clk_stop_in_c1t (stg1_l2d0_clk_stop_in_c1t ), |
| 5455 | .stg1_l2t0_clk_stop_in_c1t (stg1_l2t0_clk_stop_in_c1t ), |
| 5456 | .stg1_dr_sync_en_in_c1t (stg1_dr_sync_en_in_c1t ), |
| 5457 | .stg1_spc0_clk_stop_in_c1t (stg1_spc0_clk_stop_in_c1t ) ); |
| 5458 | |
| 5459 | n2_clk_gl_cc_stg_c1t_s1_1 x4 ( |
| 5460 | // .stg2_mcu1_dr_clk_stop_out_c1t (stg2_mcu1_dr_clk_stop_out_c1t ), |
| 5461 | // .stg1_mcu0_dr_clk_stop_in_c1t (stg1_mcu0_dr_clk_stop_in_c1t ), |
| 5462 | .stg1_mcu0_io_clk_stop_in_c1t (stg1_mcu0_io_clk_stop_in_c1t ), |
| 5463 | .stg1_mcu0_clk_stop_in_c1t (stg1_mcu0_clk_stop_in_c1t ), |
| 5464 | // .stg1_mcu1_dr_clk_stop_in_c1t (stg1_mcu1_dr_clk_stop_in_c1t ), |
| 5465 | .gclk_l2t4 (gclk_l2t4 ), |
| 5466 | .stg1_mcu1_clk_stop_in_c1t (stg1_mcu1_clk_stop_in_c1t ), |
| 5467 | .stg1_mcu1_io_clk_stop_in_c1t (stg1_mcu1_io_clk_stop_in_c1t ), |
| 5468 | // .stg2_mcu0_dr_clk_stop_out_c1t (stg2_mcu0_dr_clk_stop_out_c1t ), |
| 5469 | .stg1_mio_clk_stop_in_c1t (stg1_mio_clk_stop_in_c1t ), |
| 5470 | .stg2_mcu0_io_clk_stop_out_c1t (stg2_mcu0_io_clk_stop_out_c1t ), |
| 5471 | .stg2_mcu0_clk_stop_out_c1t (stg2_mcu0_clk_stop_out_c1t ), |
| 5472 | .stg2_mio_clk_stop_out_c1t (stg2_mio_clk_stop_out_c1t ), |
| 5473 | .stg2_mcu1_io_clk_stop_out_c1t (stg2_mcu1_io_clk_stop_out_c1t ), |
| 5474 | .stg2_mcu1_clk_stop_out_c1t (stg2_mcu1_clk_stop_out_c1t ) ); |
| 5475 | |
| 5476 | n2_clk_gl_cc_stage_rst_m0 x5 ( |
| 5477 | .stg1_rst_l2_por_out_c1b (stg1_rst_l2_por_out_c1b ), |
| 5478 | .stg1_dmu_peu_por_out_c1b (stg1_dmu_peu_por_out_c1b ), |
| 5479 | .gclk_in (gclk_rst ), |
| 5480 | .gl_rst_l2_por_c1m (gl_rst_l2_por_c1m ), |
| 5481 | .stg1_rst_l2_wmr_out_c1t (stg1_rst_l2_wmr_out_c1t ), |
| 5482 | .stg1_rst_l2_wmr_out_c1b (stg1_rst_l2_wmr_out_c1b ), |
| 5483 | .stg1_rst_niu_wmr_out_c1b (stg1_rst_niu_wmr_out_c1b ), |
| 5484 | .stg1_dmu_peu_wmr_out_c1b (stg1_dmu_peu_wmr_out_c1b ), |
| 5485 | .rst_niu_mac_ (rst_niu_mac_ ), |
| 5486 | .rst_l2_por_ (rst_l2_por_ ), |
| 5487 | .rst_l2_wmr_ (rst_l2_wmr_ ), |
| 5488 | .stg1_rst_niu_mac_out_c1b (stg1_rst_niu_mac_out_c1b ), |
| 5489 | .rst_dmu_peu_por_ (rst_dmu_peu_por_ ), |
| 5490 | .rst_dmu_peu_wmr_ (rst_dmu_peu_wmr_ ), |
| 5491 | .stg1_rst_l2_por_out_c1t (stg1_rst_l2_por_out_c1t ), |
| 5492 | .gl_rst_l2_wmr_c1m (gl_rst_l2_wmr_c1m ), |
| 5493 | .rst_niu_wmr_ (rst_niu_wmr_ ) ); |
| 5494 | |
| 5495 | n2_clk_gl_cc_stg_c1t_s4_0 x6 ( |
| 5496 | .gl_mio_io2x_sync_en_c1t (gl_mio_io2x_sync_en_c1t ), |
| 5497 | .gl_l2_wmr_c1t (gl_l2_wmr_c1t ), |
| 5498 | .stg1_io_cmp_sync_en_in_c1t (stg1_io_cmp_sync_en_in_c1tg ), // for int6.1 (set 3) |
| 5499 | .stg1_cmp_io_sync_en_in_c1t (stg1_cmp_io_sync_en_in_c1tg ), // for int6.1 (set 3) |
| 5500 | .stg1_mio_io2x_sync_en_in_c1t (stg1_mio_io2x_sync_en_in_c1tg), // for int6.1 (set 3) |
| 5501 | .stg1_l2_wmr_in_c1t (stg1_l2_wmr_in_c1tg ), // for int6.1 (set 3) |
| 5502 | .gl_io_cmp_sync_en_c1t (gl_io_cmp_sync_en_c1t ), |
| 5503 | .gclk_spc4 (gclk_spc4 ), |
| 5504 | .gl_cmp_io_sync_en_c1t (gl_cmp_io_sync_en_c1t ) ); |
| 5505 | |
| 5506 | n2_clk_gl_cc_stg_c1t_s4_2 x7 ( |
| 5507 | .gl_l2d5_clk_stop (gl_l2d5_clk_stop ), |
| 5508 | .gl_l2b5_clk_stop (gl_l2b5_clk_stop ), |
| 5509 | .stg1_l2d5_clk_stop_in_c1t (stg1_l2d5_clk_stop_in_c1t ), |
| 5510 | .stg1_mio_clk_stop_in_c1t (stg1_mio_clk_stop_in_c1tg ), // for int6.1 (set 3) |
| 5511 | .gl_mio_clk_stop_c1t (gl_mio_clk_stop_c1t ), |
| 5512 | .stg1_l2b5_clk_stop_in_c1t (stg1_l2b5_clk_stop_in_c1t ), |
| 5513 | .gclk_l2d5 (gclk_l2d5 ) ); |
| 5514 | |
| 5515 | n2_clk_gl_cc_stg_c1b_s1_1 x8 ( |
| 5516 | .gclk_spc6 (gclk_spc6s ), // for int6.1 (set 3) |
| 5517 | .stg2_ncu_io_clk_stop_out_c1b (stg2_ncu_io_clk_stop_out_c1b ), |
| 5518 | .stg2_ccx_clk_stop_out_c1b (stg2_ccx_clk_stop_out_c1b ), |
| 5519 | .stg1_ncu_clk_stop_in_c1b (stg1_ncu_clk_stop_in_c1b ), |
| 5520 | .stg1_sii_io_clk_stop_in_c1b (stg1_sii_io_clk_stop_in_c1b ), |
| 5521 | .stg1_ncu_io_clk_stop_in_c1b (stg1_ncu_io_clk_stop_in_c1b ), |
| 5522 | .stg1_sii_clk_stop_in_c1b (stg1_sii_clk_stop_in_c1b ), |
| 5523 | .stg1_ccx_clk_stop_in_c1b (stg1_ccx_clk_stop_in_c1b ), |
| 5524 | .stg1_dmu_io_clk_stop_in_c1b (stg1_dmu_io_clk_stop_in_c1b ), |
| 5525 | .stg2_peu_io_clk_stop_out_c1b (stg2_peu_io_clk_stop_out_c1b ), |
| 5526 | .stg2_sii_clk_stop_out_c1b (stg2_sii_clk_stop_out_c1b ), |
| 5527 | .stg2_ncu_clk_stop_out_c1b (stg2_ncu_clk_stop_out_c1b ), |
| 5528 | .stg2_l2t7_clk_stop_out_c1b (stg2_l2t7_clk_stop_out_c1b ), |
| 5529 | .stg2_dmu_io_clk_stop_out_c1b (stg2_dmu_io_clk_stop_out_c1b ), |
| 5530 | .stg1_peu_io_clk_stop_in_c1b (stg1_peu_io_clk_stop_in_c1b ), |
| 5531 | .stg1_l2t7_clk_stop_in_c1b (stg1_l2t7_clk_stop_in_c1b ), |
| 5532 | .stg2_sii_io_clk_stop_out_c1b (stg2_sii_io_clk_stop_out_c1b ) ); |
| 5533 | |
| 5534 | n2_clk_gl_cc_stg_c1b_s4_2 x9 ( |
| 5535 | .gl_rdp_io_clk_stop (gl_rdp_io_clk_stop ), |
| 5536 | .gl_rtx_io_clk_stop (gl_rtx_io_clk_stop ), |
| 5537 | .stg1_rdp_io_clk_stop_in_c1b (stg1_rdp_io_clk_stop_in_c1b ), |
| 5538 | .stg1_mac_io_clk_stop_in_c1b (stg1_mac_io_clk_stop_in_c1b ), |
| 5539 | .stg1_rtx_io_clk_stop_in_c1b (stg1_rtx_io_clk_stop_in_c1b ), |
| 5540 | .gl_mac_io_clk_stop (gl_mac_io_clk_stop ), |
| 5541 | .stg1_tds_io_clk_stop_in_c1b (stg1_tds_io_clk_stop_in_c1b ), |
| 5542 | .gclk_spc6 (gclk_spc6 ), |
| 5543 | .gl_tds_io_clk_stop (gl_tds_io_clk_stop ) ); |
| 5544 | |
| 5545 | n2_clk_gl_cc_stg_c1b_s4_1 x10 ( |
| 5546 | .gclk_l2d6 (gclk_l2d6 ), |
| 5547 | .gl_l2d7_clk_stop (gl_l2d7_clk_stop ), |
| 5548 | .stg1_spc6_clk_stop_in_c1b (stg1_spc6_clk_stop_in_c1b ), |
| 5549 | .gl_spc6_clk_stop (gl_spc6_clk_stop ), |
| 5550 | .stg1_l2d7_clk_stop_in_c1b (stg1_l2d7_clk_stop_in_c1b ) ); |
| 5551 | |
| 5552 | n2_clk_gl_cc_stg_c1b_s4_0 x11 ( |
| 5553 | .gl_l2_wmr_c1b (gl_l2_wmr_c1b ), |
| 5554 | .gclk_l2b6 (gclk_l2b6 ), |
| 5555 | .gl_io_cmp_sync_en_c1b (gl_io_cmp_sync_en_c1b ), |
| 5556 | .stg1_io_cmp_sync_en_in_c1b (stg1_io_cmp_sync_en_in_c1bg ), // for int6.1 (set 3) |
| 5557 | .stg1_l2_por_in_c1b (stg1_l2_por_in_c1bg ), // for int6.1 (set 3) |
| 5558 | .stg1_cmp_io_sync_en_in_c1b (stg1_cmp_io_sync_en_in_c1bg ), // for int6.1 (set 3) |
| 5559 | .gl_cmp_io_sync_en_c1b (gl_cmp_io_sync_en_c1b ), |
| 5560 | .gl_l2_por_c1b (gl_l2_por_c1b ), // for int6.1 |
| 5561 | .stg1_l2_wmr_in_c1b (stg1_l2_wmr_in_c1bg ) ); // for int6.1 (set 3) |
| 5562 | |
| 5563 | n2_clk_gl_cc_stg_c1b_s1_0 x12 ( |
| 5564 | .gclk_l2t6 (gclk_l2t6 ), |
| 5565 | .stg1_l2b2_clk_stop_in_c1b (stg1_l2b2_clk_stop_in_c1b ), |
| 5566 | .stg2_l2t2_clk_stop_out_c1b (stg2_l2t2_clk_stop_out_c1b ), |
| 5567 | .stg1_spc7_clk_stop_in_c1b (stg1_spc7_clk_stop_in_c1b ), |
| 5568 | .stg2_db0_clk_stop_out_c1b (stg2_db0_clk_stop_out_c1b ), |
| 5569 | .stg2_l2_por_out_c1b (stg2_l2_por_out_c1b ), |
| 5570 | .stg2_dmu_peu_wmr_out_c1b (stg2_dmu_peu_wmr_out_c1b ), |
| 5571 | .stg2_dmu_peu_por_out_c1b (stg2_dmu_peu_por_out_c1b ), |
| 5572 | .stg2_l2d3_clk_stop_out_c1b (stg2_l2d3_clk_stop_out_c1b ), |
| 5573 | .stg2_io_cmp_sync_en_out_c1b (stg2_io_cmp_sync_en_out_c1b ), |
| 5574 | .stg2_spc2_clk_stop_out_c1b (stg2_spc2_clk_stop_out_c1b ), |
| 5575 | .stg2_l2t3_clk_stop_out_c1b (stg2_l2t3_clk_stop_out_c1b ), |
| 5576 | .stg2_cmp_io_sync_en_out_c1b (stg2_cmp_io_sync_en_out_c1b ), |
| 5577 | .stg2_l2_wmr_out_c1b (stg2_l2_wmr_out_c1b ), |
| 5578 | .stg2_spc3_clk_stop_out_c1b (stg2_spc3_clk_stop_out_c1b ), |
| 5579 | .stg2_l2b2_clk_stop_out_c1b (stg2_l2b2_clk_stop_out_c1b ), |
| 5580 | .stg2_spc7_clk_stop_out_c1b (stg2_spc7_clk_stop_out_c1b ), |
| 5581 | .stg1_l2d3_clk_stop_in_c1b (stg1_l2d3_clk_stop_in_c1b ), |
| 5582 | .stg1_l2t3_clk_stop_in_c1b (stg1_l2t3_clk_stop_in_c1b ), |
| 5583 | .stg1_l2t2_clk_stop_in_c1b (stg1_l2t2_clk_stop_in_c1b ), |
| 5584 | .stg1_dmu_peu_wmr_in_c1b (stg1_dmu_peu_wmr_in_c1b ), |
| 5585 | .stg1_dmu_peu_por_in_c1b (stg1_dmu_peu_por_in_c1b ), |
| 5586 | .stg1_io_out_in_c1b (stg1_io_out_in_c1b ), |
| 5587 | .stg2_io_out_out_c1b (stg2_io_out_out_c1b), |
| 5588 | .stg1_l2b3_clk_stop_in_c1b (stg1_l2b3_clk_stop_in_c1b ), |
| 5589 | .stg1_db0_clk_stop_in_c1b (stg1_db0_clk_stop_in_c1b ), |
| 5590 | .stg1_l2_por_in_c1b (stg1_l2_por_in_c1b ), |
| 5591 | .stg1_l2_wmr_in_c1b (stg1_l2_wmr_in_c1b ), |
| 5592 | .stg1_cmp_io_sync_en_in_c1b (stg1_cmp_io_sync_en_in_c1b ), |
| 5593 | .stg2_l2d2_clk_stop_out_c1b (stg2_l2d2_clk_stop_out_c1b ), |
| 5594 | .stg1_l2d2_clk_stop_in_c1b (stg1_l2d2_clk_stop_in_c1b ), |
| 5595 | .stg1_io_cmp_sync_en_in_c1b (stg1_io_cmp_sync_en_in_c1b ), |
| 5596 | .stg1_spc2_clk_stop_in_c1b (stg1_spc2_clk_stop_in_c1b ), |
| 5597 | .stg2_l2b3_clk_stop_out_c1b (stg2_l2b3_clk_stop_out_c1b ), |
| 5598 | .stg1_spc3_clk_stop_in_c1b (stg1_spc3_clk_stop_in_c1b ) ); |
| 5599 | |
| 5600 | n2_clk_gl_cc_stg_c1b_s4_3 x13 ( |
| 5601 | .gl_io2x_out_c1b (gl_io2x_out_c1b ), |
| 5602 | .gl_io_out_c1b (gl_io_out_c1b ), |
| 5603 | .stg1_io_out_in_c1b (stg1_io_out_in_c1bg ), |
| 5604 | .stg1_rst_niu_wmr_in_c1b (stg1_rst_niu_wmr_in_c1b ), |
| 5605 | .stg1_rst_mac_in_c1b (stg1_rst_mac_in_c1b ), |
| 5606 | .stg1_io2x_out_in_c1b (stg1_io2x_out_in_c1b ), |
| 5607 | .gl_rst_mac_c1b (gl_rst_mac_c1b ), |
| 5608 | .gclk_mac (gclk_mac ), |
| 5609 | .gl_rst_niu_wmr_c1b (gl_rst_niu_wmr_c1b ) ); |
| 5610 | |
| 5611 | n2_clk_gl_cc_stg_c2b_s1_0 x14 ( |
| 5612 | .gclk_spc7 (gclk_spc7 ), |
| 5613 | .stg3_l2t2_clk_stop_out_c2b (stg3_l2t2_clk_stop_out_c2b ), |
| 5614 | .stg3_l2t3_clk_stop_out_c2b (stg3_l2t3_clk_stop_out_c2b ), |
| 5615 | .stg2_l2t3_clk_stop_in_c2bz (stg2_l2t3_clk_stop_in_c2bz ), |
| 5616 | .stg3_io_cmp_sync_en_out_c2b (stg3_io_cmp_sync_en_out_c2b ), |
| 5617 | .stg3_io_out_out_c2b (stg3_io_out_out_c2b ), |
| 5618 | .stg3_l2_wmr_out_c2b (stg3_l2_wmr_out_c2b ), |
| 5619 | .stg3_l2_por_out_c2b (stg3_l2_por_out_c2b ), |
| 5620 | .stg3_dmu_peu_por_out_c2b (stg3_dmu_peu_por_out_c2b ), |
| 5621 | .stg3_dmu_peu_wmr_out_c2b (stg3_dmu_peu_wmr_out_c2b ), |
| 5622 | .stg3_spc2_clk_stop_out_c2b (stg3_spc2_clk_stop_out_c2b ), |
| 5623 | .stg3_spc3_clk_stop_out_c2b (stg3_spc3_clk_stop_out_c2b ), |
| 5624 | .stg3_spc7_clk_stop_out_c2b (stg3_spc7_clk_stop_out_c2b ), |
| 5625 | .stg3_l2b2_clk_stop_out_c2b (stg3_l2b2_clk_stop_out_c2b ), |
| 5626 | .stg3_db0_clk_stop_out_c2b (stg3_db0_clk_stop_out_c2b ), |
| 5627 | .stg3_l2d2_clk_stop_out_c2b (stg3_l2d2_clk_stop_out_c2b ), |
| 5628 | .stg3_l2d3_clk_stop_out_c2b (stg3_l2d3_clk_stop_out_c2b ), |
| 5629 | .stg3_l2b3_clk_stop_out_c2b (stg3_l2b3_clk_stop_out_c2b ), |
| 5630 | .stg2_io_cmp_sync_en_in_c2b (stg2_io_cmp_sync_en_in_c2b ), |
| 5631 | .stg2_l2_wmr_in_c2b (stg2_l2_wmr_in_c2b ), |
| 5632 | .stg2_l2_por_in_c2b (stg2_l2_por_in_c2b ), |
| 5633 | .stg2_dmu_peu_por_in_c2b (stg2_dmu_peu_por_in_c2b ), |
| 5634 | .stg2_dmu_peu_wmr_in_c2b (stg2_dmu_peu_wmr_in_c2b ), |
| 5635 | .stg2_spc2_clk_stop_in_c2b (stg2_spc2_clk_stop_in_c2b ), |
| 5636 | .stg2_spc3_clk_stop_in_c2b (stg2_spc3_clk_stop_in_c2b ), |
| 5637 | .stg2_spc7_clk_stop_in_c2b (stg2_spc7_clk_stop_in_c2b ), |
| 5638 | .stg2_db0_clk_stop_in_c2b (stg2_db0_clk_stop_in_c2b ), |
| 5639 | .stg2_l2d2_clk_stop_in_c2b (stg2_l2d2_clk_stop_in_c2b ), |
| 5640 | .stg2_l2d3_clk_stop_in_c2b (stg2_l2d3_clk_stop_in_c2b ), |
| 5641 | .stg2_l2b2_clk_stop_in_c2b (stg2_l2b2_clk_stop_in_c2b ), |
| 5642 | .stg2_l2b3_clk_stop_in_c2b (stg2_l2b3_clk_stop_in_c2b ), |
| 5643 | .stg3_cmp_io_sync_en_out_c2b (stg3_cmp_io_sync_en_out_c2b ), |
| 5644 | .stg2_cmp_io_sync_en_in_c2b (stg2_cmp_io_sync_en_in_c2b ), |
| 5645 | .stg2_io_out_in_c2b (stg2_io_out_in_c2b ), |
| 5646 | .stg2_l2t2_clk_stop_in_c2b (stg2_l2t2_clk_stop_in_c2b ) ); |
| 5647 | |
| 5648 | n2_clk_gl_cc_stg_c2b_s1_1 x15 ( |
| 5649 | .stg2_sii_clk_stop_in_c2b (stg2_sii_clk_stop_in_c2b ), |
| 5650 | .gclk_l2t7 (gclk_l2t7 ), |
| 5651 | .stg2_ncu_clk_stop_in_c2b (stg2_ncu_clk_stop_in_c2b ), |
| 5652 | .stg3_l2t7_clk_stop_out_c2b (stg3_l2t7_clk_stop_out_c2b ), |
| 5653 | .stg3_ccx_clk_stop_out_c2b (stg3_ccx_clk_stop_out_c2b ), |
| 5654 | .stg3_sii_clk_stop_out_c2b (stg3_sii_clk_stop_out_c2b ), |
| 5655 | .stg3_ncu_clk_stop_out_c2b (stg3_ncu_clk_stop_out_c2b ), |
| 5656 | .stg3_sii_io_clk_stop_out_c2b (stg3_sii_io_clk_stop_out_c2b ), |
| 5657 | .stg3_ncu_io_clk_stop_out_c2b (stg3_ncu_io_clk_stop_out_c2b ), |
| 5658 | .stg3_dmu_io_clk_stop_out_c2b (stg3_dmu_io_clk_stop_out_c2b ), |
| 5659 | .stg3_peu_io_clk_stop_out_c2b (stg3_peu_io_clk_stop_out_c2b ), |
| 5660 | .stg2_peu_io_clk_stop_in_c2b (stg2_peu_io_clk_stop_in_c2b ), |
| 5661 | .stg2_sii_io_clk_stop_in_c2b (stg2_sii_io_clk_stop_in_c2b ), |
| 5662 | .stg2_ncu_io_clk_stop_in_c2b (stg2_ncu_io_clk_stop_in_c2b ), |
| 5663 | .stg2_dmu_io_clk_stop_in_c2b (stg2_dmu_io_clk_stop_in_c2b ), |
| 5664 | .stg2_l2t7_clk_stop_in_c2b (stg2_l2t7_clk_stop_in_c2b ), |
| 5665 | .stg2_ccx_clk_stop_in_c2b (stg2_ccx_clk_stop_in_c2b ) ); |
| 5666 | |
| 5667 | n2_clk_gl_cc_stg_c2b_s2_0 x16 ( |
| 5668 | .gclk_l2t3 (gclk_l2t3 ), |
| 5669 | // .spare_c2b_s2_out6 (spare_c2b_s2_out6 ), |
| 5670 | .gl_l2_wmr_c2b (gl_l2_wmr_c2b ), |
| 5671 | .stg3_ccx_clk_stop_in_c2b (stg3_ccx_clk_stop_in_c2b ), |
| 5672 | .stg3_l2t3_clk_stop_in_c2b (stg3_l2t3_clk_stop_in_c2b ), |
| 5673 | .stg3_l2_por_in_c2b (stg3_l2_por_in_c2b ), |
| 5674 | .stg3_l2_wmr_in_c2b (stg3_l2_wmr_in_c2b ), |
| 5675 | .stg3_io_cmp_sync_en_in_c2b (stg3_io_cmp_sync_en_in_c2b ), |
| 5676 | .stg3_cmp_io_sync_en_in_c2b (stg3_cmp_io_sync_en_in_c2b ), |
| 5677 | .stg3_l2t7_clk_stop_in_c2b (stg3_l2t7_clk_stop_in_c2b ), |
| 5678 | .gl_ccx_clk_stop (gl_ccx_clk_stop ), |
| 5679 | .gl_l2t3_clk_stop (gl_l2t3_clk_stop ), |
| 5680 | .gl_l2t7_clk_stop (gl_l2t7_clk_stop ), |
| 5681 | .gl_l2_por_c2b (gl_l2_por_c2b ), |
| 5682 | // .spare_c2b_s2_in6 (1'b0 ), |
| 5683 | .gl_cmp_io_sync_en_c2b (gl_cmp_io_sync_en_c2b ), |
| 5684 | .gl_io_cmp_sync_en_c2b (gl_io_cmp_sync_en_c2b ) ); |
| 5685 | |
| 5686 | n2_clk_gl_cc_stg_c2b_s2_1 x17 ( |
| 5687 | .gclk_spc3 (gclk_spc3 ), |
| 5688 | .gl_spc3_clk_stop (gl_spc3_clk_stop ), |
| 5689 | .gl_spc7_clk_stop (gl_spc7_clk_stop ), |
| 5690 | .stg3_spc7_clk_stop_in_c2b (stg3_spc7_clk_stop_in_c2b ), |
| 5691 | .stg3_spc3_clk_stop_in_c2b (stg3_spc3_clk_stop_in_c2b ) ); |
| 5692 | |
| 5693 | n2_clk_gl_cc_stg_c2t_s1_1 x18 ( |
| 5694 | .stg2_io2x_sync_en_in_c2t (stg2_io2x_sync_en_in_c2t ), |
| 5695 | // .stg3_spc5_clk_stop_in_c2b (stg3_spc5_clk_stop_in_c2b ), |
| 5696 | .stg2_mio_clk_stop_in_c2t (stg2_mio_clk_stop_in_c2t ), |
| 5697 | .stg3_mio_clk_stop_out_c2t (stg3_mio_clk_stop_out_c2t ), |
| 5698 | .stg3_io2x_sync_en_out_c2t (stg3_io2x_sync_en_out_c2t ), |
| 5699 | // .stg4_spc1_clk_stop_out_c2b (stg4_spc1_clk_stop_out_c2b ), |
| 5700 | // .stg4_spc5_clk_stop_out_c2b (stg4_spc5_clk_stop_out_c2b ), |
| 5701 | .gclk_l2t5 (gclk_l2t5 ), |
| 5702 | .stg2_mcu0_clk_stop_in_c2t ( stg2_mcu0_clk_stop_in_c2t ), |
| 5703 | .stg2_mcu1_clk_stop_in_c2t ( stg2_mcu1_clk_stop_in_c2t ), |
| 5704 | .stg3_mcu0_clk_stop_out_c2t ( stg3_mcu0_clk_stop_out_c2t ), |
| 5705 | .stg3_mcu1_clk_stop_out_c2t ( stg3_mcu1_clk_stop_out_c2t ), |
| 5706 | |
| 5707 | .stg2_mcu0_io_clk_stop_in_c2t ( stg2_mcu0_io_clk_stop_in_c2t ), |
| 5708 | // .stg2_mcu0_dr_clk_stop_in_c2t ( stg2_mcu0_dr_clk_stop_in_c2t ), |
| 5709 | // .stg2_mcu1_dr_clk_stop_in_c2t ( stg2_mcu1_dr_clk_stop_in_c2t ), |
| 5710 | .stg2_mcu1_io_clk_stop_in_c2t ( stg2_mcu1_io_clk_stop_in_c2t ), |
| 5711 | // .stg3_mcu0_dr_clk_stop_out_c2t ( stg3_mcu0_dr_clk_stop_out_c2t ), |
| 5712 | .stg3_mcu0_io_clk_stop_out_c2t ( stg3_mcu0_io_clk_stop_out_c2t ), |
| 5713 | // .stg3_mcu1_dr_clk_stop_out_c2t ( stg3_mcu1_dr_clk_stop_out_c2t ), |
| 5714 | .stg3_mcu1_io_clk_stop_out_c2t ( stg3_mcu1_io_clk_stop_out_c2t ) ); |
| 5715 | // .stg3_spc1_clk_stop_in_c2b (stg3_spc1_clk_stop_in_c2b ) ); |
| 5716 | |
| 5717 | n2_clk_gl_cc_stg_c2t_s1_0 x19 ( |
| 5718 | .gclk_spc5 (gclk_spc5 ), |
| 5719 | .stg3_l2t5_clk_stop_out_c2t (stg3_l2t5_clk_stop_out_c2t ), |
| 5720 | .stg3_l2t1_clk_stop_out_c2t (stg3_l2t1_clk_stop_out_c2t ), |
| 5721 | .stg3_l2t0_clk_stop_out_c2t (stg3_l2t0_clk_stop_out_c2t ), |
| 5722 | .stg3_l2b1_clk_stop_out_c2t (stg3_l2b1_clk_stop_out_c2t ), |
| 5723 | .stg3_l2b0_clk_stop_out_c2t (stg3_l2b0_clk_stop_out_c2t ), |
| 5724 | .stg3_l2d1_clk_stop_out_c2t (stg3_l2d1_clk_stop_out_c2t ), |
| 5725 | .stg3_l2d0_clk_stop_out_c2t (stg3_l2d0_clk_stop_out_c2t ), |
| 5726 | .stg3_spc5_clk_stop_out_c2t (stg3_spc5_clk_stop_out_c2t ), |
| 5727 | .stg3_spc1_clk_stop_out_c2t (stg3_spc1_clk_stop_out_c2t ), |
| 5728 | .stg3_spc0_clk_stop_out_c2t (stg3_spc0_clk_stop_out_c2t ), |
| 5729 | .stg3_l2_por_out_c2t (stg3_l2_por_out_c2t ), |
| 5730 | .stg3_io_out_out_c2t (stg3_io_out_out_c2t ), |
| 5731 | .stg3_dr_sync_en_out_c2t (stg3_dr_sync_en_out_c2t ), |
| 5732 | .stg3_mio_io2x_sync_en_out_c2t (stg3_mio_io2x_sync_en_out_c2t ), |
| 5733 | .stg3_io_cmp_sync_en_out_c2t (stg3_io_cmp_sync_en_out_c2t ), |
| 5734 | .stg3_cmp_io_sync_en_out_c2t (stg3_cmp_io_sync_en_out_c2t ), |
| 5735 | .stg2_cmp_io_sync_en_in_c2t (stg2_cmp_io_sync_en_in_c2t ), |
| 5736 | .stg2_io_cmp_sync_en_in_c2t (stg2_io_cmp_sync_en_in_c2t ), |
| 5737 | .stg2_mio_io2x_sync_en_in_c2t (stg2_mio_io2x_sync_en_in_c2t ), |
| 5738 | .stg2_dr_sync_en_in_c2t (stg2_dr_sync_en_in_c2t ), |
| 5739 | .stg2_io_out_in_c2t (stg2_io_out_in_c2t ), |
| 5740 | .stg3_l2_wmr_out_c2t (stg3_l2_wmr_out_c2t ), |
| 5741 | .stg2_l2_wmr_in_c2t (stg2_l2_wmr_in_c2t ), |
| 5742 | .stg2_l2_por_in_c2t (stg2_l2_por_in_c2t ), |
| 5743 | .stg2_spc0_clk_stop_in_c2t (stg2_spc0_clk_stop_in_c2t ), |
| 5744 | .stg2_spc1_clk_stop_in_c2t (stg2_spc1_clk_stop_in_c2t ), |
| 5745 | .stg2_spc5_clk_stop_in_c2t (stg2_spc5_clk_stop_in_c2t ), |
| 5746 | .stg2_l2d0_clk_stop_in_c2t (stg2_l2d0_clk_stop_in_c2t ), |
| 5747 | .stg2_l2d1_clk_stop_in_c2t (stg2_l2d1_clk_stop_in_c2t ), |
| 5748 | .stg2_l2b0_clk_stop_in_c2t (stg2_l2b0_clk_stop_in_c2t ), |
| 5749 | .stg2_l2b1_clk_stop_in_c2t (stg2_l2b1_clk_stop_in_c2t ), |
| 5750 | .stg2_l2t0_clk_stop_in_c2t (stg2_l2t0_clk_stop_in_c2t ), |
| 5751 | .stg2_l2t5_clk_stop_in_c2t (stg2_l2t5_clk_stop_in_c2t ), |
| 5752 | .stg2_l2t1_clk_stop_in_c2t (stg2_l2t1_clk_stop_in_c2t ) ); |
| 5753 | |
| 5754 | n2_clk_gl_cc_stg_c2t_s2_1 x20 ( |
| 5755 | .gclk_spc1 (gclk_spc1 ), |
| 5756 | .stg3_spc1_clk_stop_in_c2t (stg3_spc1_clk_stop_in_c2t ), |
| 5757 | .stg3_mio_clk_stop_in_c2t (stg3_mio_clk_stop_in_c2t ), |
| 5758 | .gl_mio_clk_stop_c2t (gl_mio_clk_stop_c2t ), |
| 5759 | .gl_spc5_clk_stop (gl_spc5_clk_stop ), |
| 5760 | .gl_io2x_sync_en_c2t (gl_io2x_sync_en_c2t ), |
| 5761 | .gl_spc1_clk_stop (gl_spc1_clk_stop ), |
| 5762 | .stg3_io2x_sync_en_in_c2t (stg3_io2x_sync_en_in_c2t ), |
| 5763 | .stg3_spc5_clk_stop_in_c2t (stg3_spc5_clk_stop_in_c2t ) ); |
| 5764 | |
| 5765 | n2_clk_gl_cc_stg_c2t_s2_0 x21 ( |
| 5766 | .stg3_l2t5_clk_stop_in_c2t (stg3_l2t5_clk_stop_in_c2t ), |
| 5767 | .gl_l2_por_c2t (gl_l2_por_c2t ), |
| 5768 | .stg3_io_cmp_sync_en_in_c2t (stg3_io_cmp_sync_en_in_c2t ), |
| 5769 | .stg3_l2_wmr_in_c2t (stg3_l2_wmr_in_c2t ), |
| 5770 | .stg3_l2_por_in_c2t (stg3_l2_por_in_c2t ), |
| 5771 | .stg3_l2t1_clk_stop_in_c2t (stg3_l2t1_clk_stop_in_c2t ), |
| 5772 | .stg3_cmp_io_sync_en_in_c2t (stg3_cmp_io_sync_en_in_c2t ), |
| 5773 | .gclk_l2t1 (gclk_l2t1 ), |
| 5774 | .gl_l2_wmr_c2t (gl_l2_wmr_c2t ), |
| 5775 | .gl_cmp_io_sync_en_c2t (gl_cmp_io_sync_en_c2t ), |
| 5776 | .gl_l2t5_clk_stop (gl_l2t5_clk_stop ), |
| 5777 | .gl_io_cmp_sync_en_c2t (gl_io_cmp_sync_en_c2t ), |
| 5778 | .gl_l2t1_clk_stop (gl_l2t1_clk_stop ) ); |
| 5779 | |
| 5780 | n2_clk_gl_cc_stg_c3t_s1_0 x22 ( |
| 5781 | .stg3_cmp_io_sync_en_in_c3t (stg3_cmp_io_sync_en_in_c3t ), |
| 5782 | .stg4_mio_io2x_sync_en_out_c3t (stg4_mio_io2x_sync_en_out_c3t ), |
| 5783 | .stg4_io_out_out_c3t (stg4_io_out_out_c3t ), |
| 5784 | .stg4_l2_wmr_out_c3t (stg4_l2_wmr_out_c3t ), |
| 5785 | .stg4_l2_por_out_c3t (stg4_l2_por_out_c3t ), |
| 5786 | .stg4_spc0_clk_stop_out_c3t (stg4_spc0_clk_stop_out_c3t ), |
| 5787 | .stg4_l2d0_clk_stop_out_c3t (stg4_l2d0_clk_stop_out_c3t ), |
| 5788 | .stg4_l2d1_clk_stop_out_c3t (stg4_l2d1_clk_stop_out_c3t ), |
| 5789 | .stg4_l2b0_clk_stop_out_c3t (stg4_l2b0_clk_stop_out_c3t ), |
| 5790 | .stg4_l2b1_clk_stop_out_c3t (stg4_l2b1_clk_stop_out_c3t ), |
| 5791 | .stg4_l2t0_clk_stop_out_c3t (stg4_l2t0_clk_stop_out_c3t ), |
| 5792 | .stg3_mio_io2x_sync_en_in_c3t (stg3_mio_io2x_sync_en_in_c3t ), |
| 5793 | .stg3_dr_sync_en_in_c3t (stg3_dr_sync_en_in_c3t ), |
| 5794 | .stg3_io_out_in_c3t (stg3_io_out_in_c3t ), |
| 5795 | .stg3_l2_wmr_in_c3t (stg3_l2_wmr_in_c3t ), |
| 5796 | .stg3_l2_por_in_c3t (stg3_l2_por_in_c3t ), |
| 5797 | .stg3_spc0_clk_stop_in_c3t (stg3_spc0_clk_stop_in_c3t ), |
| 5798 | .stg3_l2d0_clk_stop_in_c3t (stg3_l2d0_clk_stop_in_c3t ), |
| 5799 | .stg3_l2d1_clk_stop_in_c3t (stg3_l2d1_clk_stop_in_c3t ), |
| 5800 | .stg3_l2b0_clk_stop_in_c3t (stg3_l2b0_clk_stop_in_c3t ), |
| 5801 | .stg3_l2b1_clk_stop_in_c3t (stg3_l2b1_clk_stop_in_c3t ), |
| 5802 | .stg3_l2t0_clk_stop_in_c3t (stg3_l2t0_clk_stop_in_c3t ), |
| 5803 | .stg4_cmp_io_sync_en_out_c3t (stg4_cmp_io_sync_en_out_c3t ), |
| 5804 | .stg4_dr_sync_en_out_c3t (stg4_dr_sync_en_out_c3t ), |
| 5805 | .gclk_spc0 (gclk_spc0 ), |
| 5806 | .stg3_io_cmp_sync_en_in_c3t (stg3_io_cmp_sync_en_in_c3t ), |
| 5807 | .stg4_io_cmp_sync_en_out_c3t (stg4_io_cmp_sync_en_out_c3t ) ); |
| 5808 | |
| 5809 | n2_clk_gl_cc_stg_c3t_s1_1 x23 ( |
| 5810 | .gclk_l2t0 (gclk_l2t0 ), |
| 5811 | .stg3_mcu1_clk_stop_in_c3t (stg3_mcu1_clk_stop_in_c3t ), |
| 5812 | .stg3_mcu0_io_clk_stop_in_c3t (stg3_mcu0_io_clk_stop_in_c3t ), |
| 5813 | .stg3_mcu1_io_clk_stop_in_c3t (stg3_mcu1_io_clk_stop_in_c3t ), |
| 5814 | // .stg3_mcu0_dr_clk_stop_in_c3t (stg3_mcu0_dr_clk_stop_in_c3t ), |
| 5815 | // .stg3_mcu1_dr_clk_stop_in_c3t (stg3_mcu1_dr_clk_stop_in_c3t ), |
| 5816 | .stg3_mio_clk_stop_in_c3t (stg3_mio_clk_stop_in_c3t ), |
| 5817 | .stg4_mcu0_clk_stop_out_c3t (stg4_mcu0_clk_stop_out_c3t ), |
| 5818 | .stg4_mcu1_clk_stop_out_c3t (stg4_mcu1_clk_stop_out_c3t ), |
| 5819 | .stg4_mcu0_io_clk_stop_out_c3t (stg4_mcu0_io_clk_stop_out_c3t ), |
| 5820 | .stg4_mcu1_io_clk_stop_out_c3t (stg4_mcu1_io_clk_stop_out_c3t ), |
| 5821 | // .stg4_mcu0_dr_clk_stop_out_c3t (stg4_mcu0_dr_clk_stop_out_c3t ), |
| 5822 | // .stg4_mcu1_dr_clk_stop_out_c3t (stg4_mcu1_dr_clk_stop_out_c3t ), |
| 5823 | .stg4_mio_clk_stop_out_c3t (stg4_mio_clk_stop_out_c3t ), |
| 5824 | .stg3_mcu0_clk_stop_in_c3t (stg3_mcu0_clk_stop_in_c3t ) ); |
| 5825 | |
| 5826 | n2_clk_gl_cc_stg_c3t_s1_3 x24 ( |
| 5827 | .gclk_ncu (gclk_ncu ), |
| 5828 | .stg4_cmp_io_sync_en_in_c3t (stg4_cmp_io_sync_en_in_c3t ), |
| 5829 | .gl_io2x_sync_en_c3t (gl_io2x_sync_en_c3t ), |
| 5830 | .gl_io_out_c3t (gl_io_out_c3t ), |
| 5831 | .gl_l2_wmr_c3t (gl_l2_wmr_c3t ), |
| 5832 | .gl_l2_por_c3t (gl_l2_por_c3t ), |
| 5833 | .gl_l2t0_clk_stop (gl_l2t0_clk_stop ), |
| 5834 | .gl_mcu0_clk_stop (gl_mcu0_clk_stop ), |
| 5835 | .gl_mcu1_clk_stop (gl_mcu1_clk_stop ), |
| 5836 | // .gl_mcu0_dr_clk_stop (gl_mcu0_dr_clk_stop ), |
| 5837 | // .gl_mcu1_dr_clk_stop (gl_mcu1_dr_clk_stop ), |
| 5838 | .gl_mcu0_io_clk_stop (gl_mcu0_io_clk_stop ), |
| 5839 | .gl_mcu1_io_clk_stop (gl_mcu1_io_clk_stop ), |
| 5840 | .stg4_dr_sync_en_in_c3t (stg4_dr_sync_en_in_c3t ), |
| 5841 | .stg4_io_out_in_c3t (stg4_io_out_in_c3t ), |
| 5842 | .stg4_l2_wmr_in_c3t (stg4_l2_wmr_in_c3t ), |
| 5843 | .stg4_l2_por_in_c3t (stg4_l2_por_in_c3t ), |
| 5844 | .stg4_l2t0_clk_stop_in_c3t (stg4_l2t0_clk_stop_in_c3t ), |
| 5845 | .stg4_mcu0_clk_stop_in_c3t (stg4_mcu0_clk_stop_in_c3t ), |
| 5846 | .stg4_mcu1_clk_stop_in_c3t (stg4_mcu1_clk_stop_in_c3t ), |
| 5847 | // .stg4_mcu0_dr_clk_stop_in_c3t (stg4_mcu0_dr_clk_stop_in_c3t ), |
| 5848 | // .stg4_mcu1_dr_clk_stop_in_c3t (stg4_mcu1_dr_clk_stop_in_c3t ), |
| 5849 | .stg4_mcu0_io_clk_stop_in_c3t (stg4_mcu0_io_clk_stop_in_c3t ), |
| 5850 | .stg4_mcu1_io_clk_stop_in_c3t (stg4_mcu1_io_clk_stop_in_c3t ), |
| 5851 | .gl_cmp_io_sync_en_c3t (gl_cmp_io_sync_en_c3t ), |
| 5852 | .gl_dr_sync_en_c3t (gl_dr_sync_en_c3t ), |
| 5853 | .stg4_io_cmp_sync_en_in_c3t (stg4_io_cmp_sync_en_in_c3t ), |
| 5854 | .stg4_io2x_sync_en_in_c3t (stg4_io2x_sync_en_c3t ), |
| 5855 | .gl_io_cmp_sync_en_c3t (gl_io_cmp_sync_en_c3t ) ); |
| 5856 | |
| 5857 | n2_clk_gl_cc_stg_c3t_s1_2 x25 ( |
| 5858 | .gclk_l2b0 (gclk_l2b0 ), |
| 5859 | .gl_l2_por_c3t (gl_l2_por_c3t0 ), |
| 5860 | .gl_l2d1_clk_stop (gl_l2d1_clk_stop ), |
| 5861 | .gl_l2b0_clk_stop (gl_l2b0_clk_stop ), |
| 5862 | .gl_l2b1_clk_stop (gl_l2b1_clk_stop ), |
| 5863 | .gl_mio_clk_stop_c3t (gl_mio_clk_stop_c3t ), |
| 5864 | .stg4_spc0_clk_stop_in_c3t (stg4_spc0_clk_stop_in_c3t ), |
| 5865 | .stg4_cmp_io_sync_en_in_c3t (stg4_cmp_io_sync_en_in_c3t0 ), // for int6.1 (set 3) |
| 5866 | .stg4_io_cmp_sync_en_in_c3t (stg4_io_cmp_sync_en_in_c3t0 ), // for int6.1 (set 3) |
| 5867 | .stg4_l2_wmr_in_c3t (stg4_l2_wmr_in_c3t0 ),// for int6.1 (set 3) |
| 5868 | .stg4_l2_por_in_c3t (stg4_l2_por_in_c3t0 ),// for int6.1 (set 3) |
| 5869 | .stg4_l2d0_clk_stop_in_c3t (stg4_l2d0_clk_stop_in_c3t ), |
| 5870 | .stg4_l2d1_clk_stop_in_c3t (stg4_l2d1_clk_stop_in_c3t ), |
| 5871 | .stg4_l2b0_clk_stop_in_c3t (stg4_l2b0_clk_stop_in_c3t ), |
| 5872 | .stg4_l2b1_clk_stop_in_c3t (stg4_l2b1_clk_stop_in_c3t ), |
| 5873 | .stg4_mio_clk_stop_in_c3t (stg4_mio_clk_stop_in_c3t ), |
| 5874 | .gl_io2x_sync_en_c3t (gl_io2x_sync_en_c3t0 ), |
| 5875 | .gl_spc0_clk_stop (gl_spc0_clk_stop ), |
| 5876 | .gl_cmp_io_sync_en_c3t (gl_cmp_io_sync_en_c3t0 ), |
| 5877 | .gl_io_cmp_sync_en_c3t (gl_io_cmp_sync_en_c3t0 ), |
| 5878 | .gl_l2d0_clk_stop (gl_l2d0_clk_stop ), |
| 5879 | .stg4_io2x_sync_en_in_c3t (stg4_io2x_sync_en_in_c3t ), |
| 5880 | .gl_l2_wmr_c3t (gl_l2_wmr_c3t0 ) ); |
| 5881 | |
| 5882 | n2_clk_gl_cc_stg_c3b_s1_2 x26 ( |
| 5883 | .stg4_sii_io_clk_stop_in_c3b (stg4_sii_io_clk_stop_in_c3b ), |
| 5884 | .gl_io_out_c3b (gl_io_out_c3b0 ), |
| 5885 | .gl_l2_wmr_c3b (gl_l2_wmr_c3b ), |
| 5886 | .gl_l2_por_c3b (gl_l2_por_c3b0 ), |
| 5887 | .gl_l2d2_clk_stop (gl_l2d2_clk_stop ), |
| 5888 | .gl_l2d3_clk_stop (gl_l2d3_clk_stop ), |
| 5889 | .gl_l2b2_clk_stop (gl_l2b2_clk_stop ), |
| 5890 | .gl_l2b3_clk_stop (gl_l2b3_clk_stop ), |
| 5891 | .gl_l2t2_clk_stop (gl_l2t2_clk_stop ), |
| 5892 | .gl_sii_clk_stop (gl_sii_clk_stop ), |
| 5893 | .gl_ncu_clk_stop (gl_ncu_clk_stop ), |
| 5894 | .gl_sii_io_clk_stop (gl_sii_io_clk_stop ), |
| 5895 | .gl_ncu_io_clk_stop (gl_ncu_io_clk_stop ), |
| 5896 | .gclk_l2d2 (gclk_l2d2 ), |
| 5897 | .stg4_ncu_clk_stop_in_c3b (stg4_ncu_clk_stop_in_c3b ), |
| 5898 | .stg4_sii_clk_stop_in_c3b (stg4_sii_clk_stop_in_c3b ), |
| 5899 | .stg4_l2t2_clk_stop_in_c3b (stg4_l2t2_clk_stop_in_c3b ), |
| 5900 | .stg4_l2b3_clk_stop_in_c3b (stg4_l2b3_clk_stop_in_c3b ), |
| 5901 | .stg4_l2b2_clk_stop_in_c3b (stg4_l2b2_clk_stop_in_c3b ), |
| 5902 | .stg4_cmp_io_sync_en_in_c3b (stg4_cmp_io_sync_en_in_c3b ), |
| 5903 | .stg4_l2d3_clk_stop_in_c3b (stg4_l2d3_clk_stop_in_c3b ), |
| 5904 | .stg4_l2d2_clk_stop_in_c3b (stg4_l2d2_clk_stop_in_c3b ), |
| 5905 | .stg4_l2_por_in_c3b (stg4_l2_por_in_c3b ), |
| 5906 | .stg4_l2_wmr_in_c3b (stg4_l2_wmr_in_c3b ), |
| 5907 | .stg4_io_out_in_c3b (stg4_io_out_in_c3b0 ), // for int6.1 (set 3) |
| 5908 | .stg4_io_cmp_sync_en_in_c3b (stg4_io_cmp_sync_en_in_c3b ), |
| 5909 | .gl_io_cmp_sync_en_c3b (gl_io_cmp_sync_en_c3b ), |
| 5910 | .gl_cmp_io_sync_en_c3b (gl_cmp_io_sync_en_c3b ), |
| 5911 | .stg4_ncu_io_clk_stop_c3b (stg4_ncu_io_clk_stop_c3b ) ); |
| 5912 | |
| 5913 | n2_clk_gl_cc_stg_c3b_s1_3 x27 ( |
| 5914 | .gclk_dmu (gclk_dmu ), |
| 5915 | .stg4_dmu_peu_por_in_c3b (stg4_dmu_peu_por_in_c3b ), |
| 5916 | .stg4_dmu_peu_wmr_in_c3b (stg4_dmu_peu_wmr_in_c3b ), |
| 5917 | .stg4_spc2_clk_stop_in_c3b (stg4_spc2_clk_stop_in_c3b ), |
| 5918 | .stg4_db0_clk_stop_c3b (stg4_db0_clk_stop_c3b ), |
| 5919 | .stg4_dmu_io_clk_stop_in_c3b (stg4_dmu_io_clk_stop_in_c3b ), |
| 5920 | .stg4_peu_io_clk_stop_in_c3b (stg4_peu_io_clk_stop_in_c3b ), |
| 5921 | .gl_io_out_c3b (gl_io_out_c3b ), |
| 5922 | .gl_dmu_peu_por_c3b (gl_dmu_peu_por_c3b ), |
| 5923 | .gl_dmu_peu_wmr_c3b (gl_dmu_peu_wmr_c3b ), |
| 5924 | .gl_spc2_clk_stop (gl_spc2_clk_stop ), |
| 5925 | .gl_db0_clk_stop (gl_db0_clk_stop ), |
| 5926 | .gl_dmu_io_clk_stop (gl_dmu_io_clk_stop ), |
| 5927 | .gl_peu_io_clk_stop (gl_peu_io_clk_stop ), |
| 5928 | .stg4_io_out_in_c3b (stg4_io_out_in_c3b ) ); |
| 5929 | |
| 5930 | n2_clk_gl_cc_stg_c3b_s1_1 x28 ( |
| 5931 | .gclk_l2t2 (gclk_l2t2 ), |
| 5932 | .stg3_ncu_clk_stop_in_c3b (stg3_ncu_clk_stop_in_c3b ), |
| 5933 | .stg3_sii_io_clk_stop_in_c3b (stg3_sii_io_clk_stop_in_c3b ), |
| 5934 | .stg3_ncu_io_clk_stop_in_c3b (stg3_ncu_io_clk_stop_in_c3b ), |
| 5935 | .stg3_dmu_io_clk_stop_in_c3b (stg3_dmu_io_clk_stop_in_c3b ), |
| 5936 | .stg3_peu_io_clk_stop_in_c3b (stg3_peu_io_clk_stop_in_c3b ), |
| 5937 | .stg4_sii_clk_stop_out_c3b (stg4_sii_clk_stop_out_c3b ), |
| 5938 | .stg4_ncu_clk_stop_out_c3b (stg4_ncu_clk_stop_out_c3b ), |
| 5939 | .stg4_sii_io_clk_stop_out_c3b (stg4_sii_io_clk_stop_out_c3b ), |
| 5940 | .stg4_ncu_io_clk_stop_out_c3b (stg4_ncu_io_clk_stop_out_c3b ), |
| 5941 | .stg4_dmu_io_clk_stop_out_c3b (stg4_dmu_io_clk_stop_out_c3b ), |
| 5942 | .stg4_peu_io_clk_stop_out_c3b (stg4_peu_io_clk_stop_out_c3b ), |
| 5943 | .stg3_sii_clk_stop_in_c3b (stg3_sii_clk_stop_in_c3b ) ); |
| 5944 | |
| 5945 | n2_clk_gl_cc_stg_c3b_s1_0 x29 ( |
| 5946 | .stg4_l2t2_clk_stop_out_c3b ({stg4_l2t2_clk_stop_out_c3b } ), |
| 5947 | .stg3_l2t2_clk_stop_in_c3b ({stg3_l2t2_clk_stop_in_c3b } ), |
| 5948 | .stg4_io_out_out_c3b (stg4_io_out_out_c3b ), |
| 5949 | .stg4_l2_wmr_out_c3b (stg4_l2_wmr_out_c3b ), |
| 5950 | .stg4_l2_por_out_c3b (stg4_l2_por_out_c3b ), |
| 5951 | .stg4_dmu_peu_por_out_c3b (stg4_dmu_peu_por_out_c3b ), |
| 5952 | .stg4_dmu_peu_wmr_out_c3b (stg4_dmu_peu_wmr_out_c3b ), |
| 5953 | .stg4_spc2_clk_stop_out_c3b (stg4_spc2_clk_stop_out_c3b ), |
| 5954 | .stg4_db0_clk_stop_out_c3b (stg4_db0_clk_stop_out_c3b ), |
| 5955 | .stg4_l2d2_clk_stop_out_c3b (stg4_l2d2_clk_stop_out_c3b ), |
| 5956 | .stg4_l2d3_clk_stop_out_c3b (stg4_l2d3_clk_stop_out_c3b ), |
| 5957 | .stg4_l2b2_clk_stop_out_c3b (stg4_l2b2_clk_stop_out_c3b ), |
| 5958 | .stg4_l2b3_clk_stop_out_c3b (stg4_l2b3_clk_stop_out_c3b ), |
| 5959 | .stg3_cmp_io_sync_en_in_c3b (stg3_cmp_io_sync_en_in_c3b ), |
| 5960 | .stg3_io_cmp_sync_en_in_c3b (stg3_io_cmp_sync_en_in_c3b ), |
| 5961 | .stg3_io_out_in_c3b (stg3_io_out_in_c3b ), |
| 5962 | .stg3_l2_wmr_in_c3b (stg3_l2_wmr_in_c3b ), |
| 5963 | .stg3_l2_por_in_c3b (stg3_l2_por_in_c3b ), |
| 5964 | .stg3_dmu_peu_por_in_c3b (stg3_dmu_peu_por_in_c3b ), |
| 5965 | .stg3_dmu_peu_wmr_in_c3b (stg3_dmu_peu_wmr_in_c3b ), |
| 5966 | .stg3_spc2_clk_stop_in_c3b (stg3_spc2_clk_stop_in_c3b ), |
| 5967 | .stg3_db0_clk_stop_in_c3b (stg3_db0_clk_stop_in_c3b ), |
| 5968 | .stg3_l2d2_clk_stop_in_c3b (stg3_l2d2_clk_stop_in_c3b ), |
| 5969 | .stg3_l2d3_clk_stop_in_c3b (stg3_l2d3_clk_stop_in_c3b ), |
| 5970 | .stg3_l2b2_clk_stop_in_c3b (stg3_l2b2_clk_stop_in_c3b ), |
| 5971 | .stg3_l2b3_clk_stop_in_c3b (stg3_l2b3_clk_stop_in_c3b ), |
| 5972 | .stg4_io_cmp_sync_en_out_c3b (stg4_io_cmp_sync_en_out_c3b ), |
| 5973 | .gclk_spc2 (gclk_spc2 ), |
| 5974 | .stg4_cmp_io_sync_en_out_c3b (stg4_cmp_io_sync_en_out_c3b ) ); |
| 5975 | |
| 5976 | // n2_clk_gl_cc_stage_ccu_align xccu_align ( |
| 5977 | n2_clk_gl_cc_stage_align xccu_align ( |
| 5978 | .gclk_a (gclk_a ), |
| 5979 | .gclk_b (gclk_b ), |
| 5980 | .gclk_aligned (gclk_aligned ), |
| 5981 | .gclk_c (gclk_c ), |
| 5982 | .ccu_vco_aligned (ccu_vco_aligned ) ); |
| 5983 | |
| 5984 | |
| 5985 | n2_clk_gl_cc_stg_mcu_dr xstg_dr_1 ( // FOR INT6.1 |
| 5986 | .stg1_mcu1_dr_clk_stop_in (stg1_mcu0_dr_clk_stop_in_c2b ), |
| 5987 | .stg2_mcu1_dr_clk_stop_out (stg2_mcu0_dr_clk_stop_out_c2b ), |
| 5988 | .dr_gclk (dr_gclk_fsr7_stg ), |
| 5989 | .stg1_mcu0_dr_clk_stop_in (stg1_mcu1_dr_clk_stop_in_c2b ), |
| 5990 | .stg2_mcu0_dr_clk_stop_out (stg2_mcu1_dr_clk_stop_out_c2b )); |
| 5991 | |
| 5992 | n2_clk_gl_cc_stg_mcu_dr xstg_dr_2 ( // FOR INT6.1 |
| 5993 | .stg1_mcu1_dr_clk_stop_in (stg2_mcu0_dr_clk_stop_in_c4t ), |
| 5994 | .stg2_mcu1_dr_clk_stop_out (gl_mcu0_dr_clk_stop ), |
| 5995 | .dr_gclk ( dr_gclk_c4_mcu1 ), // (dr_gclk_mcu1 ), |
| 5996 | .stg1_mcu0_dr_clk_stop_in (stg2_mcu1_dr_clk_stop_in_c4t ), |
| 5997 | .stg2_mcu0_dr_clk_stop_out (gl_mcu1_dr_clk_stop )); |
| 5998 | |
| 5999 | |
| 6000 | n2_clk_gl_cc_stage_tcu_m0 x0 ( |
| 6001 | .stg1_peu_io_clk_stop_out_c1b (stg1_peu_io_clk_stop_out_c1b ), |
| 6002 | .gl_l2t4_clk_stop (gl_l2t4_clk_stop ), |
| 6003 | .tcu_mcu1_clk_stop (tcu_mcu1_clk_stop ), |
| 6004 | .gl_ccu_io_clk_stop (gl_ccu_io_clk_stop ), |
| 6005 | .gl_sio_clk_stop (gl_sio_clk_stop ), |
| 6006 | .gl_sio_io_clk_stop (gl_sio_io_clk_stop ), |
| 6007 | .gl_db1_clk_stop (gl_db1_clk_stop ), |
| 6008 | .gl_rst_clk_stop (gl_rst_clk_stop ), |
| 6009 | .gl_rst_io_clk_stop (gl_rst_io_clk_stop ), |
| 6010 | .gl_efu_clk_stop (gl_efu_clk_stop ), |
| 6011 | .stg1_l2t3_clk_stop_out_c1b (stg1_l2t3_clk_stop_out_c1b ), |
| 6012 | .tcu_l2t5_clk_stop (tcu_l2t5_clk_stop ), |
| 6013 | .tcu_l2t7_clk_stop (tcu_l2t7_clk_stop ), |
| 6014 | .stg1_ncu_clk_stop_out_c1b (stg1_ncu_clk_stop_out_c1b ), |
| 6015 | .gl_mcu2_dr_clk_stop (gl_mcu2_dr_clk_stop ), |
| 6016 | .stg1_l2t1_clk_stop_out_c1t (stg1_l2t1_clk_stop_out_c1t ), |
| 6017 | .tcu_spc1_clk_stop (tcu_spc1_clk_stop ), |
| 6018 | .tcu_sii_clk_stop (tcu_sii_clk_stop ), |
| 6019 | .tcu_ncu_io_clk_stop (tcu_ncu_io_clk_stop ), |
| 6020 | .tcu_sii_io_clk_stop (tcu_sii_io_clk_stop ), |
| 6021 | .tcu_ncu_clk_stop (tcu_ncu_clk_stop ), |
| 6022 | .tcu_db0_clk_stop (tcu_db0_clk_stop ), |
| 6023 | .gl_l2d6_clk_stop (gl_l2d6_clk_stop ), |
| 6024 | .gl_l2t6_clk_stop (gl_l2t6_clk_stop ), |
| 6025 | .stg1_l2t7_clk_stop_out_c1b (stg1_l2t7_clk_stop_out_c1b ), |
| 6026 | .stg1_sii_io_clk_stop_out_c1b (stg1_sii_io_clk_stop_out_c1b ), |
| 6027 | .stg1_l2d0_clk_stop_out_c1t (stg1_l2d0_clk_stop_out_c1t ), |
| 6028 | .stg1_ccx_clk_stop_out_c1b (stg1_ccx_clk_stop_out_c1b ), |
| 6029 | .stg1_rtx_io_clk_stop_out_c1b (stg1_rtx_io_clk_stop_out_c1b ), |
| 6030 | .gclk_in (gclk_tcu ), |
| 6031 | .dr_gclk_in ( dr_gclk_stg_tcu), |
| 6032 | .tcu_mcu2_io_clk_stop (tcu_mcu2_io_clk_stop ), |
| 6033 | .gl_efu_io_clk_stop (gl_efu_io_clk_stop ), |
| 6034 | .tcu_mcu0_clk_stop (tcu_mcu0_clk_stop ), |
| 6035 | .stg1_mio_clk_stop_out_c1t (stg1_mio_clk_stop_out_c1t ), |
| 6036 | .stg1_l2t2_clk_stop_out_c1b (stg1_l2t2_clk_stop_out_c1b ), |
| 6037 | .stg1_mcu1_clk_stop_out_c1t (stg1_mcu1_clk_stop_out_c1t ), |
| 6038 | .stg1_ncu_io_clk_stop_out_c1b (stg1_ncu_io_clk_stop_out_c1b ), |
| 6039 | .tcu_ccu_clk_stop (tcu_ccu_clk_stop ), |
| 6040 | .tcu_ccu_io_clk_stop (tcu_ccu_io_clk_stop ), |
| 6041 | .tcu_efu_io_clk_stop (tcu_efu_io_clk_stop ), |
| 6042 | .tcu_l2b6_clk_stop (tcu_l2b6_clk_stop ), |
| 6043 | .tcu_l2t6_clk_stop (tcu_l2t6_clk_stop ), |
| 6044 | .tcu_rst_clk_stop (tcu_rst_clk_stop ), |
| 6045 | .tcu_rst_io_clk_stop (tcu_rst_io_clk_stop ), |
| 6046 | .tcu_efu_clk_stop (tcu_efu_clk_stop ), |
| 6047 | .tcu_sio_clk_stop (tcu_sio_clk_stop ), |
| 6048 | .tcu_sio_io_clk_stop (tcu_sio_io_clk_stop ), |
| 6049 | .tcu_db1_clk_stop (tcu_db1_clk_stop ), |
| 6050 | .tcu_peu_io_clk_stop (tcu_peu_io_clk_stop ), |
| 6051 | .stg1_db0_clk_stop_out_c1b (stg1_db0_clk_stop_out_c1b ), |
| 6052 | .tcu_ccx_clk_stop (tcu_ccx_clk_stop ), |
| 6053 | .tcu_spc0_clk_stop (tcu_spc0_clk_stop ), |
| 6054 | .tcu_spc2_clk_stop (tcu_spc2_clk_stop ), |
| 6055 | .stg1_mcu1_dr_clk_stop_out_c1t (stg1_mcu1_dr_clk_stop_out_c1t ), |
| 6056 | .tcu_spc3_clk_stop (tcu_spc3_clk_stop ), |
| 6057 | .tcu_spc4_clk_stop (tcu_spc4_clk_stop ), |
| 6058 | .tcu_spc5_clk_stop (tcu_spc5_clk_stop ), |
| 6059 | .tcu_spc6_clk_stop (tcu_spc6_clk_stop ), |
| 6060 | .tcu_spc7_clk_stop (tcu_spc7_clk_stop ), |
| 6061 | .tcu_mcu2_clk_stop (tcu_mcu2_clk_stop ), |
| 6062 | .tcu_mcu3_io_clk_stop (tcu_mcu3_io_clk_stop ), |
| 6063 | .tcu_mcu3_dr_clk_stop (tcu_mcu3_dr_clk_stop ), |
| 6064 | .tcu_l2t0_clk_stop (tcu_l2t0_clk_stop ), |
| 6065 | .gl_mcu2_clk_stop (gl_mcu2_clk_stop ), |
| 6066 | .tcu_l2t3_clk_stop (tcu_l2t3_clk_stop ), |
| 6067 | .tcu_l2t2_clk_stop (tcu_l2t2_clk_stop ), |
| 6068 | .tcu_l2t1_clk_stop (tcu_l2t1_clk_stop ), |
| 6069 | .tcu_l2d0_clk_stop (tcu_l2d0_clk_stop ), |
| 6070 | .tcu_l2d1_clk_stop (tcu_l2d1_clk_stop ), |
| 6071 | .tcu_l2d2_clk_stop (tcu_l2d2_clk_stop ), |
| 6072 | .tcu_l2d3_clk_stop (tcu_l2d3_clk_stop ), |
| 6073 | .tcu_l2d4_clk_stop (tcu_l2d4_clk_stop ), |
| 6074 | .tcu_l2d5_clk_stop (tcu_l2d5_clk_stop ), |
| 6075 | .tcu_l2d7_clk_stop (tcu_l2d7_clk_stop ), |
| 6076 | .tcu_l2b0_clk_stop (tcu_l2b0_clk_stop ), |
| 6077 | .tcu_l2b1_clk_stop (tcu_l2b1_clk_stop ), |
| 6078 | .tcu_l2b2_clk_stop (tcu_l2b2_clk_stop ), |
| 6079 | .tcu_l2b3_clk_stop (tcu_l2b3_clk_stop ), |
| 6080 | .tcu_l2b4_clk_stop (tcu_l2b4_clk_stop ), |
| 6081 | .tcu_l2b5_clk_stop (tcu_l2b5_clk_stop ), |
| 6082 | .tcu_mcu0_io_clk_stop (tcu_mcu0_io_clk_stop ), |
| 6083 | .tcu_mcu1_io_clk_stop (tcu_mcu1_io_clk_stop ), |
| 6084 | .tcu_mcu0_dr_clk_stop (tcu_mcu0_dr_clk_stop ), |
| 6085 | .tcu_mcu1_dr_clk_stop (tcu_mcu1_dr_clk_stop ), |
| 6086 | .gl_ccu_clk_stop (gl_ccu_clk_stop ), |
| 6087 | .stg1_spc1_clk_stop_out_c1t (stg1_spc1_clk_stop_out_c1t ), |
| 6088 | .tcu_mac_io_clk_stop (tcu_mac_io_clk_stop ), |
| 6089 | .tcu_tds_io_clk_stop (tcu_tds_io_clk_stop ), |
| 6090 | .tcu_rtx_io_clk_stop (tcu_rtx_io_clk_stop ), |
| 6091 | .tcu_rdp_io_clk_stop (tcu_rdp_io_clk_stop ), |
| 6092 | .stg1_spc2_clk_stop_out_c1b (stg1_spc2_clk_stop_out_c1b ), |
| 6093 | .gl_l2b6_clk_stop (gl_l2b6_clk_stop ), |
| 6094 | .stg1_spc3_clk_stop_out_c1b (stg1_spc3_clk_stop_out_c1b ), |
| 6095 | .stg1_spc4_clk_stop_out_c1t (stg1_spc4_clk_stop_out_c1t ), |
| 6096 | .stg1_spc5_clk_stop_out_c1t (stg1_spc5_clk_stop_out_c1t ), |
| 6097 | .gl_l2b7_clk_stop (gl_l2b7_clk_stop ), |
| 6098 | .gl_mcu3_clk_stop (gl_mcu3_clk_stop ), |
| 6099 | .tcu_mcu3_clk_stop (tcu_mcu3_clk_stop ), |
| 6100 | .tcu_l2b7_clk_stop (tcu_l2b7_clk_stop ), |
| 6101 | .tcu_l2d6_clk_stop (tcu_l2d6_clk_stop ), |
| 6102 | .tcu_l2t4_clk_stop (tcu_l2t4_clk_stop ), |
| 6103 | .stg1_spc6_clk_stop_out_c1b (stg1_spc6_clk_stop_out_c1b ), |
| 6104 | .stg1_spc7_clk_stop_out_c1b (stg1_spc7_clk_stop_out_c1b ), |
| 6105 | .stg1_l2t0_clk_stop_out_c1t (stg1_l2t0_clk_stop_out_c1t ), |
| 6106 | .tcu_dmu_io_clk_stop (tcu_dmu_io_clk_stop ), |
| 6107 | .stg1_l2t5_clk_stop_out_c1t (stg1_l2t5_clk_stop_out_c1t ), |
| 6108 | .stg1_l2d1_clk_stop_out_c1t (stg1_l2d1_clk_stop_out_c1t ), |
| 6109 | .stg1_l2d2_clk_stop_out_c1b (stg1_l2d2_clk_stop_out_c1b ), |
| 6110 | .stg1_l2d3_clk_stop_out_c1b (stg1_l2d3_clk_stop_out_c1b ), |
| 6111 | .stg1_l2d4_clk_stop_out_c1t (stg1_l2d4_clk_stop_out_c1t ), |
| 6112 | .stg1_l2d5_clk_stop_out_c1t (stg1_l2d5_clk_stop_out_c1t ), |
| 6113 | .stg1_l2d7_clk_stop_out_c1b (stg1_l2d7_clk_stop_out_c1b ), |
| 6114 | .stg1_l2b0_clk_stop_out_c1t (stg1_l2b0_clk_stop_out_c1t ), |
| 6115 | .stg1_sii_clk_stop_out_c1b (stg1_sii_clk_stop_out_c1b ), |
| 6116 | .stg1_l2b1_clk_stop_out_c1t (stg1_l2b1_clk_stop_out_c1t ), |
| 6117 | .stg1_l2b2_clk_stop_out_c1b (stg1_l2b2_clk_stop_out_c1b ), |
| 6118 | .stg1_l2b3_clk_stop_out_c1b (stg1_l2b3_clk_stop_out_c1b ), |
| 6119 | .stg1_l2b4_clk_stop_out_c1t (stg1_l2b4_clk_stop_out_c1t ), |
| 6120 | .stg1_l2b5_clk_stop_out_c1t (stg1_l2b5_clk_stop_out_c1t ), |
| 6121 | .stg1_mcu0_clk_stop_out_c1t (stg1_mcu0_clk_stop_out_c1t ), |
| 6122 | .stg1_spc0_clk_stop_out_c1t (stg1_spc0_clk_stop_out_c1t ), |
| 6123 | .stg1_mcu1_io_clk_stop_out_c1t (stg1_mcu1_io_clk_stop_out_c1t ), |
| 6124 | .stg1_mcu0_dr_clk_stop_out_c1t (stg1_mcu0_dr_clk_stop_out_c1t ), |
| 6125 | .stg1_rdp_io_clk_stop_out_c1b (stg1_rdp_io_clk_stop_out_c1b ), |
| 6126 | .stg1_tds_io_clk_stop_out_c1b (stg1_tds_io_clk_stop_out_c1b ), |
| 6127 | .stg1_mac_io_clk_stop_out_c1b (stg1_mac_io_clk_stop_out_c1b ), |
| 6128 | .stg1_dmu_io_clk_stop_out_c1b (stg1_dmu_io_clk_stop_out_c1b ), |
| 6129 | .stg1_mcu0_io_clk_stop_out_c1t (stg1_mcu0_io_clk_stop_out_c1t ), |
| 6130 | .tcu_mio_clk_stop (tcu_mio_clk_stop ), |
| 6131 | .gl_mcu2_io_clk_stop (gl_mcu2_io_clk_stop ), |
| 6132 | .tcu_mcu2_dr_clk_stop (tcu_mcu2_dr_clk_stop ), |
| 6133 | .gl_mcu3_io_clk_stop (gl_mcu3_io_clk_stop ), |
| 6134 | .gl_mcu3_dr_clk_stop (gl_mcu3_dr_clk_stop ) ); |
| 6135 | |
| 6136 | // n2_clk_gl_cc_stage_ccu_m0 x1 ( |
| 6137 | n2_clk_gl_exp x1 ( |
| 6138 | .gclk_in (gclk_ccu ), |
| 6139 | .gl_cmp_io_sync_en_c1m (gl_cmp_io_sync_en_c1m ), |
| 6140 | .gl_io_out_c1m (gl_io_out_c1m ), |
| 6141 | .gl_io_cmp_sync_en_c1m (gl_io_cmp_sync_en_c1m ), |
| 6142 | .stg1_io2x_out_out_c1b (stg1_io2x_out_out_c1b ), |
| 6143 | .gl_io2x_sync_en_c1m (gl_io2x_sync_en_c1m ), |
| 6144 | .ccu_cmp_io_sync_en (ccu_cmp_io_sync_en ), |
| 6145 | .ccu_io_out (ccu_io_out ), |
| 6146 | .stg1_dr_sync_en_out_c1t (stg1_dr_sync_en_out_c1t ), |
| 6147 | .stg1_io2x_sync_en_out_c1b (stg1_io2x_sync_en_out_c1b ), |
| 6148 | .stg1_cmp_io_sync_en_out_c1t (stg1_cmp_io_sync_en_out_c1t ), |
| 6149 | .stg1_io_cmp_sync_en_out_c1t (stg1_io_cmp_sync_en_out_c1t ), |
| 6150 | .stg1_io2x_sync_en_out_c1t (stg1_io2x_sync_en_out_c1t ), |
| 6151 | .ccu_io2x_sync_en (ccu_io2x_sync_en ), |
| 6152 | .gl_dr_sync_en_c1m (gl_dr_sync_en_c1m ), |
| 6153 | .stg1_cmp_io_sync_en_out_c1b (stg1_cmp_io_sync_en_out_c1b ), |
| 6154 | .stg1_io_out_out_c1t (stg1_io_out_out_c1t ), |
| 6155 | .stg1_io_out_out_c1b (stg1_io_out_out_c1b ), |
| 6156 | .stg1_io_cmp_sync_en_out_c1b (stg1_io_cmp_sync_en_out_c1b ), |
| 6157 | .ccu_io_cmp_sync_en (ccu_io_cmp_sync_en ), |
| 6158 | .ccu_dr_sync_en (ccu_dr_sync_en ), |
| 6159 | .ccu_io2x_out (ccu_io2x_out ) ); |
| 6160 | |
| 6161 | |
| 6162 | // temporarily grounded |
| 6163 | //assign stg4_io2x_sync_en_c3t = 1'b0;//lijuan |
| 6164 | |
| 6165 | endmodule |
| 6166 | |