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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * Hypervisor Software File: cache.h | |
5 | * | |
6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
7 | * | |
8 | * - Do no alter or remove copyright notices | |
9 | * | |
10 | * - Redistribution and use of this software in source and binary forms, with | |
11 | * or without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistribution of source code must retain the above copyright notice, | |
15 | * this list of conditions and the following disclaimer. | |
16 | * | |
17 | * - Redistribution in binary form must reproduce the above copyright notice, | |
18 | * this list of conditions and the following disclaimer in the | |
19 | * documentation and/or other materials provided with the distribution. | |
20 | * | |
21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors | |
22 | * may be used to endorse or promote products derived from this software | |
23 | * without specific prior written permission. | |
24 | * | |
25 | * This software is provided "AS IS," without a warranty of any kind. | |
26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, | |
27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A | |
28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN | |
29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR | |
30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR | |
31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN | |
32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR | |
33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE | |
34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, | |
35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF | |
36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. | |
37 | * | |
38 | * You acknowledge that this software is not designed, licensed or | |
39 | * intended for use in the design, construction, operation or maintenance of | |
40 | * any nuclear facility. | |
41 | * | |
42 | * ========== Copyright Header End ============================================ | |
43 | */ | |
44 | /* | |
45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. | |
46 | * Use is subject to license terms. | |
47 | */ | |
48 | ||
49 | #ifndef _PLATFORM_CACHE_H | |
50 | #define _PLATFORM_CACHE_H | |
51 | ||
52 | #pragma ident "@(#)cache.h 1.1 07/05/03 SMI" | |
53 | ||
54 | #ifdef __cplusplus | |
55 | extern "C" { | |
56 | #endif | |
57 | ||
58 | /* | |
59 | * I/D/L2 Cache definitions | |
60 | */ | |
61 | ||
62 | /* | |
63 | * L2 cache index | |
64 | */ | |
65 | #define L2_BANK_SHIFT 6 | |
66 | #define L2_BANK_MASK (0x3) | |
67 | #define L2_SET_SHIFT 8 | |
68 | #define L2_SET_MASK (0x3FF) | |
69 | #define L2_WAY_SHIFT 18 | |
70 | #define L2_WAY_MASK (0xF) | |
71 | #define NO_L2_BANKS 4 | |
72 | ||
73 | #define L2_LINE_SHIFT 6 | |
74 | #define L2_LINE_SIZE (1 << L2_LINE_SHIFT) /* 64 */ | |
75 | #define N_LONG_IN_LINE (L2_LINE_SIZE / SIZEOF_UI64) | |
76 | #define L2_NUM_WAYS 12 | |
77 | ||
78 | #define L2_CSR_BASE (0xa0 << 32) | |
79 | ||
80 | /* | |
81 | * L2 Control Register definitions (Count 4 Step 64) | |
82 | */ | |
83 | #define L2_CONTROL_REG (0xa9 << 32) | |
84 | #define L2_DIS_SHIFT 0 | |
85 | #define L2_DIS (1 << L2_DIS_SHIFT) | |
86 | #define L2_DMMODE_SHIFT 1 | |
87 | #define L2_DMMODE (1 << L2_DMMODE_SHIFT) | |
88 | #define L2_SCRUBENABLE_SHIFT 2 | |
89 | #define L2_SCRUBENABLE (1 << L2_SCRUBENABLE_SHIFT) | |
90 | #define L2_SCRUBINTERVAL_SHIFT 3 | |
91 | #define L2_SCRUBINTERVAL_MASK (0xfff << L2_SCRUBENABLE_SHIFT) | |
92 | #define L2_ERRORSTEER_SHIFT 15 | |
93 | #define L2_ERRORSTEER_MASK (0x1f << L2_ERRORSTEER_SHIFT) | |
94 | #define L2_DBGEN_SHIFT 20 | |
95 | #define L2_DBGEN (1 << L2_DBGEN_SHIFT) | |
96 | #define L2_DIRCLEAR_SHIFT 21 | |
97 | #define L2_DIRCLEAR (1 << L2_DBGEN_SHIFT) | |
98 | ||
99 | /* | |
100 | * L2 Error Enable Register (Count 4 Step 64) | |
101 | */ | |
102 | #define L2_EEN_BA 0xaa | |
103 | #define L2_EEN_BASE (L2_EEN_BA << 32) | |
104 | #define L2_EEN_STEP 0x40 | |
105 | #define DEBUG_TRIG_EN (1 << 2) /* Debug Port Trigger enable */ | |
106 | ||
107 | /* BEGIN CSTYLED */ | |
108 | #define SET_L2_EEN_BASE(reg) \ | |
109 | mov L2_EEN_BA, reg;\ | |
110 | sllx reg, 32, reg | |
111 | #define GET_L2_BANK_EEN(bank, dst, scr1) \ | |
112 | SET_L2_EEN_BASE(scr1) /* Error Enable Register */ ;\ | |
113 | sllx bank, L2_BANK_SHIFT, dst /* bank offset */ ;\ | |
114 | ldx [scr1 + dst], dst /* get current */ | |
115 | #define BTST_L2_BANK_EEN(bank, bits, scr1, scr2) \ | |
116 | GET_L2_BANK_EEN(bank, scr1, scr2) /* get current */ ;\ | |
117 | btst bits, scr1 /* test bit(s) */ | |
118 | #define BCLR_L2_BANK_EEN(bank, bits, scr1, scr2) \ | |
119 | .pushlocals ;\ | |
120 | SET_L2_EEN_BASE(scr2) /* Error Enable Register */ ;\ | |
121 | sllx bank, L2_BANK_SHIFT, scr1 /* bank offset */ ;\ | |
122 | add scr2, scr1, scr2 /* bank address */ ;\ | |
123 | ldx [scr2], scr1 /* get current */ ;\ | |
124 | btst bits, scr1 /* reset? */ ;\ | |
125 | bz,pn %xcc, 9f /* yes: return cc=z */ ;\ | |
126 | bclr bits, scr1 /* reset bit(s) */ ;\ | |
127 | stx scr1, [scr2] /* store back */ ;\ | |
128 | 9: .poplocals /* success: cc=nz */ | |
129 | #define BSET_L2_BANK_EEN(bank, bits, scr1, scr2) \ | |
130 | SET_L2_EEN_BASE(scr2) /* Error Enable Register */ ;\ | |
131 | sllx bank, L2_BANK_SHIFT, scr1 /* bank offset */ ;\ | |
132 | add scr2, scr1, scr2 /* bank address */ ;\ | |
133 | ldx [scr2], scr1 /* get current */ ;\ | |
134 | bset bits, scr1 /* set bit(s) */ ;\ | |
135 | stx scr1, [scr2] /* store back */ | |
136 | /* END CSTYLED */ | |
137 | ||
138 | /* | |
139 | * L2 Error Status Register (Count 4 Step 64) | |
140 | */ | |
141 | #define L2_ESR_BA 0xab | |
142 | #define L2_ESR_BASE (L2_ESR_BA << 32) | |
143 | #define L2_ESR_STEP 0x40 | |
144 | #define L2_BANK_STEP 0x40 | |
145 | #define L2_ESR_MEU (1 << 63) | |
146 | #define L2_ESR_MEC (1 << 62) | |
147 | #define L2_ESR_RW (1 << 61) | |
148 | #define L2_ESR_MODA (1 << 59) | |
149 | #define L2_ESR_VCID_SHIFT 54 | |
150 | #define L2_ESR_VCID_MASK 0x1f | |
151 | #define L2_ESR_VCID (L2_ESR_VCID_MASK << L2_ESR_VCID_SHIFT) | |
152 | #define L2_ESR_LDAC (1 << 53) | |
153 | #define L2_ESR_LDAU (1 << 52) | |
154 | #define L2_ESR_LDWC (1 << 51) | |
155 | #define L2_ESR_LDWU (1 << 50) | |
156 | #define L2_ESR_LDRC (1 << 49) | |
157 | #define L2_ESR_LDRU (1 << 48) | |
158 | #define L2_ESR_LDSC (1 << 47) | |
159 | #define L2_ESR_LDSU (1 << 46) | |
160 | #define L2_ESR_LTC (1 << 45) | |
161 | #define L2_ESR_LRU (1 << 44) | |
162 | #define L2_ESR_LVU (1 << 43) | |
163 | #define L2_ESR_DAC (1 << 42) | |
164 | #define L2_ESR_DAU (1 << 41) | |
165 | #define L2_ESR_DRC (1 << 40) | |
166 | #define L2_ESR_DRU (1 << 39) | |
167 | #define L2_ESR_DSC (1 << 38) | |
168 | #define L2_ESR_DSU (1 << 37) | |
169 | #define L2_ESR_VEC (1 << 36) | |
170 | #define L2_ESR_VEU (1 << 35) | |
171 | #define L2_ESR_SYND_SHIFT 0 | |
172 | #define L2_ESR_SYND_MASK 0xffffffff | |
173 | #define L2_ESR_SYND (L2_ESR_SYND_MASK << L2_ESR_SYND_SHIFT) | |
174 | ||
175 | #define L2_ERROR_STATUS_CLEAR 0xc03ffff800000000 | |
176 | ||
177 | /* | |
178 | * L2 Error Address Register (Count 4 Step 64) | |
179 | */ | |
180 | #define L2_EAR_BA 0xac | |
181 | #define L2_EAR_BASE (L2_EAR_BA << 32) | |
182 | ||
183 | #ifdef __cplusplus | |
184 | } | |
185 | #endif | |
186 | ||
187 | #endif /* !_PLATFORM_CACHE_H */ |