[OpenSPARC-T2-SAM] / hypervisor / src / greatlakes / ontario / include / platform / mau.h

/*
* ========== Copyright Header Begin ==========================================
*
* Hypervisor Software File: mau.h
* 
* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
* 
*  - Do no alter or remove copyright notices
* 
*  - Redistribution and use of this software in source and binary forms, with 
*    or without modification, are permitted provided that the following 
*    conditions are met: 
* 
*  - Redistribution of source code must retain the above copyright notice, 
*    this list of conditions and the following disclaimer.
* 
*  - Redistribution in binary form must reproduce the above copyright notice,
*    this list of conditions and the following disclaimer in the
*    documentation and/or other materials provided with the distribution. 
* 
*    Neither the name of Sun Microsystems, Inc. or the names of contributors 
* may be used to endorse or promote products derived from this software 
* without specific prior written permission. 
* 
*     This software is provided "AS IS," without a warranty of any kind. 
* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* 
* You acknowledge that this software is not designed, licensed or
* intended for use in the design, construction, operation or maintenance of
* any nuclear facility. 
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
 * Use is subject to license terms.
 */

#ifndef _PLATFORM_MAU_H
#define	_PLATFORM_MAU_H

#pragma ident	"@(#)mau.h	1.2	07/07/27 SMI"

#ifdef __cplusplus
extern "C" {
#endif

#include <config.h>
#include <ncs.h>
#include <resource.h>


/*
 * MA Control Register
 *	Field	Bits	R/W
 *	-----	----	---
 *	STRAND	12:11	R/W
 *	BUSY	10	RO
 *	INTR	9	R/W
 *	OP	8:6	R/W
 *	LENGTH	5:0	R/W
 */
#define	MA_CTL_STRAND_SHIFT	11
#define	MA_CTL_BUSY_SHIFT	10
#define	MA_CTL_INTR_SHIFT	9
#define	MA_CTL_INTR_MASK	0x1
#define	MA_CTL_OP_SHIFT		6
#define	MA_CTL_OP_MASK		7
#define	MA_CTL_LENGTH_MASK	0x3f

#ifdef _ASM

/* BEGIN CSTYLED */

/* Range check and real to phys conversion macro */
#define	REAL_TO_PHYS(raddr, size, paddr, fail_label, gstruct, scr2)	\
	GUEST_STRUCT(gstruct)						;\
	RA2PA_RANGE_CHECK(gstruct, raddr, size, fail_label, scr2)	;\
	RA2PA_CONV(gstruct, raddr, paddr, scr2)

#define	REAL_TO_PHYS_G(raddr, size, paddr, fail_label, gstruct, scr2)	\
	RA2PA_RANGE_CHECK(gstruct, raddr, size, fail_label, scr2)	;\
	RA2PA_CONV(gstruct, raddr, paddr, scr2)

/*
 * MAU_LOAD preps and loads MAU registers.
 * If a Load or Store operation is being performed, then the
 * MA address is translated to a physical address.
 * Leaves an errno result in 'ret' if there is an
 * alignment issue with the MA address.
 *
 * membar #Sync prior to storing Control register
 * is due to NIAGARA_ERRATUM_41.
 */
#define	MAU_LOAD(nhd, tid, ret, intr, errlbl, chklbl, scr1, scr2, scr3)	\
	.pushlocals					; \
	ldx	[nhd + MR_CTL], scr1			; \
	srlx	scr1, MA_CTL_OP_SHIFT, scr2		; \
	and	scr2, MA_CTL_OP_MASK, scr2		; \
	cmp	scr2, MA_OP_LOAD			; \
	be	%xcc, 0f				; \
	cmp	scr2, MA_OP_STORE			; \
	bne,a	%xcc, 1f				; \
	  ldx	[nhd + MR_MPA], scr1			; \
0:							; \
	and	scr1, MA_CTL_LENGTH_MASK, scr1		; \
	inc	scr1					; \
	sllx	scr1, MA_WORDS2BYTES_SHIFT, scr2	; \
	ldx	[nhd + MR_MPA], scr1			; \
	btst	NCS_PTR_ALIGN - 1, scr1			; \
	bnz,a,pn %xcc, chklbl				; \
	  mov	EINVAL, ret				; \
	REAL_TO_PHYS(scr1, scr2, scr1, errlbl, scr3, ret)       ; \
1:							; \
	mov	ASI_MAU_MPA, scr2			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	ldx	[nhd + MR_MA], scr1			; \
	mov	ASI_MAU_ADDR, scr2			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	ldx	[nhd + MR_NP], scr1			; \
	mov	ASI_MAU_NP, scr2			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	ldx	[nhd + MR_CTL], scr1			; \
	sll	tid, MA_CTL_STRAND_SHIFT, scr2		; \
	or	scr1, scr2, scr1			; \
	mov	ASI_MAU_CONTROL, scr2			; \
	membar	#Sync					; \
	mov	MA_CTL_INTR_MASK, scr3			; \
	sllx	scr3, MA_CTL_INTR_SHIFT, scr3		; \
	andn	scr1, scr3, scr1			; \
	mov	intr, scr3				; \
	and	scr3, MA_CTL_INTR_MASK, scr3		; \
	sllx	scr3, MA_CTL_INTR_SHIFT, scr3		; \
	or	scr1, scr3, scr1			; \
	stxa	scr1, [scr2]ASI_STREAM			; \
	.poplocals

/*
 * In Niagara-2 we'll be able to check for
 * possible errors that occurred in the MAU,
 * however for Niagara-1 we really can't.
 * So, we assume success.
 */
#define	MAU_CHECK_ERR(ret, scr1, scr2)		\
	mov	%g0, ret


#define	MAU_HANDLE_SIG		0x0864
#define	HANDLE_SIGMASK		0xfff
#define	HANDLE_IDMASK		0xfff
#define	HANDLE_IDSHIFT		16
#define	HANDLE2ID(hdl, idx)			\
	srlx	hdl, HANDLE_IDSHIFT, idx	; \
	and	idx, HANDLE_IDMASK, idx
#define	ID2HANDLE(idx, sig, hdl)		\
	and	idx, HANDLE_IDMASK, hdl		; \
	sllx	hdl, HANDLE_IDSHIFT, hdl	; \
	or	hdl, sig, hdl
#define	HANDLE_IS_MAU(hdl, scr)			\
	and	hdl, HANDLE_SIGMASK, scr	; \
	cmp	scr, MAU_HANDLE_SIG
/*
 * MAU_HANDLE2ID_VERIFY
 *	Translates and verifies a MAU specific handle
 *	for a valid signature and ID.
 */
#define	MAU_HANDLE2ID_VERIFY(hdl, lbl, id)	\
	HANDLE_IS_MAU(hdl, id)			; \
	bne,pn	%xcc, lbl			; \
	nop					; \
	HANDLE2ID(hdl, id)			; \
	cmp	id, NMAUS			; \
	bgeu,pn	%xcc, lbl			; \
	nop

#define	MAU_CLEAR_QSTATE(mau)			\
	stx	%g0, [mau + MAU_QUEUE + MQ_LOCK]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_BASE_RA]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_BASE]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_END]		; \
	stx	%g0, [mau + MAU_QUEUE + MQ_HEAD]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_HEAD_MARKER]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_TAIL]	; \
	stx	%g0, [mau + MAU_QUEUE + MQ_NENTRIES]	; \
	st	%g0, [mau + MAU_QUEUE + MQ_BUSY]

#define	GUEST_MID_GETMAU(guest, id, mau)	\
	sllx	id, GUEST_MAUS_SHIFT, mau	; \
	add	mau, GUEST_MAUS, mau		; \
	ldx	[guest + mau], mau

#define	GUEST_MID_SETMAU(guest, id, mau, scr)	\
	sllx	id, GUEST_MAUS_SHIFT, scr	; \
	add	scr, GUEST_MAUS, scr		; \
	stx	mau, [guest + scr]

#define	MAU_LOCK_ENTER(mau, lck, scr1, scr2)	\
	add	mau, MAU_QUEUE, lck		; \
	add	lck, MQ_LOCK, lck		; \
	SPINLOCK_ENTER(lck, scr1, scr2)
#define	MAU_LOCK_EXIT(mau, lck)			\
	add	mau, MAU_QUEUE, lck		; \
	add	lck, MQ_LOCK, lck		; \
	SPINLOCK_EXIT(lck)
#define	MAU_LOCK_EXIT_L(lck)			\
	SPINLOCK_EXIT(lck)

/*
 *	We wait for the MAU to stop by doing a sync-load.
 *	If the MAU is currently busy running a job on behalf
 *	of the current strand (cpu) being stopped then the
 *	sync-load will wait for it to complete.  If the MAU
 *	is busy running a job for a different strand (cpu)
 *	then the sync-load will immediately return.  Since
 *	the job being executed is on behalf of a different
 *	cpu then the immediate return is okay since we only
 *	care about the local cpu being stopped.
 *
 *	Note that we have to enable interrupts while doing
 *	this load to ensure the MAU can complete the operation
 *	including possibly handling an interrupt.
 */
#define	CRYPTO_STOP(scr1, scr2)				\
	/*						;\
	 * Make sure interrupts are enabled		;\
	 */						;\
	rdpr	%pstate, scr1				;\
	or	scr1, PSTATE_IE, scr2			;\
	wrpr	scr2, %pstate				;\
							;\
	/*						;\
	 * Do a synchronous load to wait for 		;\
	 * MAU to idle.					;\
	 */						;\
	mov	ASI_MAU_SYNC, scr2			;\
	ldxa	[scr2]ASI_STREAM, %g0			;\
							;\
	/*						;\
	 * Restore interrupt state			;\
	 */						;\
	wrpr	scr1, %pstate

#endif

#ifdef __cplusplus
}
#endif

#endif /* _PLATFORM_MAU_H */
Commit	Line	Data
920dae64 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* Hypervisor Software File: mau.h
	5	*
	6	* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	7	*
	8	* - Do no alter or remove copyright notices
	9	*
	10	* - Redistribution and use of this software in source and binary forms, with
	11	* or without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistribution of source code must retain the above copyright notice,
	15	* this list of conditions and the following disclaimer.
	16	*
	17	* - Redistribution in binary form must reproduce the above copyright notice,
	18	* this list of conditions and the following disclaimer in the
	19	* documentation and/or other materials provided with the distribution.
	20	*
	21	* Neither the name of Sun Microsystems, Inc. or the names of contributors
	22	* may be used to endorse or promote products derived from this software
	23	* without specific prior written permission.
	24	*
	25	* This software is provided "AS IS," without a warranty of any kind.
	26	* ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	27	* INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	28	* PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	29	* MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	30	* ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	31	* DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	32	* OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	33	* FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	34	* DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	35	* ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	36	* SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	37	*
	38	* You acknowledge that this software is not designed, licensed or
	39	* intended for use in the design, construction, operation or maintenance of
	40	* any nuclear facility.
	41	*
	42	* ========== Copyright Header End ============================================
	43	*/
	44	/*
	45	* Copyright 2007 Sun Microsystems, Inc. All rights reserved.
	46	* Use is subject to license terms.
	47	*/
	48
	49	#ifndef _PLATFORM_MAU_H
	50	#define _PLATFORM_MAU_H
	51
	52	#pragma ident "@(#)mau.h 1.2 07/07/27 SMI"
	53
	54	#ifdef __cplusplus
	55	extern "C" {
	56	#endif
	57
	58	#include <config.h>
	59	#include <ncs.h>
	60	#include <resource.h>
	61
	62
	63	/*
	64	* MA Control Register
65	* Field Bits R/W
66	* ----- ---- ---
67	* STRAND 12:11 R/W
68	* BUSY 10 RO
69	* INTR 9 R/W
70	* OP 8:6 R/W
71	* LENGTH 5:0 R/W
72	*/
73	#define MA_CTL_STRAND_SHIFT 11
74	#define MA_CTL_BUSY_SHIFT 10
75	#define MA_CTL_INTR_SHIFT 9
76	#define MA_CTL_INTR_MASK 0x1
77	#define MA_CTL_OP_SHIFT 6
78	#define MA_CTL_OP_MASK 7
79	#define MA_CTL_LENGTH_MASK 0x3f
80
81	#ifdef _ASM
82
83	/* BEGIN CSTYLED */
84
85	/* Range check and real to phys conversion macro */
86	#define REAL_TO_PHYS(raddr, size, paddr, fail_label, gstruct, scr2) \
87	GUEST_STRUCT(gstruct) ;\
88	RA2PA_RANGE_CHECK(gstruct, raddr, size, fail_label, scr2) ;\
89	RA2PA_CONV(gstruct, raddr, paddr, scr2)
90
91	#define REAL_TO_PHYS_G(raddr, size, paddr, fail_label, gstruct, scr2) \
92	RA2PA_RANGE_CHECK(gstruct, raddr, size, fail_label, scr2) ;\
93	RA2PA_CONV(gstruct, raddr, paddr, scr2)
94
95	/*
96	* MAU_LOAD preps and loads MAU registers.
97	* If a Load or Store operation is being performed, then the
98	* MA address is translated to a physical address.
99	* Leaves an errno result in 'ret' if there is an
100	* alignment issue with the MA address.
101	*
102	* membar #Sync prior to storing Control register
103	* is due to NIAGARA_ERRATUM_41.
104	*/
105	#define MAU_LOAD(nhd, tid, ret, intr, errlbl, chklbl, scr1, scr2, scr3) \
106	.pushlocals ; \
107	ldx [nhd + MR_CTL], scr1 ; \
108	srlx scr1, MA_CTL_OP_SHIFT, scr2 ; \
109	and scr2, MA_CTL_OP_MASK, scr2 ; \
110	cmp scr2, MA_OP_LOAD ; \
111	be %xcc, 0f ; \
112	cmp scr2, MA_OP_STORE ; \
113	bne,a %xcc, 1f ; \
114	ldx [nhd + MR_MPA], scr1 ; \
115	0: ; \
116	and scr1, MA_CTL_LENGTH_MASK, scr1 ; \
117	inc scr1 ; \
118	sllx scr1, MA_WORDS2BYTES_SHIFT, scr2 ; \
119	ldx [nhd + MR_MPA], scr1 ; \
120	btst NCS_PTR_ALIGN - 1, scr1 ; \
121	bnz,a,pn %xcc, chklbl ; \
122	mov EINVAL, ret ; \
123	REAL_TO_PHYS(scr1, scr2, scr1, errlbl, scr3, ret) ; \
124	1: ; \
125	mov ASI_MAU_MPA, scr2 ; \
126	stxa scr1, [scr2]ASI_STREAM ; \
127	ldx [nhd + MR_MA], scr1 ; \
128	mov ASI_MAU_ADDR, scr2 ; \
129	stxa scr1, [scr2]ASI_STREAM ; \
130	ldx [nhd + MR_NP], scr1 ; \
131	mov ASI_MAU_NP, scr2 ; \
132	stxa scr1, [scr2]ASI_STREAM ; \
133	ldx [nhd + MR_CTL], scr1 ; \
134	sll tid, MA_CTL_STRAND_SHIFT, scr2 ; \
135	or scr1, scr2, scr1 ; \
136	mov ASI_MAU_CONTROL, scr2 ; \
137	membar #Sync ; \
138	mov MA_CTL_INTR_MASK, scr3 ; \
139	sllx scr3, MA_CTL_INTR_SHIFT, scr3 ; \
140	andn scr1, scr3, scr1 ; \
141	mov intr, scr3 ; \
142	and scr3, MA_CTL_INTR_MASK, scr3 ; \
143	sllx scr3, MA_CTL_INTR_SHIFT, scr3 ; \
144	or scr1, scr3, scr1 ; \
145	stxa scr1, [scr2]ASI_STREAM ; \
146	.poplocals
147
148	/*
149	* In Niagara-2 we'll be able to check for
150	* possible errors that occurred in the MAU,
151	* however for Niagara-1 we really can't.
152	* So, we assume success.
153	*/
154	#define MAU_CHECK_ERR(ret, scr1, scr2) \
155	mov %g0, ret
156
157
158	#define MAU_HANDLE_SIG 0x0864
159	#define HANDLE_SIGMASK 0xfff
160	#define HANDLE_IDMASK 0xfff
161	#define HANDLE_IDSHIFT 16
162	#define HANDLE2ID(hdl, idx) \
163	srlx hdl, HANDLE_IDSHIFT, idx ; \
164	and idx, HANDLE_IDMASK, idx
165	#define ID2HANDLE(idx, sig, hdl) \
166	and idx, HANDLE_IDMASK, hdl ; \
167	sllx hdl, HANDLE_IDSHIFT, hdl ; \
168	or hdl, sig, hdl
169	#define HANDLE_IS_MAU(hdl, scr) \
170	and hdl, HANDLE_SIGMASK, scr ; \
171	cmp scr, MAU_HANDLE_SIG
172	/*
173	* MAU_HANDLE2ID_VERIFY
174	* Translates and verifies a MAU specific handle
175	* for a valid signature and ID.
176	*/
177	#define MAU_HANDLE2ID_VERIFY(hdl, lbl, id) \
178	HANDLE_IS_MAU(hdl, id) ; \
179	bne,pn %xcc, lbl ; \
180	nop ; \
181	HANDLE2ID(hdl, id) ; \
182	cmp id, NMAUS ; \
183	bgeu,pn %xcc, lbl ; \
184	nop
185
186	#define MAU_CLEAR_QSTATE(mau) \
187	stx %g0, [mau + MAU_QUEUE + MQ_LOCK] ; \
188	stx %g0, [mau + MAU_QUEUE + MQ_BASE_RA] ; \
189	stx %g0, [mau + MAU_QUEUE + MQ_BASE] ; \
190	stx %g0, [mau + MAU_QUEUE + MQ_END] ; \
191	stx %g0, [mau + MAU_QUEUE + MQ_HEAD] ; \
192	stx %g0, [mau + MAU_QUEUE + MQ_HEAD_MARKER] ; \
193	stx %g0, [mau + MAU_QUEUE + MQ_TAIL] ; \
194	stx %g0, [mau + MAU_QUEUE + MQ_NENTRIES] ; \
195	st %g0, [mau + MAU_QUEUE + MQ_BUSY]
196
197	#define GUEST_MID_GETMAU(guest, id, mau) \
198	sllx id, GUEST_MAUS_SHIFT, mau ; \
199	add mau, GUEST_MAUS, mau ; \
200	ldx [guest + mau], mau
201
202	#define GUEST_MID_SETMAU(guest, id, mau, scr) \
203	sllx id, GUEST_MAUS_SHIFT, scr ; \
204	add scr, GUEST_MAUS, scr ; \
205	stx mau, [guest + scr]
206
207	#define MAU_LOCK_ENTER(mau, lck, scr1, scr2) \
208	add mau, MAU_QUEUE, lck ; \
209	add lck, MQ_LOCK, lck ; \
210	SPINLOCK_ENTER(lck, scr1, scr2)
211	#define MAU_LOCK_EXIT(mau, lck) \
212	add mau, MAU_QUEUE, lck ; \
213	add lck, MQ_LOCK, lck ; \
214	SPINLOCK_EXIT(lck)
215	#define MAU_LOCK_EXIT_L(lck) \
216	SPINLOCK_EXIT(lck)
217
218	/*
219	* We wait for the MAU to stop by doing a sync-load.
220	* If the MAU is currently busy running a job on behalf
221	* of the current strand (cpu) being stopped then the
222	* sync-load will wait for it to complete. If the MAU
223	* is busy running a job for a different strand (cpu)
224	* then the sync-load will immediately return. Since
225	* the job being executed is on behalf of a different
226	* cpu then the immediate return is okay since we only
227	* care about the local cpu being stopped.
228	*
229	* Note that we have to enable interrupts while doing
230	* this load to ensure the MAU can complete the operation
231	* including possibly handling an interrupt.
232	*/
233	#define CRYPTO_STOP(scr1, scr2) \
234	/* ;\
235	* Make sure interrupts are enabled ;\
236	*/ ;\
237	rdpr %pstate, scr1 ;\
238	or scr1, PSTATE_IE, scr2 ;\
239	wrpr scr2, %pstate ;\
240	;\
241	/* ;\
242	* Do a synchronous load to wait for ;\
243	* MAU to idle. ;\
244	*/ ;\
245	mov ASI_MAU_SYNC, scr2 ;\
246	ldxa [scr2]ASI_STREAM, %g0 ;\
247	;\
248	/* ;\
249	* Restore interrupt state ;\
250	*/ ;\
251	wrpr scr1, %pstate
252
253	#endif
254
255	#ifdef __cplusplus
256	}
257	#endif
258
259	#endif /* _PLATFORM_MAU_H */