[OpenSPARC-T2-SAM] / obp / obp / fm / kernel / sparc / move.fth

\ ========== Copyright Header Begin ==========================================
\ 
\ Hypervisor Software File: move.fth
\ 
\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
\ 
\  - Do no alter or remove copyright notices
\ 
\  - Redistribution and use of this software in source and binary forms, with 
\    or without modification, are permitted provided that the following 
\    conditions are met: 
\ 
\  - Redistribution of source code must retain the above copyright notice, 
\    this list of conditions and the following disclaimer.
\ 
\  - Redistribution in binary form must reproduce the above copyright notice,
\    this list of conditions and the following disclaimer in the
\    documentation and/or other materials provided with the distribution. 
\ 
\    Neither the name of Sun Microsystems, Inc. or the names of contributors 
\ may be used to endorse or promote products derived from this software 
\ without specific prior written permission. 
\ 
\     This software is provided "AS IS," without a warranty of any kind. 
\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, 
\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN 
\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR 
\ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR 
\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN 
\ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR 
\ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE 
\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, 
\ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF 
\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
\ 
\ You acknowledge that this software is not designed, licensed or
\ intended for use in the design, construction, operation or maintenance of
\ any nuclear facility. 
\ 
\ ========== Copyright Header End ============================================
\ move.fth 2.6 93/10/20
\ Copyright 1985-1990 Bradley Forthware

\ Mike Saari's blazing `move' ...
\ This implements the MOVE instruction.  It is optimized
\ for speed, particularly when longword stores may be used.

code (move)  ( src dst cnt -- )
			\ tos = Count
   sp 1 /n*  scr   nget	\ scr = Src address
   sp 0 /n*  sc1   nget	\ sc1 = Dst address
			\ sc2 = Temp. data being transferred
			\ sc3 = src xor drc, low bits=0 indicates compatible
			\ sc4 = Working src in loops
			\       (also temp last+1 address)
			\ sc5 = Working dst in loops
			\ sc6 = Loop index

   scr sc1  %g0  subcc	\ Src > dst?
   > if			\ Then copy low-to-high
      scr sc1  sc3  xor		\ (delay) sc3 low bits=0 indicates compatible

      tos h# 10   %g0  subcc	\ Enough bytes to bother optimizing?
      >= if			\ Otherwise, just skip to byte move
         sc3 1    %g0  andcc	\ (delay) =0 if at least shortword aligned
         0= if			\ Otherwise, just skip to byte move

            scr 1   %g0  andcc		\ (delay) Not on halfword boundary?
            0<> if		\ Ensure halfword alignment (lower)
               scr 0  sc2  ldub		\ (delay) Load bottom byte
               sc2  sc1 0  stb		\ Store byte 
               scr 1  scr  add		\ Advance by one byte
               sc1 1  sc1  add		\  "
               tos 1  tos  sub		\ Decrement count 
            then

            sc3 2   %g0  andcc		\ =0 if at least longword aligned
            0= if		\ Otherwise, skip to halfword case

               scr 2  %g0  andcc	\ (delay) Not on longword boundary?
               0<> if		\ Ensure longword alignment (lower)
                  scr 0  sc2  lduh	\ (delay) Load bottom halfword
                  sc2  sc1 0  sth	\ Store halfword
                  scr 2  scr  add	\ Advance by one halfword
                  sc1 2  sc1  add	\  "
                  tos 2  tos  sub       \ Decrement count
               then

               sc3 4  %g0  andcc	\ =0 if doublelong aligned
               0= if		\ Otherwise, skip to longword case

                  scr 4  %g0  andcc	\ (delay) Not on doublelong boundary?
                  0<> if	\ Ensure doublelong alignment (lower)
                     scr 0  sc2  ld	\ (delay) Load bottom longword
                     sc2  sc1 0  st	\ Store longword
                     scr 4  scr  add	\ Advance by one longword
                     sc1 4  sc1  add	\  "
                     tos 4  tos  sub	\ Decrement count
                  then
				\ Doublelong Copy Loop (low-to-high)
                  tos 7  sc6  andn	\ Index w/ even multiples of 8
                  scr sc6  scr  add	\ src = src+index
                  scr   8  sc4  sub 	\ Working src = src+index-8 
                  sc1 sc6  sc1  add	\ dst = dst+index
                  sc1   8  sc5  sub	\ Working dst = dst+index-8
                  %g0 sc6  sc6  subcc	\ Negate index
                  begin	
                  < while
                     sc6 8     sc6  addcc	\ (delay) Increment index
32\                  sc4 sc6   sc2  ldd		\ Load doublelong
64\                  sc4 sc6   sc2  ldx		\ Load 64-bit
                  repeat
32\                  sc2   sc5 sc6  std		\ (delay) Store doublelong
64\                  sc2   sc5 sc6  stx		\ (delay) Store 64-bit

                  tos 7   tos   and	\ At end, adjust cnt for few remaining

               else		\ Longword Copy Loop (low-to-high)
                  nop			\ (delay)
                  tos 3  sc6  andn	\ Index w/ even multiples of 4
                  scr sc6  scr  add	\ src = src+index
                  scr   4  sc4  sub	\ Working src = src+index-4 
                  sc1 sc6  sc1  add	\ dst = dst+index
                  sc1   4  sc5  sub	\ Working dst = dst+index-4
                  %g0 sc6  sc6  subcc	\ Negate index
                  begin
                  < while
                     sc6 4     sc6  addcc	\ (delay) Increment index
                     sc4 sc6   sc2  ld		\ Load longword
                  repeat
                     sc2   sc5 sc6  st		\ (delay) Store longword

                  tos 3   tos   and	\ At end, adjust cnt for few remaining
               then

            else 		\ Halfword Copy Loop (low-to-high)
               nop			\ (delay)
               tos 1  sc6  andn		\ Index w/ even multiples of 2
               scr sc6  scr  add	\ src = src+index
               scr   2  sc4  sub	\ Working src = src+index-2 
               sc1 sc6  sc1  add	\ dst = dst+index
               sc1   2  sc5  sub	\ Working dst = dst+index-2
               %g0 sc6  sc6  subcc	\ Negate index
               begin
               < while
                  sc6 2     sc6  addcc		\ (delay) Increment index
                  sc4 sc6   sc2  lduh		\ Load halfword
               repeat
                  sc2   sc5 sc6  sth		\ (delay) Store halfword

               tos 1   tos   and	\ At end, adjust cnt for few remaining
            then
         then			
      then	\ Now do a normal byte move for all remaining bytes (at top)

      \ Byte Copy Loop (low-to-high)
				\ (tos = index)
      scr tos  scr  add
      scr   1  sc4  sub		\ Working src = src+cnt-1 
      sc1 tos  sc1  add
      sc1   1  sc5  sub		\ Working dst = dst+cnt-1 
      %g0 tos  sc6  subcc	\ Negate index
      begin
      < while
         sc6 1     sc6  addcc	\ (delay) Increment cnt
         sc4 sc6   sc2  ldub	\ Load byte
      repeat
         sc2   sc5 sc6  stb	\ (delay) Store byte

   else  		\ Copy high-to-low case
      nop			\ (delay)
      tos h# 10   %g0  subcc	\ Enough bytes to bother optimizing?
      >= if			\ Otherwise, just skip to byte move
         sc3 1    %g0  andcc	\ (delay) =0 if at least shortword aligned
         0= if			\ Otherwise, just skip to byte move

            scr tos  sc4  add		\ (delay) Calculate last+1 address

            sc4 1    %g0  andcc		\ Not on halfword boundary? (at top)
            0<> if		\ Ensure halfword alignment (at top)
               sc4 -1   sc2  ldub	\ (delay) Load top byte
               tos 1    tos  sub	\ Decrement count 
               sc2  sc1 tos  stb	\ Store byte 
               sc4 1    sc4  sub	\ Recalculate last+1 address
            then

            sc3 2   %g0  andcc		\ =0 if at least longword aligned
            0= if		\ Otherwise, skip to halfword case

               sc4 2    %g0  andcc	\ (delay) Not on longword boundary? (at top)
               0<> if		\ Ensure longword alignment (at top)
                  sc4 -2   sc2  lduh	\ (delay) Load top halfword
                  tos 2    tos  sub	\ Decrement count
                  sc2  sc1 tos  sth	\ Store halfword
                  sc4 2    sc4  sub	\ Recalculate last+1 address
               then

               sc3 4  %g0  andcc	\ =0 if doublelong aligned
               0= if		\ Otherwise, skip to longword case

                  sc4 4  %g0  andcc	\ (delay) Not on doublelong boundary? (top)
                  0<> if	\ Ensure doublelong alignment (at top)
                     sc4 -4   sc2  ld	\ (delay) Load top longword
                     tos 4    tos  sub	\ Decrement count
                     sc2  sc1 tos  st	\ Store longword
                  then
				\ Doublelong Copy Loop (high-to-low)
                  scr 8   sc4   add	\ Working src = src+8
                  sc1 8   sc5   add	\ Working dst = dst+8
                  tos 8   sc6   subcc	\ Loop index = cnt-8
                  begin
                  >= while
                     sc6 8     sc6  subcc	\ (delay) Decrement index
32\                  sc4 sc6   sc2  ldd		\ Load doublelong
64\                  sc4 sc6   sc2  ldx		\ Load 64-bit
                  repeat
32\                  sc2   sc5 sc6  std		\ (delay) Store doublelong
64\                  sc2   sc5 sc6  stx		\ (delay) Store 64-bit

                  tos 7   tos   and	\ At end, adjust cnt for few remaining

               else		\ Longword Copy Loop (high-to-low)
                  nop			\ (delay)
                  scr 4   sc4   add	\ Working src = src+4
                  sc1 4   sc5   add	\ Working dst = dst+4
                  tos 4   sc6   subcc	\ Loop index = cnt-4
                  begin
                  >= while
                     sc6 4     sc6  subcc	\ (delay) Decrement index
                     sc4 sc6   sc2  ld		\ Load longword
                  repeat
                     sc2   sc5 sc6  st		\ (delay) Store longword

                  tos 3   tos   and	\ At end, adjust cnt for few remaining
               then

            else		\ Halfword Copy Loop (high-to-low)
               nop			\ (delay)
               scr 2   sc4   add	\ Working src = src+2
               sc1 2   sc5   add	\ Working dst = dst+2
               tos 2   sc6   subcc	\ Loop index = cnt-2
               begin
               >= while
                  sc6 2     sc6  subcc	\ (delay) Decrement index
                  sc4 sc6   sc2  lduh	\ Load halfword
               repeat
                  sc2   sc5 sc6  sth	\ (delay) Store halfword

               tos 1   tos   and	\ At end, adjust cnt for few remaining
            then
         then	
      then	\ Now do a normal byte move for all remaining bytes (at bottom)

      \ Byte Copy Loop (high-to-low)
      scr 1     sc4  add	\ Working src = src+1
      sc1 1     sc5  add	\ Working dst = dst+1
      tos 1     tos  subcc	\ Loop index = cnt-1
      begin
      >= while
         tos 1     tos  subcc	\ (delay) Decrement index
         sc4 tos   sc2  ldub	\ Load byte
      repeat
         sc2   sc5 tos  stb	\ (delay) Store byte
   then

   sp 2 /n*  tos nget	\ Delete 3 stack items
   sp 3 /n*  sp  add	\   "
c;
defer move
' (move) is move
Commit	Line	Data
920dae64 AT	1	\ ========== Copyright Header Begin ==========================================
	2	\
	3	\ Hypervisor Software File: move.fth
	4	\
	5	\ Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
	6	\
	7	\ - Do no alter or remove copyright notices
	8	\
	9	\ - Redistribution and use of this software in source and binary forms, with
	10	\ or without modification, are permitted provided that the following
	11	\ conditions are met:
	12	\
	13	\ - Redistribution of source code must retain the above copyright notice,
	14	\ this list of conditions and the following disclaimer.
	15	\
	16	\ - Redistribution in binary form must reproduce the above copyright notice,
	17	\ this list of conditions and the following disclaimer in the
	18	\ documentation and/or other materials provided with the distribution.
	19	\
	20	\ Neither the name of Sun Microsystems, Inc. or the names of contributors
	21	\ may be used to endorse or promote products derived from this software
	22	\ without specific prior written permission.
	23	\
	24	\ This software is provided "AS IS," without a warranty of any kind.
	25	\ ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES,
	26	\ INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A
	27	\ PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN
	28	\ MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR
	29	\ ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR
	30	\ DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN
	31	\ OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR
	32	\ FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE
	33	\ DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY,
	34	\ ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF
	35	\ SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
	36	\
	37	\ You acknowledge that this software is not designed, licensed or
	38	\ intended for use in the design, construction, operation or maintenance of
	39	\ any nuclear facility.
	40	\
	41	\ ========== Copyright Header End ============================================
	42	\ move.fth 2.6 93/10/20
	43	\ Copyright 1985-1990 Bradley Forthware
	44
	45	\ Mike Saari's blazing `move' ...
	46	\ This implements the MOVE instruction. It is optimized
	47	\ for speed, particularly when longword stores may be used.
	48
	49	code (move) ( src dst cnt -- )
	50	\ tos = Count
	51	sp 1 /n* scr nget \ scr = Src address
	52	sp 0 /n* sc1 nget \ sc1 = Dst address
	53	\ sc2 = Temp. data being transferred
	54	\ sc3 = src xor drc, low bits=0 indicates compatible
	55	\ sc4 = Working src in loops
	56	\ (also temp last+1 address)
	57	\ sc5 = Working dst in loops
	58	\ sc6 = Loop index
	59
	60	scr sc1 %g0 subcc \ Src > dst?
	61	> if \ Then copy low-to-high
	62	scr sc1 sc3 xor \ (delay) sc3 low bits=0 indicates compatible
	63
	64	tos h# 10 %g0 subcc \ Enough bytes to bother optimizing?
65	>= if \ Otherwise, just skip to byte move
66	sc3 1 %g0 andcc \ (delay) =0 if at least shortword aligned
67	0= if \ Otherwise, just skip to byte move
68
69	scr 1 %g0 andcc \ (delay) Not on halfword boundary?
70	0<> if \ Ensure halfword alignment (lower)
71	scr 0 sc2 ldub \ (delay) Load bottom byte
72	sc2 sc1 0 stb \ Store byte
73	scr 1 scr add \ Advance by one byte
74	sc1 1 sc1 add \ "
75	tos 1 tos sub \ Decrement count
76	then
77
78	sc3 2 %g0 andcc \ =0 if at least longword aligned
79	0= if \ Otherwise, skip to halfword case
80
81	scr 2 %g0 andcc \ (delay) Not on longword boundary?
82	0<> if \ Ensure longword alignment (lower)
83	scr 0 sc2 lduh \ (delay) Load bottom halfword
84	sc2 sc1 0 sth \ Store halfword
85	scr 2 scr add \ Advance by one halfword
86	sc1 2 sc1 add \ "
87	tos 2 tos sub \ Decrement count
88	then
89
90	sc3 4 %g0 andcc \ =0 if doublelong aligned
91	0= if \ Otherwise, skip to longword case
92
93	scr 4 %g0 andcc \ (delay) Not on doublelong boundary?
94	0<> if \ Ensure doublelong alignment (lower)
95	scr 0 sc2 ld \ (delay) Load bottom longword
96	sc2 sc1 0 st \ Store longword
97	scr 4 scr add \ Advance by one longword
98	sc1 4 sc1 add \ "
99	tos 4 tos sub \ Decrement count
100	then
101	\ Doublelong Copy Loop (low-to-high)
102	tos 7 sc6 andn \ Index w/ even multiples of 8
103	scr sc6 scr add \ src = src+index
104	scr 8 sc4 sub \ Working src = src+index-8
105	sc1 sc6 sc1 add \ dst = dst+index
106	sc1 8 sc5 sub \ Working dst = dst+index-8
107	%g0 sc6 sc6 subcc \ Negate index
108	begin
109	< while
110	sc6 8 sc6 addcc \ (delay) Increment index
111	32\ sc4 sc6 sc2 ldd \ Load doublelong
112	64\ sc4 sc6 sc2 ldx \ Load 64-bit
113	repeat
114	32\ sc2 sc5 sc6 std \ (delay) Store doublelong
115	64\ sc2 sc5 sc6 stx \ (delay) Store 64-bit
116
117	tos 7 tos and \ At end, adjust cnt for few remaining
118
119	else \ Longword Copy Loop (low-to-high)
120	nop \ (delay)
121	tos 3 sc6 andn \ Index w/ even multiples of 4
122	scr sc6 scr add \ src = src+index
123	scr 4 sc4 sub \ Working src = src+index-4
124	sc1 sc6 sc1 add \ dst = dst+index
125	sc1 4 sc5 sub \ Working dst = dst+index-4
126	%g0 sc6 sc6 subcc \ Negate index
127	begin
128	< while
129	sc6 4 sc6 addcc \ (delay) Increment index
130	sc4 sc6 sc2 ld \ Load longword
131	repeat
132	sc2 sc5 sc6 st \ (delay) Store longword
133
134	tos 3 tos and \ At end, adjust cnt for few remaining
135	then
136
137	else \ Halfword Copy Loop (low-to-high)
138	nop \ (delay)
139	tos 1 sc6 andn \ Index w/ even multiples of 2
140	scr sc6 scr add \ src = src+index
141	scr 2 sc4 sub \ Working src = src+index-2
142	sc1 sc6 sc1 add \ dst = dst+index
143	sc1 2 sc5 sub \ Working dst = dst+index-2
144	%g0 sc6 sc6 subcc \ Negate index
145	begin
146	< while
147	sc6 2 sc6 addcc \ (delay) Increment index
148	sc4 sc6 sc2 lduh \ Load halfword
149	repeat
150	sc2 sc5 sc6 sth \ (delay) Store halfword
151
152	tos 1 tos and \ At end, adjust cnt for few remaining
153	then
154	then
155	then \ Now do a normal byte move for all remaining bytes (at top)
156
157	\ Byte Copy Loop (low-to-high)
158	\ (tos = index)
159	scr tos scr add
160	scr 1 sc4 sub \ Working src = src+cnt-1
161	sc1 tos sc1 add
162	sc1 1 sc5 sub \ Working dst = dst+cnt-1
163	%g0 tos sc6 subcc \ Negate index
164	begin
165	< while
166	sc6 1 sc6 addcc \ (delay) Increment cnt
167	sc4 sc6 sc2 ldub \ Load byte
168	repeat
169	sc2 sc5 sc6 stb \ (delay) Store byte
170
171	else \ Copy high-to-low case
172	nop \ (delay)
173	tos h# 10 %g0 subcc \ Enough bytes to bother optimizing?
174	>= if \ Otherwise, just skip to byte move
175	sc3 1 %g0 andcc \ (delay) =0 if at least shortword aligned
176	0= if \ Otherwise, just skip to byte move
177
178	scr tos sc4 add \ (delay) Calculate last+1 address
179
180	sc4 1 %g0 andcc \ Not on halfword boundary? (at top)
181	0<> if \ Ensure halfword alignment (at top)
182	sc4 -1 sc2 ldub \ (delay) Load top byte
183	tos 1 tos sub \ Decrement count
184	sc2 sc1 tos stb \ Store byte
185	sc4 1 sc4 sub \ Recalculate last+1 address
186	then
187
188	sc3 2 %g0 andcc \ =0 if at least longword aligned
189	0= if \ Otherwise, skip to halfword case
190
191	sc4 2 %g0 andcc \ (delay) Not on longword boundary? (at top)
192	0<> if \ Ensure longword alignment (at top)
193	sc4 -2 sc2 lduh \ (delay) Load top halfword
194	tos 2 tos sub \ Decrement count
195	sc2 sc1 tos sth \ Store halfword
196	sc4 2 sc4 sub \ Recalculate last+1 address
197	then
198
199	sc3 4 %g0 andcc \ =0 if doublelong aligned
200	0= if \ Otherwise, skip to longword case
201
202	sc4 4 %g0 andcc \ (delay) Not on doublelong boundary? (top)
203	0<> if \ Ensure doublelong alignment (at top)
204	sc4 -4 sc2 ld \ (delay) Load top longword
205	tos 4 tos sub \ Decrement count
206	sc2 sc1 tos st \ Store longword
207	then
208	\ Doublelong Copy Loop (high-to-low)
209	scr 8 sc4 add \ Working src = src+8
210	sc1 8 sc5 add \ Working dst = dst+8
211	tos 8 sc6 subcc \ Loop index = cnt-8
212	begin
213	>= while
214	sc6 8 sc6 subcc \ (delay) Decrement index
215	32\ sc4 sc6 sc2 ldd \ Load doublelong
216	64\ sc4 sc6 sc2 ldx \ Load 64-bit
217	repeat
218	32\ sc2 sc5 sc6 std \ (delay) Store doublelong
219	64\ sc2 sc5 sc6 stx \ (delay) Store 64-bit
220
221	tos 7 tos and \ At end, adjust cnt for few remaining
222
223	else \ Longword Copy Loop (high-to-low)
224	nop \ (delay)
225	scr 4 sc4 add \ Working src = src+4
226	sc1 4 sc5 add \ Working dst = dst+4
227	tos 4 sc6 subcc \ Loop index = cnt-4
228	begin
229	>= while
230	sc6 4 sc6 subcc \ (delay) Decrement index
231	sc4 sc6 sc2 ld \ Load longword
232	repeat
233	sc2 sc5 sc6 st \ (delay) Store longword
234
235	tos 3 tos and \ At end, adjust cnt for few remaining
236	then
237
238	else \ Halfword Copy Loop (high-to-low)
239	nop \ (delay)
240	scr 2 sc4 add \ Working src = src+2
241	sc1 2 sc5 add \ Working dst = dst+2
242	tos 2 sc6 subcc \ Loop index = cnt-2
243	begin
244	>= while
245	sc6 2 sc6 subcc \ (delay) Decrement index
246	sc4 sc6 sc2 lduh \ Load halfword
247	repeat
248	sc2 sc5 sc6 sth \ (delay) Store halfword
249
250	tos 1 tos and \ At end, adjust cnt for few remaining
251	then
252	then
253	then \ Now do a normal byte move for all remaining bytes (at bottom)
254
255	\ Byte Copy Loop (high-to-low)
256	scr 1 sc4 add \ Working src = src+1
257	sc1 1 sc5 add \ Working dst = dst+1
258	tos 1 tos subcc \ Loop index = cnt-1
259	begin
260	>= while
261	tos 1 tos subcc \ (delay) Decrement index
262	sc4 tos sc2 ldub \ Load byte
263	repeat
264	sc2 sc5 tos stb \ (delay) Store byte
265	then
266
267	sp 2 /n* tos nget \ Delete 3 stack items
268	sp 3 /n* sp add \ "
269	c;
270	defer move
271	' (move) is move