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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: N2_IrfEcc.cc | |
4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. | |
5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. | |
6 | // | |
7 | // The above named program is free software; you can redistribute it and/or | |
8 | // modify it under the terms of the GNU General Public | |
9 | // License version 2 as published by the Free Software Foundation. | |
10 | // | |
11 | // The above named program is distributed in the hope that it will be | |
12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | // General Public License for more details. | |
15 | // | |
16 | // You should have received a copy of the GNU General Public | |
17 | // License along with this work; if not, write to the Free Software | |
18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. | |
19 | // | |
20 | // ========== Copyright Header End ============================================ | |
21 | /************************************************************************ | |
22 | ** | |
23 | ** Copyright (C) 2006, Sun Microsystems, Inc. | |
24 | ** | |
25 | ** Sun considers its source code as an unpublished, proprietary | |
26 | ** trade secret and it is available only under strict license provisions. | |
27 | ** This copyright notice is placed here only to protect Sun in the event | |
28 | ** the source is deemed a published work. Disassembly, decompilation, | |
29 | ** or other means of reducing the object code to human readable form | |
30 | ** is prohibited by the license agreement under which this code is | |
31 | ** provided to the user or company in possession of this copy. | |
32 | ** | |
33 | *************************************************************************/ | |
34 | ||
35 | #include "N2_Core.h" | |
36 | #include "N2_Strand.h" | |
37 | #include "N2_IrfEcc.h" | |
38 | #include "BL_Hamming_64_8_Synd.h" | |
39 | ||
40 | extern "C" SS_Vaddr n2_irf_ras_inject(SS_Vaddr pc, | |
41 | SS_Vaddr npc, | |
42 | SS_Strand* s, | |
43 | SS_Instr* i, | |
44 | int reg_nr) | |
45 | { | |
46 | assert (reg_nr >= 0 && reg_nr < 32); | |
47 | N2_Strand* n2_strand = (N2_Strand *)s; | |
48 | N2_Core& n2_core = n2_strand->core; | |
49 | ||
50 | unsigned long long value = n2_strand->get_irf(SS_Strand::reg_idx2off(reg_nr)); | |
51 | BL_EccBits ecc_obj = BL_Hamming_64_8_Synd::calc_check_bits(value); | |
52 | unsigned ecc = ecc_obj.get(); | |
53 | if ((n2_core.error_inject.ene() == 1) && (n2_core.error_inject.ircu() == 1)) | |
54 | { | |
55 | ecc ^= n2_core.error_inject.eccmask(); | |
56 | } | |
57 | // Set back the corrputed ecc | |
58 | ecc_obj.set(ecc); | |
59 | n2_strand->irf_ecc[reg_nr] = ecc_obj; | |
60 | return 0; // Not sure if this is the right value to return | |
61 | } | |
62 | ||
63 | // This method detects any errors (injected or otherwise), associtated | |
64 | // with this particular register in IRF | |
65 | extern "C" SS_Vaddr n2_irf_ras_detect(SS_Vaddr pc, | |
66 | SS_Vaddr npc, | |
67 | SS_Strand* s, | |
68 | SS_Instr* i, | |
69 | int reg_nr) | |
70 | { | |
71 | assert (reg_nr >= 0 && reg_nr < 32); | |
72 | N2_Strand* n2_strand = (N2_Strand *)s; | |
73 | N2_Core& n2_core = n2_strand->core; | |
74 | ||
75 | // Error Detection happens only if the IRF bit in CERER is set | |
76 | if (n2_core.cerer.irf()) | |
77 | { | |
78 | unsigned long long value = n2_strand->get_irf(SS_Strand::reg_idx2off(reg_nr)); | |
79 | BL_EccBits ecc_obj = n2_strand->irf_ecc[reg_nr]; | |
80 | // Check if the ecc associated with this register is a valid ecc | |
81 | if (ecc_obj.valid()) | |
82 | { | |
83 | // Syndrome is the difference between the stored and calculated ECC values | |
84 | BL_Hamming_64_8_Synd syndrome = BL_Hamming_64_8_Synd(value,ecc_obj); | |
85 | // Setting the current global level | |
86 | unsigned long long gl = 0; // Dummy value... need to get actual val | |
87 | unsigned long long temp_reg = reg_nr; | |
88 | // If the syndrome is not zero, then it means an ECC error has occured | |
89 | if (!syndrome.noError()) | |
90 | { | |
91 | // Errors are recorded only if the PSCCE bit is set in the SETER | |
92 | if (n2_strand->seter.pscce()) | |
93 | { | |
94 | if (syndrome.isSingleBitError()) | |
95 | n2_strand->data_sfsr.error_type(2); | |
96 | else if (syndrome.isDoubleBitError() || syndrome.isMultipleBitError()) | |
97 | n2_strand->data_sfsr.error_type(1); | |
98 | unsigned long long native_add = 0; | |
99 | // Based on N2 PRM, the syndrome should be recorded | |
100 | // in bits 14:7 of DSFAR (fault address register) | |
101 | unsigned long long intermediate_err_add = (native_add & ~0x7f80ULL) | | |
102 | syndrome.getSyndrome() << 7; | |
103 | // Capture global level in bits 6:5 | |
104 | unsigned long long intermediate1_err_add = (intermediate_err_add & ~0x60ULL) | | |
105 | gl << 5; | |
106 | // capture the register number in bits 4:0 | |
107 | unsigned long long error_add = (intermediate1_err_add & ~0x1fULL) | temp_reg; | |
108 | n2_strand->data_sfar.error_addr(error_add); | |
109 | return (s->trap)(pc,npc,s,i,SS_Trap::INTERNAL_PROCESSOR_ERROR); | |
110 | } | |
111 | } | |
112 | } | |
113 | // If the ecc associated with the register is invalid | |
114 | else | |
115 | { | |
116 | // Not sure what the exact functioning should be in this case | |
117 | // Should we calculate clean ecc and associate it with this reg (as in Riesling) | |
118 | // unsigned ecc = N2_EccFile::calc_n2_IRF_checks(value); | |
119 | // setECC(reg, ecc); | |
120 | // Or should the program just call it quits! | |
121 | // cerr << " Invalid ECC: Aborting!" << endl; | |
122 | // exit(-1); | |
123 | } | |
124 | } | |
125 | } |