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[OpenSPARC-T2-SAM] / sam-t2 / sam / devices / sas / include / mpi_ioc.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: mpi_ioc.h
5* Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
6* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
7*
8* The above named program is free software; you can redistribute it and/or
9* modify it under the terms of the GNU General Public
10* License version 2 as published by the Free Software Foundation.
11*
12* The above named program is distributed in the hope that it will be
13* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15* General Public License for more details.
16*
17* You should have received a copy of the GNU General Public
18* License along with this work; if not, write to the Free Software
19* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
20*
21* ========== Copyright Header End ============================================
22*/
23/*
24 * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
25 * Use is subject to license terms.
26 */
27
28#ifndef _SYS_MPI_IOC_H
29#define _SYS_MPI_IOC_H
30
31#pragma ident "@(#)mpi_ioc.h 1.2 04/11/08 SMI"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37/*
38 * IOCInit message
39 */
40typedef struct msg_ioc_init {
41 uint8_t WhoInit;
42 uint8_t Reserved;
43 uint8_t ChainOffset;
44 uint8_t Function;
45 uint8_t Flags;
46 uint8_t MaxDevices;
47 uint8_t MaxBuses;
48 uint8_t MsgFlags;
49 uint32_t MsgContext;
50 uint16_t ReplyFrameSize;
51 uint8_t Reserved1[2];
52 uint32_t HostMfaHighAddr;
53 uint32_t SenseBufferHighAddr;
54 /* following used in new mpi implementations */
55 uint32_t ReplyFifoHostSignalingAddr;
56 sge_simple64_t HostPageBufferSGE;
57 uint16_t MsgVersion;
58 uint16_t HeaderVersion;
59} msg_ioc_init_t;
60
61typedef struct msg_ioc_init_reply {
62 uint8_t WhoInit;
63 uint8_t Reserved;
64 uint8_t MsgLength;
65 uint8_t Function;
66 uint8_t Flags;
67 uint8_t MaxDevices;
68 uint8_t MaxBuses;
69 uint8_t MsgFlags;
70 uint32_t MsgContext;
71 uint16_t Reserved2;
72 uint16_t IOCStatus;
73 uint32_t IOCLogInfo;
74} msg_ioc_init_reply_t;
75
76/*
77 * WhoInit values
78 */
79#define MPI_WHOINIT_NO_ONE 0x00
80#define MPI_WHOINIT_SYSTEM_BIOS 0x01
81#define MPI_WHOINIT_ROM_BIOS 0x02
82#define MPI_WHOINIT_PCI_PEER 0x03
83#define MPI_WHOINIT_HOST_DRIVER 0x04
84#define MPI_WHOINIT_MANUFACTURER 0x05
85
86/*
87 * Flags values
88 */
89#define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE 0x01
90#define MPI_IOCINIT_FLAGS_REPLY_FIFO_HOST_SIGNAL 0x02
91
92#define MPI_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
93#define MPI_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
94#define MPI_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
95#define MPI_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
96
97#define MPI_IOCINIT_HEADERVERSION_UNIT_MASK (0xFF00)
98#define MPI_IOCINIT_HEADERVERSION_UNIT_SHIFT (8)
99#define MPI_IOCINIT_HEADERVERSION_DEV_MASK (0x00FF)
100#define MPI_IOCINIT_HEADERVERSION_DEV_SHIFT (0)
101
102
103/*
104 * IOC Facts message
105 */
106typedef struct msg_ioc_facts {
107 uint8_t Reserved[2];
108 uint8_t ChainOffset;
109 uint8_t Function;
110 uint8_t Reserved1[3];
111 uint8_t MsgFlags;
112 uint32_t MsgContext;
113} msg_ioc_facts_t;
114
115/*
116 * FW version
117 */
118typedef struct mpi_fw_version_struct {
119 uint8_t Dev;
120 uint8_t Unit;
121 uint8_t Minor;
122 uint8_t Major;
123} mpi_fw_version_struct_t;
124
125typedef union mpi_fw_version {
126 mpi_fw_version_struct_t Struct;
127 uint32_t Word;
128} mpi_fw_version_t;
129
130/*
131 * IOC Facts Reply
132 */
133typedef struct msg_ioc_facts_reply {
134 uint16_t MsgVersion;
135 uint8_t MsgLength;
136 uint8_t Function;
137 uint16_t HeaderVersion;
138 uint8_t IOCNumber;
139 uint8_t MsgFlags;
140 uint32_t MsgContext;
141 uint16_t IOCExceptions;
142 uint16_t IOCStatus;
143 uint32_t IOCLogInfo;
144 uint8_t MaxChainDepth;
145 uint8_t WhoInit;
146 uint8_t BlockSize;
147 uint8_t Flags;
148 uint16_t ReplyQueueDepth;
149 uint16_t RequestFrameSize;
150 uint16_t Reserved_0101_FWVersion; /* obsolete */
151 uint16_t ProductID;
152 uint32_t CurrentHostMfaHighAddr;
153 uint16_t GlobalCredits;
154 uint8_t NumberOfPorts;
155 uint8_t EventState;
156 uint32_t CurrentSenseBufferHighAddr;
157 uint16_t CurReplyFrameSize;
158 uint8_t MaxDevices;
159 uint8_t MaxBuses;
160 uint32_t FWImageSize;
161 uint32_t IOCCapabilities;
162 mpi_fw_version_t FWVersion;
163 /* following used in newer mpi implementations */
164 uint16_t HighPriorityQueueDepth;
165 uint16_t Reserved2;
166 sge_simple64_t HostPageBufferSGE;
167} msg_ioc_facts_reply_t;
168
169#define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK 0xFF00
170#define MPI_IOCFACTS_MSGVERSION_MINOR_MASK 0x00FF
171
172#define MPI_IOCFACTS_HEADERVERSION_UNIT_MASK 0xFF00
173#define MPI_IOCFACTS_HEADERVERSION_DEV_MASK 0x00FF
174
175#define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL 0x0001
176#define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID 0x0002
177#define MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL 0x0004
178#define MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL 0x0008
179
180#define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT 0x01
181
182#define MPI_IOCFACTS_EVENTSTATE_DISABLED 0x00
183#define MPI_IOCFACTS_EVENTSTATE_ENABLED 0x01
184
185#define MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q 0x00000001
186#define MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL 0x00000002
187#define MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING 0x00000004
188#define MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER 0x00000008
189#define MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER 0x00000010
190#define MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER 0x00000020
191#define MPI_IOCFACTS_CAPABILITY_EEDP 0x00000040
192
193/*
194 * Port Facts message and Reply
195 */
196typedef struct msg_port_facts {
197 uint8_t Reserved[2];
198 uint8_t ChainOffset;
199 uint8_t Function;
200 uint8_t Reserved1[2];
201 uint8_t PortNumber;
202 uint8_t MsgFlags;
203 uint32_t MsgContext;
204} msg_port_facts_t;
205
206typedef struct msg_port_facts_reply {
207 uint16_t Reserved;
208 uint8_t MsgLength;
209 uint8_t Function;
210 uint16_t Reserved1;
211 uint8_t PortNumber;
212 uint8_t MsgFlags;
213 uint32_t MsgContext;
214 uint16_t Reserved2;
215 uint16_t IOCStatus;
216 uint32_t IOCLogInfo;
217 uint8_t Reserved3;
218 uint8_t PortType;
219 uint16_t MaxDevices;
220 uint16_t PortSCSIID;
221 uint16_t ProtocolFlags;
222 uint16_t MaxPostedCmdBuffers;
223 uint16_t MaxPersistentIDs;
224 uint16_t MaxLanBuckets;
225 uint16_t Reserved4;
226 uint32_t Reserved5;
227} msg_port_facts_reply_t;
228
229/*
230 * PortTypes values
231 */
232#define MPI_PORTFACTS_PORTTYPE_INACTIVE 0x00
233#define MPI_PORTFACTS_PORTTYPE_SCSI 0x01
234#define MPI_PORTFACTS_PORTTYPE_FC 0x10
235#define MPI_PORTFACTS_PORTTYPE_ISCSI 0x20
236#define MPI_PORTFACTS_PORTTYPE_SAS 0x30
237
238/*
239 * ProtocolFlags values
240 */
241#define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR 0x01
242#define MPI_PORTFACTS_PROTOCOL_LAN 0x02
243#define MPI_PORTFACTS_PROTOCOL_TARGET 0x04
244#define MPI_PORTFACTS_PROTOCOL_INITIATOR 0x08
245
246/*
247 * Port Enable Message
248 */
249typedef struct msg_port_enable {
250 uint8_t Reserved[2];
251 uint8_t ChainOffset;
252 uint8_t Function;
253 uint8_t Reserved1[2];
254 uint8_t PortNumber;
255 uint8_t MsgFlags;
256 uint32_t MsgContext;
257} msg_port_enable_t;
258
259typedef struct msg_port_enable_reply {
260 uint8_t Reserved[2];
261 uint8_t MsgLength;
262 uint8_t Function;
263 uint8_t Reserved1[2];
264 uint8_t PortNumber;
265 uint8_t MsgFlags;
266 uint32_t MsgContext;
267 uint16_t Reserved2;
268 uint16_t IOCStatus;
269 uint32_t IOCLogInfo;
270} msg_port_enable_reply_t;
271
272
273/*
274 * Event Notification messages
275 */
276typedef struct msg_event_notify {
277 uint8_t Switch;
278 uint8_t Reserved;
279 uint8_t ChainOffset;
280 uint8_t Function;
281 uint8_t Reserved1[3];
282 uint8_t MsgFlags;
283 uint32_t MsgContext;
284} msg_event_notify_t;
285
286/*
287 * Event Notification Reply
288 */
289typedef struct msg_event_notify_reply {
290 uint16_t EventDataLength;
291 uint8_t MsgLength;
292 uint8_t Function;
293 uint8_t Reserved1[2];
294 uint8_t AckRequired;
295 uint8_t MsgFlags;
296 uint32_t MsgContext;
297 uint8_t Reserved2[2];
298 uint16_t IOCStatus;
299 uint32_t IOCLogInfo;
300 uint32_t Event;
301 uint32_t EventContext;
302 uint32_t Data[1];
303} msg_event_notify_reply_t;
304
305/*
306 * Event Acknowledge
307 */
308typedef struct msg_event_ack {
309 uint8_t Reserved[2];
310 uint8_t ChainOffset;
311 uint8_t Function;
312 uint8_t Reserved1[3];
313 uint8_t MsgFlags;
314 uint32_t MsgContext;
315 uint32_t Event;
316 uint32_t EventContext;
317} msg_event_ack_t;
318
319typedef struct msg_event_ack_reply {
320 uint8_t Reserved[2];
321 uint8_t Function;
322 uint8_t MsgLength;
323 uint8_t Reserved1[3];
324 uint8_t MsgFlags;
325 uint32_t MsgContext;
326 uint16_t Reserved2;
327 uint16_t IOCStatus;
328 uint32_t IOCLogInfo;
329} msg_event_ack_reply_t;
330
331/*
332 * Switch
333 */
334#define MPI_EVENT_NOTIFICATION_SWITCH_OFF 0x00
335#define MPI_EVENT_NOTIFICATION_SWITCH_ON 0x01
336
337/*
338 * Event
339 */
340#define MPI_EVENT_NONE 0x00000000
341#define MPI_EVENT_LOG_DATA 0x00000001
342#define MPI_EVENT_STATE_CHANGE 0x00000002
343#define MPI_EVENT_UNIT_ATTENTION 0x00000003
344#define MPI_EVENT_IOC_BUS_RESET 0x00000004
345#define MPI_EVENT_EXT_BUS_RESET 0x00000005
346#define MPI_EVENT_RESCAN 0x00000006
347#define MPI_EVENT_LINK_STATUS_CHANGE 0x00000007
348#define MPI_EVENT_LOOP_STATE_CHANGE 0x00000008
349#define MPI_EVENT_LOGOUT 0x00000009
350#define MPI_EVENT_EVENT_CHANGE 0x0000000A
351#define MPI_EVENT_INTEGRATED_RAID 0x0000000B
352#define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE 0x0000000C
353#define MPI_EVENT_ON_BUS_TIMER_EXPIRED 0x0000000D
354#define MPI_EVENT_QUEUE_FULL 0x0000000E
355#define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE 0x0000000F
356#define MPI_EVENT_SAS_SES 0x00000010
357#define MPI_EVENT_PERSISTENT_TABLE_FULL 0x00000011
358#define MPI_EVENT_SAS_PHY_LINK_STATUS 0x00000012
359#define MPI_EVENT_SAS_DISCOVERY_ERROR 0x00000013
360
361/*
362 * AckRequired field values
363 */
364#define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED 0x00
365#define MPI_EVENT_NOTIFICATION_ACK_REQUIRED 0x01
366
367/*
368 * Eventchange event data
369 */
370typedef struct event_data_event_change {
371 uint8_t EventState;
372 uint8_t Reserved;
373 uint16_t Reserved1;
374} event_data_event_change_t;
375
376/*
377 * SCSI Event data for Port, Bus and Device forms)
378 */
379typedef struct event_data_scsi {
380 uint8_t TargetID;
381 uint8_t BusPort;
382 uint16_t Reserved;
383} event_data_scsi_t;
384
385/*
386 * SCSI Device Status Change Event data
387 */
388typedef struct event_data_scsi_device_status_change {
389 uint8_t TargetID;
390 uint8_t Bus;
391 uint8_t ReasonCode;
392 uint8_t LUN;
393 uint8_t ASC;
394 uint8_t ASCQ;
395 uint16_t Reserved;
396} event_data_scsi_device_status_change_t;
397
398/*
399 * SCSI Device Status Change Event data ReasonCode values
400 */
401#define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED 0x03
402#define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING 0x04
403#define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA 0x05
404
405/*
406 * SAS Device Status Change event data
407 */
408typedef struct event_data_sas_device_status_change {
409 uint8_t TargetID;
410 uint8_t Bus;
411 uint8_t ReasonCode;
412 uint8_t Reserved;
413 uint8_t ASC;
414 uint8_t ASCQ;
415 uint16_t DevHandle;
416 uint32_t DeviceInfo;
417 uint16_t ParentDevHandle;
418 uint8_t PhyNum;
419 uint8_t Reserved1;
420 uint64_t SASAddress;
421} event_data_sas_device_status_change_t;
422
423#define MPI_EVENT_SAS_DEV_STAT_RC_ADDED 0x03
424#define MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING 0x04
425#define MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA 0x05
426#define MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED 0x06
427
428/*
429 * SCSI event data for queue full event
430 */
431typedef struct event_data_queue_full {
432 uint8_t TargetID;
433 uint8_t Bus;
434 uint16_t CurrentDepth;
435} event_data_queue_full_t;
436
437/*
438 * MPI Link Status Change Event data
439 */
440typedef struct event_data_link_status {
441 uint8_t State;
442 uint8_t Reserved;
443 uint16_t Reserved1;
444 uint8_t Reserved2;
445 uint8_t Port;
446 uint16_t Reserved3;
447} event_data_link_status_t;
448
449#define MPI_EVENT_LINK_STATUS_FAILURE 0x00000000
450#define MPI_EVENT_LINK_STATUS_ACTIVE 0x00000001
451
452/* MPI Loop State Change Event data */
453
454typedef struct event_data_loop_state {
455 uint8_t Character4;
456 uint8_t Character3;
457 uint8_t Type;
458 uint8_t Reserved;
459 uint8_t Reserved1;
460 uint8_t Port;
461 uint16_t Reserved2;
462} event_data_loop_state_t;
463
464#define MPI_EVENT_LOOP_STATE_CHANGE_LIP 0x0001
465#define MPI_EVENT_LOOP_STATE_CHANGE_LPE 0x0002
466#define MPI_EVENT_LOOP_STATE_CHANGE_LPB 0x0003
467
468/*
469 * MPI LOGOUT Event data
470 */
471typedef struct event_data_logout {
472 uint32_t NPortID;
473 uint8_t Reserved;
474 uint8_t Port;
475 uint16_t Reserved1;
476} event_data_logout_t;
477
478/*
479 * MPI RAID Status Change Event Data
480 */
481typedef struct event_data_raid {
482 uint8_t VolumeID;
483 uint8_t VolumeBus;
484 uint8_t ReasonCode;
485 uint8_t PhysDiskNum;
486 uint8_t ASC;
487 uint8_t ASCQ;
488 uint16_t Reserved;
489 uint32_t SettingsStatus;
490} event_data_raid_t;
491
492/* MPI RAID Status Change Event data ReasonCode values */
493#define MPI_EVENT_RAID_RC_VOLUME_CREATED 0x00
494#define MPI_EVENT_RAID_RC_VOLUME_DELETED 0x01
495#define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED 0x02
496#define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED 0x03
497#define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED 0x04
498#define MPI_EVENT_RAID_RC_PHYSDISK_CREATED 0x05
499#define MPI_EVENT_RAID_RC_PHYSDISK_DELETED 0x06
500#define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED 0x07
501#define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED 0x08
502#define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED 0x09
503#define MPI_EVENT_RAID_RC_SMART_DATA 0x0A
504#define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED 0x0B
505
506/*
507 * SAS Phy link down event data
508 */
509typedef struct event_data_sas_phy_link_status {
510 uint8_t PhyNum;
511 uint8_t LinkRates;
512 uint16_t DevHandle;
513 uint64_t SASAddress;
514} event_data_sas_phy_link_status_t;
515
516#define MPI_EVENT_SAS_PLS_LR_CURRENT_MASK 0xF0
517#define MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT 4
518#define MPI_EVENT_SAS_PLS_LR_PREVIOUS_MASK 0x0F
519#define MPI_EVENT_SAS_PLS_LR_PREVIOUS_SHIFT 0
520#define MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN 0x00
521#define MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED 0x01
522#define MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION 0x02
523#define MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE 0x03
524#define MPI_EVENT_SAS_PLS_LR_RATE_1_5 0x08
525#define MPI_EVENT_SAS_PLS_LR_RATE_3_0 0x09
526
527/*
528 * Firmware Load Messages
529 */
530
531/*
532 * Firmware download message and associated structures
533 */
534typedef struct msg_fw_download {
535 uint8_t ImageType;
536 uint8_t Reserved;
537 uint8_t ChainOffset;
538 uint8_t Function;
539 uint8_t Reserved1[3];
540 uint8_t MsgFlags;
541 uint32_t MsgContext;
542 sge_mpi_union_t SGL;
543} msg_fw_download_t;
544
545#define MPI_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT 0x01
546
547#define MPI_FW_DOWNLOAD_ITYPE_RESERVED 0x00
548#define MPI_FW_DOWNLOAD_ITYPE_FW 0x01
549#define MPI_FW_DOWNLOAD_ITYPE_BIOS 0x02
550#define MPI_FW_DOWNLOAD_ITYPE_NVDATA 0x03
551#define MPI_FW_DOWNLOAD_ITYPE_BOOTLOADER 0x04
552
553typedef struct fw_download_tcsge {
554 uint8_t Reserved;
555 uint8_t ContextSize;
556 uint8_t DetailsLength;
557 uint8_t Flags;
558 uint32_t Reserved_0100_Checksum; /* obsolete */
559 uint32_t ImageOffset;
560 uint32_t ImageSize;
561} fw_download_tcsge_t;
562
563typedef struct msg_fw_download_reply {
564 uint8_t ImageType;
565 uint8_t Reserved;
566 uint8_t MsgLength;
567 uint8_t Function;
568 uint8_t Reserved1[3];
569 uint8_t MsgFlags;
570 uint32_t MsgContext;
571 uint16_t Reserved2;
572 uint16_t IOCStatus;
573 uint32_t IOCLogInfo;
574} msg_fw_download_reply_t;
575
576/*
577 * Firmware upload messages and associated structures
578 */
579typedef struct msg_fw_upload {
580 uint8_t ImageType;
581 uint8_t Reserved;
582 uint8_t ChainOffset;
583 uint8_t Function;
584 uint8_t Reserved1[3];
585 uint8_t MsgFlags;
586 uint32_t MsgContext;
587 sge_mpi_union_t SGL;
588} msg_fw_upload_t;
589
590#define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM 0x00
591#define MPI_FW_UPLOAD_ITYPE_FW_FLASH 0x01
592#define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH 0x02
593#define MPI_FW_UPLOAD_ITYPE_NVDATA 0x03
594#define MPI_FW_UPLOAD_ITYPE_BOOTLOADER 0x04
595
596typedef struct fw_upload_tcsge {
597 uint8_t Reserved;
598 uint8_t ContextSize;
599 uint8_t DetailsLength;
600 uint8_t Flags;
601 uint32_t Reserved1;
602 uint32_t ImageOffset;
603 uint32_t ImageSize;
604} fw_upload_tcsge_t;
605
606typedef struct msg_fw_upload_reply {
607 uint8_t ImageType;
608 uint8_t Reserved;
609 uint8_t MsgLength;
610 uint8_t Function;
611 uint8_t Reserved1[3];
612 uint8_t MsgFlags;
613 uint32_t MsgContext;
614 uint16_t Reserved2;
615 uint16_t IOCStatus;
616 uint32_t IOCLogInfo;
617 uint32_t ActualImageSize;
618} msg_fw_upload_reply_t;
619
620typedef struct msg_fw_header {
621 uint32_t ArmBranchInstruction0;
622 uint32_t Signature0;
623 uint32_t Signature1;
624 uint32_t Signature2;
625 uint32_t ArmBranchInstruction1;
626 uint32_t ArmBranchInstruction2;
627 uint32_t Reserved;
628 uint32_t Checksum;
629 uint16_t VendorId;
630 uint16_t ProductId;
631 mpi_fw_version_t FWVersion;
632 uint32_t SeqCodeVersion;
633 uint32_t ImageSize;
634 uint32_t NextImageHeaderOffset;
635 uint32_t LoadStartAddress;
636 uint32_t IopResetVectorValue;
637 uint32_t IopResetRegAddr;
638 uint32_t VersionNameWhat;
639 uint8_t VersionName[32];
640 uint32_t VendorNameWhat;
641 uint8_t VendorName[32];
642} msg_fw_header_t;
643
644#define MPI_FW_HEADER_WHAT_SIGNATURE 0x29232840
645
646/* defines for using the ProductId field */
647#define MPI_FW_HEADER_PID_TYPE_MASK 0xF000
648#define MPI_FW_HEADER_PID_TYPE_SCSI 0x0000
649#define MPI_FW_HEADER_PID_TYPE_FC 0x1000
650
651#define MPI_FW_HEADER_PID_PROD_MASK 0x0F00
652#define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI 0x0100
653#define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI 0x0200
654#define MPI_FW_HEADER_PID_PROD_TARGET_SCSI 0x0300
655#define MPI_FW_HEADER_PID_PROD_IM_SCSI 0x0400
656#define MPI_FW_HEADER_PID_PROD_IS_SCSI 0x0500
657#define MPI_FW_HEADER_PID_PROD_CTX_SCSI 0x0600
658#define MPI_FW_HEADER_PID_PROD_IR_SCSI 0x0700
659
660#define MPI_FW_HEADER_PID_FAMILY_MASK 0x00FF
661#define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI 0x0001
662#define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI 0x0002
663#define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI 0x0003
664#define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI 0x0004
665#define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI 0x0005
666#define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI 0x0006
667#define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI 0x0007
668#define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI 0x0008
669#define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI 0x0009
670#define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI 0x000A
671#define MPI_FW_HEADER_PID_FAMILY_909_FC 0x0000
672#define MPI_FW_HEADER_PID_FAMILY_919_FC 0x0001
673#define MPI_FW_HEADER_PID_FAMILY_919X_FC 0x0002
674#define MPI_FW_HEADER_PID_FAMILY_1064_SAS 0x0001
675#define MPI_FW_HEADER_PID_FAMILY_1068_SAS 0x0002
676#define MPI_FW_HEADER_PID_FAMILY_1078_SAS 0x0003
677
678typedef struct mpi_ext_image_header {
679 uint8_t ImageType;
680 uint8_t Reserved;
681 uint16_t Reserved1;
682 uint32_t Checksum;
683 uint32_t ImageSize;
684 uint32_t NextImageHeaderOffset;
685 uint32_t LoadStartAddress;
686 uint32_t Reserved2;
687} mpi_ext_image_header_t;
688
689#define MPI_EXT_IMAGE_TYPE_UNSPECIFIED 0x00
690#define MPI_EXT_IMAGE_TYPE_FW 0x01
691#define MPI_EXT_IMAGE_TYPE_NVDATA 0x03
692#define MPI_EXT_IMAGE_TYPE_BOOTLOADER 0x04
693
694#ifdef __cplusplus
695}
696#endif
697
698#endif /* _SYS_MPI_IOC_H */
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