| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * Hypervisor Software File: ncu.h |
| 5 | * |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 7 | * |
| 8 | * - Do no alter or remove copyright notices |
| 9 | * |
| 10 | * - Redistribution and use of this software in source and binary forms, with |
| 11 | * or without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistribution of source code must retain the above copyright notice, |
| 15 | * this list of conditions and the following disclaimer. |
| 16 | * |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, |
| 18 | * this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors |
| 22 | * may be used to endorse or promote products derived from this software |
| 23 | * without specific prior written permission. |
| 24 | * |
| 25 | * This software is provided "AS IS," without a warranty of any kind. |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| 37 | * |
| 38 | * You acknowledge that this software is not designed, licensed or |
| 39 | * intended for use in the design, construction, operation or maintenance of |
| 40 | * any nuclear facility. |
| 41 | * |
| 42 | * ========== Copyright Header End ============================================ |
| 43 | */ |
| 44 | /* |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 46 | * Use is subject to license terms. |
| 47 | */ |
| 48 | |
| 49 | #ifndef _HURON_NCU_H |
| 50 | #define _HURON_NCU_H |
| 51 | |
| 52 | #pragma ident "@(#)ncu.h 1.2 07/07/25 SMI" |
| 53 | |
| 54 | #ifdef __cplusplus |
| 55 | extern "C" { |
| 56 | #endif |
| 57 | |
| 58 | #include <cmp.h> |
| 59 | |
| 60 | /* |
| 61 | * Niagara2 Non-Cacheable Unit definitions |
| 62 | */ |
| 63 | #define NCU_BASE 0x8000000000 |
| 64 | #define MONDO_INT_VEC 0xa00 |
| 65 | |
| 66 | #define NCUINT 0x8000040000 |
| 67 | #define MONDO_INT_BUSY 0x800 /* step 8 count 64 */ |
| 68 | #define MONDO_INT_ABUSY 0xa00 /* aliased to the current strands */ |
| 69 | |
| 70 | #define MONDO_INT_BUSY_BUSY (1 << 6) |
| 71 | #define MONDO_INT_ADATA0 0x400 |
| 72 | #define MONDO_INT_ADATA1 0x600 |
| 73 | |
| 74 | #define PROC_SER_NUM 0x1000 |
| 75 | /* |
| 76 | * Interrupt Management |
| 77 | */ |
| 78 | #define INT_MAN (0x0) |
| 79 | #define INT_MAN_BASE (NCU_BASE + INT_MAN) |
| 80 | #define INT_MAN_REGISTERS 128 /* number of INT MAN registers */ |
| 81 | #define INT_MAN_STEP (8) |
| 82 | #define INT_MAN_SHIFT (3) /* log2(INT_MAN_STEP) */ |
| 83 | #define INT_MAN_DEV_OFF(dev) ((dev) * INT_MAN_STEP) |
| 84 | #define INT_CTL_DEV_OFF(dev) ((dev) * INT_MAN_STEP) |
| 85 | |
| 86 | /* |
| 87 | * NCU internal device ids |
| 88 | */ |
| 89 | #define NCUDEV_SSIERR 1 /* Used for errors */ |
| 90 | #define NCUDEV_SSI 2 /* SSI interrupt from EXT_INT_L pin */ |
| 91 | /* NIU device ids are 64 + logical device number */ |
| 92 | |
| 93 | #define DEV_SSI NCUDEV_SSI |
| 94 | |
| 95 | /* |
| 96 | * INT_MAN Register |
| 97 | */ |
| 98 | #define INT_MAN_CPU_SHIFT 8 |
| 99 | #define INT_MAN_CPU_MASK 0x3f |
| 100 | #define INT_MAN_VEC_MASK 0x3f |
| 101 | |
| 102 | |
| 103 | /* |
| 104 | * some vector dispatch priorities |
| 105 | * |
| 106 | * N.B. some of the "remaining" vector dispatch priorities 0..35 are |
| 107 | * reserved for NIU devices. These aren't really priorities more at |
| 108 | * identifiers. |
| 109 | */ |
| 110 | #define VECINTR_CPUINERR 63 /* not used */ |
| 111 | #define VECINTR_ERROR_XCALL 62 |
| 112 | #define VECINTR_XCALL 61 |
| 113 | #define VECINTR_SSIERR 60 |
| 114 | #define VECINTR_DEV 59 |
| 115 | #define VECINTR_VDEV 58 |
| 116 | #define VECINTR_HVXCALL 57 |
| 117 | #define VECINTR_FPGA 36 /* not used */ |
| 118 | #define VECINTR_NIU_HI 35 |
| 119 | #define VECINTR_NIU_LO 0 |
| 120 | |
| 121 | /* BEGIN CSTYLED */ |
| 122 | #define FPGA_MBOX_INT_DISABLE(x, scr1, scr2) \ |
| 123 | setx FPGA_INTR_BASE, scr1, scr2 ;\ |
| 124 | mov x, scr1 ;\ |
| 125 | stb scr1, [scr2 + FPGA_MBOX_INTR_DISABLE] |
| 126 | |
| 127 | #define CLEAR_INT_CTL_PEND(scr1, scr2) |
| 128 | |
| 129 | /* END CSTYLED */ |
| 130 | |
| 131 | /* |
| 132 | * Reset Unit |
| 133 | */ |
| 134 | #define SUBSYS_RESET 0x8900000838 |
| 135 | #define RESET_NIU (1 << 0) |
| 136 | |
| 137 | #ifdef __cplusplus |
| 138 | } |
| 139 | #endif |
| 140 | |
| 141 | #endif /* _HURON_NCU_H */ |