| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * Hypervisor Software File: dram.h |
| 5 | * |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 7 | * |
| 8 | * - Do no alter or remove copyright notices |
| 9 | * |
| 10 | * - Redistribution and use of this software in source and binary forms, with |
| 11 | * or without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistribution of source code must retain the above copyright notice, |
| 15 | * this list of conditions and the following disclaimer. |
| 16 | * |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, |
| 18 | * this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors |
| 22 | * may be used to endorse or promote products derived from this software |
| 23 | * without specific prior written permission. |
| 24 | * |
| 25 | * This software is provided "AS IS," without a warranty of any kind. |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| 37 | * |
| 38 | * You acknowledge that this software is not designed, licensed or |
| 39 | * intended for use in the design, construction, operation or maintenance of |
| 40 | * any nuclear facility. |
| 41 | * |
| 42 | * ========== Copyright Header End ============================================ |
| 43 | */ |
| 44 | /* |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 46 | * Use is subject to license terms. |
| 47 | */ |
| 48 | |
| 49 | #ifndef _PLATFORM_DRAM_H |
| 50 | #define _PLATFORM_DRAM_H |
| 51 | |
| 52 | #pragma ident "@(#)dram.h 1.2 07/06/20 SMI" |
| 53 | |
| 54 | /* |
| 55 | * Niagara2 DRAM definitions |
| 56 | */ |
| 57 | |
| 58 | #ifdef __cplusplus |
| 59 | extern "C" { |
| 60 | #endif |
| 61 | |
| 62 | #define DRAM_BASE (0x84 << 32) |
| 63 | #define DRAM_ERROR_RETRY_REG 0x2a8 |
| 64 | #define DRAM_ERROR_FBD_SYNDROME_REG 0xc00 |
| 65 | #define DRAM_ERROR_FBD_COUNTER_REG 0xc10 |
| 66 | |
| 67 | #define DRAM_ESR_ERROR_SHIFT 54 /* first error bit set */ |
| 68 | |
| 69 | #define DRAM_ESR_MEU (1 << 63) |
| 70 | #define DRAM_ESR_MEC (1 << 62) |
| 71 | #define DRAM_ESR_DAC (1 << 61) |
| 72 | #define DRAM_ESR_DAU (1 << 60) |
| 73 | #define DRAM_ESR_DSC (1 << 59) |
| 74 | #define DRAM_ESR_DSU (1 << 58) |
| 75 | #define DRAM_ESR_DBU (1 << 57) |
| 76 | #define DRAM_ESR_MEB (1 << 56) |
| 77 | #define DRAM_ESR_FBU (1 << 55) |
| 78 | #define DRAM_ESR_FBR (1 << 54) |
| 79 | |
| 80 | /* |
| 81 | * DRAM Error Retry Register (count 4 Step 4096) |
| 82 | */ |
| 83 | #define DRAM_RETRY_OFFSET DRAM_ERROR_RETRY_REG |
| 84 | #define DRAM_RETRY_BASE (DRAM_BASE + DRAM_RETRY_OFFSET) |
| 85 | |
| 86 | /* |
| 87 | * DRAM FBD Error Syndrome Register (count 4 Step 4096) |
| 88 | */ |
| 89 | #define DRAM_FBD_OFFSET DRAM_ERROR_FBD_SYNDROME_REG |
| 90 | #define DRAM_FBD_BASE (DRAM_BASE + DRAM_FBD_OFFSET) |
| 91 | |
| 92 | /* |
| 93 | * DRAM FBR Error Counter Register (count 4 Step 4096) |
| 94 | */ |
| 95 | #define DRAM_FBR_COUNT_OFFSET DRAM_ERROR_FBD_COUNTER_REG |
| 96 | #define DRAM_FBR_COUNT_BASE (DRAM_BASE + DRAM_FBR_COUNT_OFFSET) |
| 97 | |
| 98 | /* BEGIN CSTYLED */ |
| 99 | #define SKIP_DISABLED_DRAM_BANK(bank, reg1, reg2, skip_label) \ |
| 100 | setx L2_BANK_ENABLE_STATUS, reg1, reg2 ;\ |
| 101 | ldx [reg2], reg2 ;\ |
| 102 | srlx reg2, L2_BANK_ENABLE_STATUS_SHIFT, reg2 ;\ |
| 103 | and reg2, L2_BANK_ENABLE_STATUS_MASK, reg2 ;\ |
| 104 | or %g0, bank, reg1 ;\ |
| 105 | srlx reg2, reg1, reg2 ;\ |
| 106 | btst 1, reg2 ;\ |
| 107 | bz,pn %xcc, skip_label ;\ |
| 108 | nop ;\ |
| 109 | setx DRAM_BASE, reg1, reg2 ;\ |
| 110 | or reg2, DRAM_CHANNEL_DISABLE_REG, reg2 ;\ |
| 111 | mov bank, reg1 ;\ |
| 112 | sllx reg1, DRAM_BANK_SHIFT, reg1 ;\ |
| 113 | or reg2, reg1, reg2 ;\ |
| 114 | ldx [reg2], reg1 ;\ |
| 115 | brnz,pn reg1, skip_label ;\ |
| 116 | nop |
| 117 | |
| 118 | #define DRAM_SNGL_CHNL_MODE_REG 0x148 |
| 119 | #define DRAM_SNGL_CHNL_MODE_BASE (DRAM_BASE + DRAM_SNGL_CHNL_MODE_REG) |
| 120 | #define DRAM_DIMM_PRESENT_BASE (DRAM_BASE + DRAM_DIMM_PRESENT_REG) |
| 121 | |
| 122 | #define CONFIG_REG_ACC_ADDR_REG 0x900 |
| 123 | #define CONFIG_REG_ACC_DATA_REG 0x908 |
| 124 | |
| 125 | #define DRAM_CONFIG_REG_ACC_ADDR_BASE (DRAM_BASE + CONFIG_REG_ACC_ADDR_REG) |
| 126 | #define DRAM_CONFIG_REG_ACC_DATA_BASE (DRAM_BASE + CONFIG_REG_ACC_DATA_REG) |
| 127 | |
| 128 | #define DRAM_FBDIMM_FERR 0x90 |
| 129 | #define DRAM_FBDIMM_NERR 0x94 |
| 130 | |
| 131 | /* CONFIG_REG_ACCESS_ADDR_REG bit positions */ |
| 132 | #define CONFIG_ADDR_AMB_POS 11 |
| 133 | #define CONFIG_ADDR_CH_POS 15 |
| 134 | #define CONFIG_FUNCTION_SHIFT 8 |
| 135 | #define CONFIG_FUNCTION_FBD 1 |
| 136 | |
| 137 | /* END CSTYLED */ |
| 138 | #ifdef __cplusplus |
| 139 | } |
| 140 | #endif |
| 141 | |
| 142 | #endif /* _PLATFORM_DRAM_H */ |