| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: sparcv9decode.c |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 7 | * |
| 8 | * The above named program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public |
| 10 | * License version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * The above named program is distributed in the hope that it will be |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public |
| 18 | * License along with this work; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 20 | * |
| 21 | * ========== Copyright Header End ============================================ |
| 22 | */ |
| 23 | /* |
| 24 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 25 | * Use is subject to license terms. |
| 26 | */ |
| 27 | |
| 28 | #pragma ident "@(#)sparcv9decode.c 1.69 07/03/19 SMI" |
| 29 | |
| 30 | #include <stdio.h> |
| 31 | #include <stdlib.h> |
| 32 | #include <ctype.h> |
| 33 | #include <unistd.h> |
| 34 | #include <sys/types.h> |
| 35 | |
| 36 | #include <assert.h> |
| 37 | |
| 38 | #include "basics.h" |
| 39 | #include "fatal.h" |
| 40 | #include "simcore.h" |
| 41 | #include "config.h" |
| 42 | #include "xicache.h" |
| 43 | #include "tsparcv9.h" |
| 44 | #include "tsparcv9internal.h" |
| 45 | #include "sparcv9decode.h" |
| 46 | #include "breakpoint.h" |
| 47 | |
| 48 | #include "hostnative_asm.h" /* autogenerated from hostnative_asm.S */ |
| 49 | #include "hostnative.h" /* autogenerated from hostnative.c */ |
| 50 | |
| 51 | #include "execinstns.h" /* autogenerated core defined instructions */ |
| 52 | #include "sparcv9instns.h" /* autogenerated sparcv9 instruction definitions */ |
| 53 | |
| 54 | |
| 55 | |
| 56 | static char * v9_illegal_reason_str[]={ |
| 57 | "illegal_instruction", |
| 58 | "unknown_instruction", |
| 59 | "unknown_fp_instruction", |
| 60 | "bpcc_illegal_cc_specifier", |
| 61 | "bpr_illegal_cc_specifier", |
| 62 | "done_retry_illegal_fcn_field", |
| 63 | "saved_fcn_invalid", |
| 64 | "saved_reserved_field_non_zero", |
| 65 | "tcc_reserved_field_non_zero", |
| 66 | "tcc_illegal_cc_field", |
| 67 | "movcc_reserved_field_non_zero", |
| 68 | "movcc_illegal_cc_field", |
| 69 | "movr_illegal_cc_field", |
| 70 | "odd_rd_for_ldd", |
| 71 | "odd_rd_for_std", |
| 72 | "fpop_bit13_set", |
| 73 | "illegal_fsr_specifier", |
| 74 | "unimplemented_visop", |
| 75 | "illtrap_reserved_field_non_zero", |
| 76 | "fmovcc_reserved_field_non_zero", |
| 77 | "fmovcc_illegal_cc_field", |
| 78 | "flushw_reserved_field_non_zero", |
| 79 | "visop36_reserved_field_non_zero", |
| 80 | "sir_reserved_field_non_zero", |
| 81 | "cas_reserved_field_non_zero", |
| 82 | "misc_reserved_field_non_zero" |
| 83 | }; |
| 84 | |
| 85 | |
| 86 | #ifdef FP_DECODE_DISABLED |
| 87 | #define FP_DECODE_FPU_ON_CHECK \ |
| 88 | if (!((sparcv9_cpu_t*)(sp->specificp))->fpu_on) goto fp_disabled |
| 89 | #else /* FP_DECODE_DISABLED */ |
| 90 | #define FP_DECODE_FPU_ON_CHECK |
| 91 | #endif /* FP_DECODE_DISABLED */ |
| 92 | |
| 93 | |
| 94 | void sparcv9_decode_me(simcpu_t *sp, xicache_instn_t * xcip) |
| 95 | { |
| 96 | int rs1, rd, rs2; |
| 97 | void (*exec_funcp)(simcpu_t *sp, xicache_instn_t * xcip); |
| 98 | void (*p_exec_funcp)(simcpu_t *sp, xicache_instn_t * xcip); |
| 99 | sint32_t simm; |
| 100 | uint32_t uimm; |
| 101 | T0o3_code_t op0c; |
| 102 | T2o3_code_t op2c; |
| 103 | T3o3_code_t op3c; |
| 104 | uint64_t tmp; |
| 105 | bool_t on_bp; |
| 106 | uint32_t instn; |
| 107 | |
| 108 | |
| 109 | XIC_MISS(sp); |
| 110 | on_bp = false; |
| 111 | |
| 112 | /* |
| 113 | * Very first step .... check to see if breakpoint |
| 114 | * reached. If true, install breakpoint catcher instead |
| 115 | * of a decoded instruction .... |
| 116 | * ... if there is a match, we still decode the instruction, |
| 117 | * but replace the actual instruction operation with a trampoline |
| 118 | * the instruction operation is then encoded into the |
| 119 | * breakpoint itself. |
| 120 | * |
| 121 | * FIXME : for the time being because of the hassles of flushing the |
| 122 | * x-cache, we dont install a trampoline .. we leave the decoded func |
| 123 | * as decode_me and pay the penalty .... this way we can track the |
| 124 | * breakpoint progress for the time being. |
| 125 | * Also means we don't have to have the decoded instn in the breakpoint |
| 126 | * either .... |
| 127 | * |
| 128 | * OK: So if we match an active breakpoint, we *must* always leave the |
| 129 | * decoded function as *_decode_me. Asside from this whether or |
| 130 | * not we execute the *real* decoded instruction depends on whether or |
| 131 | * not the breakpoint is being executed for the first time, or this |
| 132 | * is the first instruction after that breakpoint being taken ! |
| 133 | */ |
| 134 | |
| 135 | if (sp->bp_infop != NULL) { |
| 136 | breakpoint_t *bp; |
| 137 | |
| 138 | switch (breakpoint_check(sp->bp_infop, sp->pc, DEFAULT_BP_CONTEXT /* FIXME */, &bp)) { |
| 139 | case ON_BREAKPOINT: |
| 140 | if (bp == NULL /* "next" breakpoint */ |
| 141 | || bp->first_strike == false) { |
| 142 | /* just stop if we really want to break */ |
| 143 | if (bp != NULL) |
| 144 | bp->first_strike = true; |
| 145 | simcore_stop(); |
| 146 | return; |
| 147 | } else { |
| 148 | /* if not, continue the decode, but don't install the function */ |
| 149 | bp->first_strike = false; |
| 150 | on_bp = true; |
| 151 | } |
| 152 | break; |
| 153 | case NOTHING: |
| 154 | break; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | /* |
| 159 | * For sparcv9, to save us time an undecoded instruction is |
| 160 | * saved as a bit pattern in the xicache ... |
| 161 | * ... saves us a second v-to-p conversion so we can read memory |
| 162 | */ |
| 163 | instn = xcip->rawi; |
| 164 | |
| 165 | /* |
| 166 | * Decoder is designed for a big endian instn encoding. |
| 167 | * So to make life simpler on a little endian host, reverse the byte order |
| 168 | * and then treat as big endian. |
| 169 | */ |
| 170 | instn = FE_INSTN(instn); |
| 171 | |
| 172 | /* |
| 173 | * Now go about the legitimate instruction decoding |
| 174 | */ |
| 175 | |
| 176 | switch ((ty_code_t)X_OP(instn)) { |
| 177 | case Ty_0: |
| 178 | op0c = (T0o3_code_t)X_OP2(instn); |
| 179 | |
| 180 | switch (op0c) { |
| 181 | sint32_t br_offset; |
| 182 | bool_t annul_bit; |
| 183 | |
| 184 | case T0o3_Bicc: |
| 185 | /* Deprecated integer condition code branches */ |
| 186 | |
| 187 | br_offset = X_FMT2_DISP22(instn); |
| 188 | br_offset = ((br_offset << 10) >> 8); /* sign extend to 32bits */ |
| 189 | annul_bit = X_ANNUL_BIT(instn); |
| 190 | |
| 191 | bpcc_entry:; |
| 192 | SET_OP_BROFF32(br_offset); |
| 193 | |
| 194 | switch ((bcc_type_t)X_COND(instn)) { |
| 195 | case Bcc_a: |
| 196 | bicc_ba:; |
| 197 | if (annul_bit) { |
| 198 | SET_OPv9(bralways_ds_annul); |
| 199 | } else { |
| 200 | SET_OPv9(bralways_ds); |
| 201 | } |
| 202 | goto all_done; |
| 203 | |
| 204 | case Bcc_n: |
| 205 | bicc_bn:; |
| 206 | if (!annul_bit) goto do_noop; |
| 207 | SET_OPv9(brnever_ds_annul); |
| 208 | goto all_done; |
| 209 | |
| 210 | #define BR_DECODE(_cc, _type) \ |
| 211 | case Bcc_##_type: \ |
| 212 | if (annul_bit) { \ |
| 213 | SET_OPv9(b##_type##_##_cc##_an); \ |
| 214 | } else { \ |
| 215 | SET_OPv9(b##_type##_##_cc); \ |
| 216 | } \ |
| 217 | break |
| 218 | BR_DECODE(icc, ne); |
| 219 | BR_DECODE(icc, e); |
| 220 | BR_DECODE(icc, g); |
| 221 | BR_DECODE(icc, le); |
| 222 | BR_DECODE(icc, ge); |
| 223 | BR_DECODE(icc, l); |
| 224 | BR_DECODE(icc, gu); |
| 225 | BR_DECODE(icc, leu); |
| 226 | BR_DECODE(icc, cc); |
| 227 | BR_DECODE(icc, cs); |
| 228 | BR_DECODE(icc, pos); |
| 229 | BR_DECODE(icc, neg); |
| 230 | BR_DECODE(icc, vc); |
| 231 | BR_DECODE(icc, vs); |
| 232 | } |
| 233 | |
| 234 | goto all_done; |
| 235 | |
| 236 | case T0o3_BPcc: |
| 237 | br_offset = X_FMT2_DISP19(instn); |
| 238 | br_offset = ((br_offset << 13) >> 11); /* sign extend */ |
| 239 | annul_bit = X_ANNUL_BIT(instn); |
| 240 | |
| 241 | /* v9 Predicted integer condition code branches */ |
| 242 | switch( (cc2bit_t)X_FMT2_CC(instn)) { |
| 243 | case CC2bit_icc: |
| 244 | goto bpcc_entry; |
| 245 | |
| 246 | case CC2bit_xcc: |
| 247 | break; |
| 248 | |
| 249 | default: |
| 250 | /* defined as illegal - rather than unknown */ |
| 251 | SET_OP_ILL_REASON(bpcc_illegal_cc_specifier); |
| 252 | goto illegal_instruction; |
| 253 | } |
| 254 | |
| 255 | /* Only xcc bpcc forms here ... */ |
| 256 | SET_OP_BROFF32(br_offset); |
| 257 | |
| 258 | switch ((bcc_type_t)X_COND(instn)) { |
| 259 | case Bcc_a: goto bicc_ba; |
| 260 | case Bcc_n: goto bicc_bn; |
| 261 | |
| 262 | BR_DECODE(xcc, ne); |
| 263 | BR_DECODE(xcc, e); |
| 264 | BR_DECODE(xcc, g); |
| 265 | BR_DECODE(xcc, le); |
| 266 | BR_DECODE(xcc, ge); |
| 267 | BR_DECODE(xcc, l); |
| 268 | BR_DECODE(xcc, gu); |
| 269 | BR_DECODE(xcc, leu); |
| 270 | BR_DECODE(xcc, cc); |
| 271 | BR_DECODE(xcc, cs); |
| 272 | BR_DECODE(xcc, pos); |
| 273 | BR_DECODE(xcc, neg); |
| 274 | BR_DECODE(xcc, vc); |
| 275 | BR_DECODE(xcc, vs); |
| 276 | } |
| 277 | |
| 278 | goto all_done; |
| 279 | |
| 280 | case T0o3_SetHi: |
| 281 | rd = X_RD(instn); |
| 282 | if (rd == 0) goto do_noop; |
| 283 | uimm = (instn & 0x3FFFFF) << 10; |
| 284 | SET_OP( move_uimm ); |
| 285 | SET_OP_RD(rd); |
| 286 | SET_OP_UIMM32(uimm); |
| 287 | goto all_done; |
| 288 | |
| 289 | case T0o3_Illtrap: |
| 290 | if (!CHECK_RESERVED_ZERO(instn, 29, 25)) { |
| 291 | SET_OP_ILL_REASON(illtrap_reserved_field_non_zero); |
| 292 | goto illegal_instruction; |
| 293 | } |
| 294 | SET_OPv9(illtrap); |
| 295 | /* capture const22 */ |
| 296 | SET_OP_UIMM32((instn & 0x3FFFFF)); |
| 297 | goto all_done; |
| 298 | |
| 299 | case T0o3_BPr: |
| 300 | |
| 301 | rs1 = X_RS1(instn); |
| 302 | br_offset = X_FMT2_DISP16(instn); |
| 303 | br_offset = ((br_offset << 16) >> 14); /* sign extend to 32bits & scale by 4*/ |
| 304 | annul_bit = X_ANNUL_BIT(instn); |
| 305 | |
| 306 | SET_OP_BREGOFF32(br_offset); |
| 307 | SET_OP_RS1(rs1); |
| 308 | |
| 309 | #define BREG_DECODE(_type, _an) \ |
| 310 | case RCond_##_type: \ |
| 311 | SET_OPv9(br##_type##_an); \ |
| 312 | goto all_done |
| 313 | |
| 314 | if (annul_bit) { |
| 315 | switch ((rcond_type_t)X_RCOND(instn)) { |
| 316 | BREG_DECODE(z,_an); |
| 317 | BREG_DECODE(lez,_an); |
| 318 | BREG_DECODE(lz,_an); |
| 319 | BREG_DECODE(nz,_an); |
| 320 | BREG_DECODE(gz,_an); |
| 321 | BREG_DECODE(gez,_an); |
| 322 | default: |
| 323 | break; |
| 324 | } |
| 325 | SET_OP_ILL_REASON(bpr_illegal_cc_specifier); |
| 326 | goto illegal_instruction; |
| 327 | } |
| 328 | |
| 329 | switch ((rcond_type_t)X_RCOND(instn)) { |
| 330 | BREG_DECODE(z,); |
| 331 | BREG_DECODE(lez,); |
| 332 | BREG_DECODE(lz,); |
| 333 | BREG_DECODE(nz,); |
| 334 | BREG_DECODE(gz,); |
| 335 | BREG_DECODE(gez,); |
| 336 | default: |
| 337 | break; |
| 338 | } |
| 339 | SET_OP_ILL_REASON(bpr_illegal_cc_specifier); |
| 340 | goto illegal_instruction; |
| 341 | |
| 342 | #undef BREG_DECODE |
| 343 | |
| 344 | case T0o3_FBfcc: |
| 345 | FP_DECODE_FPU_ON_CHECK; |
| 346 | /* Deprecated floating condition code branches */ |
| 347 | |
| 348 | br_offset = X_FMT2_DISP22(instn); |
| 349 | br_offset = ((br_offset << 10) >> 8); /* sign extend to 32bits */ |
| 350 | annul_bit = X_ANNUL_BIT(instn); |
| 351 | SET_OP_BR_FCC(0); |
| 352 | |
| 353 | fbpcc_entry:; |
| 354 | SET_OP_BROFF32(br_offset); |
| 355 | |
| 356 | switch ((bcc_type_t)X_COND(instn)) { |
| 357 | case FBcc_a: |
| 358 | fbicc_ba:; |
| 359 | if (annul_bit) { |
| 360 | SET_OPv9(bralways_ds_annul); |
| 361 | } else { |
| 362 | SET_OPv9(bralways_ds); |
| 363 | } |
| 364 | goto all_done; |
| 365 | |
| 366 | case FBcc_n: |
| 367 | fbicc_bn:; |
| 368 | if (!annul_bit) goto do_noop; |
| 369 | SET_OPv9(brnever_ds_annul); |
| 370 | goto all_done; |
| 371 | |
| 372 | #define FBR_DECODE(_cc, _type) \ |
| 373 | case FBcc_##_type: \ |
| 374 | if (annul_bit) { \ |
| 375 | SET_OPv9(fb##_type##_##_cc##_an); \ |
| 376 | } else { \ |
| 377 | SET_OPv9(fb##_type##_##_cc); \ |
| 378 | } \ |
| 379 | break |
| 380 | FBR_DECODE(fcc0, e); |
| 381 | FBR_DECODE(fcc0, ne); |
| 382 | FBR_DECODE(fcc0, ue); |
| 383 | FBR_DECODE(fcc0, lg); |
| 384 | FBR_DECODE(fcc0, ge); |
| 385 | FBR_DECODE(fcc0, ul); |
| 386 | FBR_DECODE(fcc0, uge); |
| 387 | FBR_DECODE(fcc0, l); |
| 388 | FBR_DECODE(fcc0, le); |
| 389 | FBR_DECODE(fcc0, ug); |
| 390 | FBR_DECODE(fcc0, ule); |
| 391 | FBR_DECODE(fcc0, g); |
| 392 | FBR_DECODE(fcc0, o); |
| 393 | FBR_DECODE(fcc0, u); |
| 394 | } |
| 395 | |
| 396 | goto all_done; |
| 397 | |
| 398 | case T0o3_FBPfcc: |
| 399 | FP_DECODE_FPU_ON_CHECK; |
| 400 | br_offset = X_FMT2_DISP19(instn); |
| 401 | br_offset = ((br_offset << 13) >> 11); /* sign extend */ |
| 402 | annul_bit = X_ANNUL_BIT(instn); |
| 403 | |
| 404 | /* v9 Predicted floating condition code branches */ |
| 405 | SET_OP_BR_FCC(X_FMT2_CC(instn)); |
| 406 | switch( (fcc2bit_t)X_FMT2_CC(instn)) { |
| 407 | case FCC2bit_fcc0: |
| 408 | goto fbpcc_entry; |
| 409 | |
| 410 | } |
| 411 | |
| 412 | /* Only fcc1-3 bpcc forms here ... */ |
| 413 | SET_OP_BROFF32(br_offset); |
| 414 | |
| 415 | switch ((bcc_type_t)X_COND(instn)) { |
| 416 | case FBcc_a: goto fbicc_ba; |
| 417 | case FBcc_n: goto fbicc_bn; |
| 418 | |
| 419 | FBR_DECODE(fccN, e); |
| 420 | FBR_DECODE(fccN, ne); |
| 421 | FBR_DECODE(fccN, ue); |
| 422 | FBR_DECODE(fccN, lg); |
| 423 | FBR_DECODE(fccN, ge); |
| 424 | FBR_DECODE(fccN, ul); |
| 425 | FBR_DECODE(fccN, uge); |
| 426 | FBR_DECODE(fccN, l); |
| 427 | FBR_DECODE(fccN, le); |
| 428 | FBR_DECODE(fccN, ug); |
| 429 | FBR_DECODE(fccN, ule); |
| 430 | FBR_DECODE(fccN, g); |
| 431 | FBR_DECODE(fccN, o); |
| 432 | FBR_DECODE(fccN, u); |
| 433 | } |
| 434 | |
| 435 | goto all_done; |
| 436 | |
| 437 | default: |
| 438 | break; |
| 439 | } |
| 440 | |
| 441 | goto unknown_decode; |
| 442 | |
| 443 | case Ty_1: /* Call instruction only */ |
| 444 | |
| 445 | { |
| 446 | sint32_t offset; |
| 447 | offset = X_FMT1_DISP30(instn) << 2; /* shift to be address relative */ |
| 448 | SET_OP_SIMM32( offset ); |
| 449 | SET_OPv9(call); |
| 450 | goto all_done; |
| 451 | } |
| 452 | |
| 453 | case Ty_2: |
| 454 | |
| 455 | rs1 = X_RS1(instn); |
| 456 | rd = X_RD(instn); |
| 457 | op2c = (T2o3_code_t)X_OP3(instn); |
| 458 | |
| 459 | if (X_I(instn)) { |
| 460 | simm = X_SIMM13(instn); |
| 461 | |
| 462 | /* register x immediate -> register forms */ |
| 463 | |
| 464 | switch ( op2c ) { |
| 465 | |
| 466 | /* |
| 467 | * Arithmetic instructions first |
| 468 | */ |
| 469 | |
| 470 | case T2o3_add : |
| 471 | if (rd == 0) goto do_noop; |
| 472 | if (simm == 0) { |
| 473 | if (rs1 == 0) goto do_zero_reg; |
| 474 | goto do_move_reg; |
| 475 | } |
| 476 | if (rs1 == 0) goto do_move_simm; |
| 477 | SET_OP( add_imm ); |
| 478 | goto do_imm; |
| 479 | |
| 480 | case T2o3_addc : |
| 481 | if (rd == 0) goto do_noop; |
| 482 | SET_OPv9( add_ci_imm ); |
| 483 | goto do_imm; |
| 484 | |
| 485 | case T2o3_addcc : |
| 486 | if (rd == 0) { |
| 487 | SET_OPv9( add_co_imm_rd0 ); /* rd==0 */ |
| 488 | } else { |
| 489 | SET_OPv9( add_co_imm ); |
| 490 | } |
| 491 | goto do_imm; |
| 492 | |
| 493 | case T2o3_addccc : |
| 494 | if (rd == 0 ) { |
| 495 | SET_OPv9( add_cico_imm_rd0 ); /* rd==0 */ |
| 496 | } else { |
| 497 | SET_OPv9( add_cico_imm ); |
| 498 | } |
| 499 | goto do_imm; |
| 500 | |
| 501 | case T2o3_sub : |
| 502 | if (rd == 0) goto do_noop; |
| 503 | if (simm == 0 && rs1 == 0) goto do_zero_reg; |
| 504 | if (simm == 0) goto do_move_reg; |
| 505 | simm = -simm; |
| 506 | if (rs1 == 0) goto do_move_simm; |
| 507 | SET_OP( add_imm ); |
| 508 | goto do_imm; |
| 509 | |
| 510 | case T2o3_subc : |
| 511 | if (rd == 0) goto do_noop; |
| 512 | SET_OPv9( sub_ci_imm ); |
| 513 | goto do_imm; |
| 514 | |
| 515 | case T2o3_subcc : |
| 516 | if (rd == 0) { |
| 517 | SET_OPv9( sub_co_imm_rd0 ); /* rd==0 */ |
| 518 | } else { |
| 519 | SET_OPv9( sub_co_imm ); |
| 520 | } |
| 521 | goto do_imm; |
| 522 | |
| 523 | case T2o3_subccc : |
| 524 | if (rd == 0) { |
| 525 | SET_OPv9( sub_cico_imm_rd0 ); /* rd==0 */ |
| 526 | } else { |
| 527 | SET_OPv9( sub_cico_imm ); |
| 528 | } |
| 529 | goto do_imm; |
| 530 | |
| 531 | case T2o3_andn : |
| 532 | simm = ~simm; /* fall thru*/ |
| 533 | case T2o3_and : |
| 534 | if (rd == 0) goto do_noop; |
| 535 | if (simm == 0 || rs1==0) goto do_zero_reg; |
| 536 | if (simm == -1) goto do_move_reg; |
| 537 | SET_OP( and_imm ); |
| 538 | goto do_imm; |
| 539 | |
| 540 | case T2o3_orn: |
| 541 | simm = ~simm; /* fall thru*/ |
| 542 | case T2o3_or : |
| 543 | if (rd == 0) goto do_noop; |
| 544 | if (simm == 0 && rs1==0) goto do_zero_reg; |
| 545 | if (simm == 0) goto do_move_reg; |
| 546 | if (rs1 == 0) goto do_move_simm; |
| 547 | SET_OP( or_imm ); |
| 548 | goto do_imm; |
| 549 | |
| 550 | case T2o3_xnor : |
| 551 | simm = ~simm; /* fall thru*/ |
| 552 | case T2o3_xor : |
| 553 | if (rd == 0) goto do_noop; |
| 554 | if (simm == 0 && rs1 == 0) goto do_zero_reg; |
| 555 | if (simm == 0) goto do_move_reg; |
| 556 | if (rs1 == 0) goto do_move_simm; |
| 557 | SET_OP( xor_imm ); |
| 558 | goto do_imm; |
| 559 | |
| 560 | |
| 561 | /* cond code out - forms */ |
| 562 | |
| 563 | case T2o3_andncc : |
| 564 | simm = ~simm; /* fall thru*/ |
| 565 | case T2o3_andcc : |
| 566 | if (rd == 0) { |
| 567 | SET_OPv9( and_cc_imm_rd0 ); /* rd==0 */ |
| 568 | } else { |
| 569 | SET_OPv9( and_cc_imm ); |
| 570 | } |
| 571 | goto do_imm; |
| 572 | |
| 573 | case T2o3_orncc : |
| 574 | simm = ~simm; /* fall thru*/ |
| 575 | case T2o3_orcc : |
| 576 | if (rd == 0) { |
| 577 | SET_OPv9( or_cc_imm_rd0 ); /* rd==0 */ |
| 578 | } else { |
| 579 | SET_OPv9( or_cc_imm ); |
| 580 | } |
| 581 | goto do_imm; |
| 582 | |
| 583 | case T2o3_xnorcc : |
| 584 | simm = ~simm; /* fall thru*/ |
| 585 | case T2o3_xorcc : |
| 586 | if (rd == 0) { |
| 587 | SET_OPv9( xor_cc_imm_rd0 ); /* rd==0 */ |
| 588 | } else { |
| 589 | SET_OPv9( xor_cc_imm ); |
| 590 | } |
| 591 | goto do_imm; |
| 592 | |
| 593 | |
| 594 | /* |
| 595 | ** Shift operations |
| 596 | */ |
| 597 | |
| 598 | case T2o3_sll : |
| 599 | if (!(X_SHIFT_SIZE_BIT(instn) ? |
| 600 | CHECK_RESERVED_ZERO(instn, 11, 6) : |
| 601 | CHECK_RESERVED_ZERO(instn, 11, 5))) { |
| 602 | SET_OP_ILL_REASON(misc_reserved_field_non_zero); |
| 603 | goto illegal_instruction; |
| 604 | } |
| 605 | if (rd == 0) goto do_noop; |
| 606 | if (rs1 == 0) goto do_zero_reg; |
| 607 | |
| 608 | simm = (X_SHIFT_SIZE_BIT(instn)) ? X_SHIFT_IMM64(instn) : X_SHIFT_IMM32(instn); |
| 609 | SET_OP(sll_imm); |
| 610 | goto do_imm; |
| 611 | |
| 612 | case T2o3_srl : |
| 613 | if (!(X_SHIFT_SIZE_BIT(instn) ? |
| 614 | CHECK_RESERVED_ZERO(instn, 11, 6) : |
| 615 | CHECK_RESERVED_ZERO(instn, 11, 5))) { |
| 616 | SET_OP_ILL_REASON(misc_reserved_field_non_zero); |
| 617 | goto illegal_instruction; |
| 618 | } |
| 619 | |
| 620 | if (rd == 0) goto do_noop; |
| 621 | if (rs1 == 0) goto do_zero_reg; |
| 622 | |
| 623 | if (X_SHIFT_SIZE_BIT(instn)) { |
| 624 | simm = X_SHIFT_IMM64(instn); |
| 625 | SET_OP( srl64_imm ); |
| 626 | } else { |
| 627 | simm = X_SHIFT_IMM32(instn); |
| 628 | SET_OP( srl32_imm ); |
| 629 | } |
| 630 | |
| 631 | goto do_imm; |
| 632 | |
| 633 | case T2o3_sra : |
| 634 | if (!(X_SHIFT_SIZE_BIT(instn) ? |
| 635 | CHECK_RESERVED_ZERO(instn, 11, 6) : |
| 636 | CHECK_RESERVED_ZERO(instn, 11, 5))) { |
| 637 | SET_OP_ILL_REASON(misc_reserved_field_non_zero); |
| 638 | goto illegal_instruction; |
| 639 | } |
| 640 | if (rd == 0) goto do_noop; |
| 641 | if (rs1 == 0) goto do_zero_reg; |
| 642 | |
| 643 | if (X_SHIFT_SIZE_BIT(instn)) { |
| 644 | simm = X_SHIFT_IMM64(instn); |
| 645 | SET_OP( sra64_imm ); |
| 646 | } else { |
| 647 | simm = X_SHIFT_IMM32(instn); |
| 648 | SET_OP( sra32_imm ); |
| 649 | } |
| 650 | |
| 651 | goto do_imm; |
| 652 | |
| 653 | case T2o3_jmpl : |
| 654 | if (rd == 0) { |
| 655 | SET_OPv9(jmpl_imm_rd0); |
| 656 | } else { |
| 657 | SET_OPv9(jmpl_imm); |
| 658 | } |
| 659 | goto do_imm; |
| 660 | |
| 661 | case T2o3_tcc : |
| 662 | if (!CHECK_RESERVED_ZERO(instn, 10, 8)) { |
| 663 | SET_OP_ILL_REASON(tcc_reserved_field_non_zero); |
| 664 | goto illegal_instruction; |
| 665 | } |
| 666 | switch( (cc4bit_t)X_FMT4_CC(instn) ) { |
| 667 | case CC4bit_icc: SET_OP_TRAP_CC(0); break; |
| 668 | case CC4bit_xcc: SET_OP_TRAP_CC(1); break; |
| 669 | default: |
| 670 | SET_OP_ILL_REASON(tcc_illegal_cc_field); |
| 671 | goto illegal_instruction; |
| 672 | } |
| 673 | |
| 674 | /* truncate simm - as only an 8 bit |
| 675 | * immediate in tcc instructions, not the |
| 676 | * 13 bit field we extracted above |
| 677 | */ |
| 678 | simm = simm & 0xff; |
| 679 | |
| 680 | if (X_COND(instn) == cond_n) goto do_noop; |
| 681 | SET_OP_RS1(rs1); |
| 682 | SET_OP_SIMM16(simm); |
| 683 | SET_OP_TRAP_COND(X_COND(instn)); |
| 684 | /* We attempt to fast path ta ... */ |
| 685 | if (X_COND(instn) == cond_a && rs1==0) |
| 686 | SET_OPv9(trap_imm_fast); |
| 687 | else |
| 688 | SET_OPv9(trapcc_imm); |
| 689 | goto all_done; |
| 690 | |
| 691 | case T2o3_saved: |
| 692 | saved_instn:; |
| 693 | /* Niagara2 and Rock support additional functions. */ |
| 694 | goto unknown_decode; |
| 695 | |
| 696 | case T2o3_retry : |
| 697 | done_retry_instn:; |
| 698 | /* This instruction is handled differently wrt niagara and rock. |
| 699 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 700 | * and niagara?.c |
| 701 | */ |
| 702 | goto unknown_decode; |
| 703 | |
| 704 | case T2o3_save : |
| 705 | /* This instruction is handled differently wrt niagara and rock. |
| 706 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 707 | * and niagara?.c |
| 708 | */ |
| 709 | goto unknown_decode; |
| 710 | |
| 711 | case T2o3_restore : |
| 712 | /* This instruction is handled differently wrt niagara and rock. |
| 713 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 714 | * and niagara?.c |
| 715 | */ |
| 716 | goto unknown_decode; |
| 717 | |
| 718 | case T2o3_smul : |
| 719 | /* can't check for rd = 0 because side-effect is write to Y reg */ |
| 720 | SET_OPv9(smul_imm); |
| 721 | goto do_imm; |
| 722 | |
| 723 | case T2o3_umul : |
| 724 | /* can't check for rd = 0 because side-effect is write to Y reg */ |
| 725 | SET_OPv9(umul_imm); |
| 726 | goto do_imm; |
| 727 | |
| 728 | case T2o3_mulx : |
| 729 | if (rd==0) goto do_noop; |
| 730 | SET_OP(mul_imm); |
| 731 | goto do_imm; |
| 732 | |
| 733 | case T2o3_rdasr : |
| 734 | /* This instruction is handled differently wrt niagara and rock. |
| 735 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 736 | * and niagara?.c |
| 737 | */ |
| 738 | goto unknown_decode; |
| 739 | |
| 740 | case T2o3_wrasr : |
| 741 | if (rd == 0xf) { |
| 742 | /* sir shares this opcode */ |
| 743 | if (!CHECK_RESERVED_ZERO(instn, 18, 14)) { |
| 744 | SET_OP_ILL_REASON(sir_reserved_field_non_zero); |
| 745 | goto illegal_instruction; |
| 746 | } |
| 747 | SET_OPv9( sir ); |
| 748 | SET_OP_SIMM16(simm); |
| 749 | goto all_done; |
| 750 | } |
| 751 | SET_OPv9( write_state_reg_imm ); |
| 752 | goto do_imm; |
| 753 | |
| 754 | case T2o3_rdpr : |
| 755 | SET_OPv9( read_priv_reg ); |
| 756 | simm = rs1; /* duplicate the reg code into simm */ |
| 757 | goto do_imm; |
| 758 | |
| 759 | case T2o3_rdhpr : |
| 760 | SET_OPv9( read_hyper_priv_reg ); |
| 761 | simm = rs1; /* duplicate the reg code into simm */ |
| 762 | goto do_imm; |
| 763 | |
| 764 | case T2o3_wrpr : |
| 765 | SET_OPv9( write_priv_reg_imm ); |
| 766 | goto do_imm; |
| 767 | |
| 768 | case T2o3_wrhpr : |
| 769 | SET_OPv9( write_hyper_priv_reg_imm ); |
| 770 | goto do_imm; |
| 771 | |
| 772 | case T2o3_return : |
| 773 | /* This instruction is handled differently wrt niagara and rock. |
| 774 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 775 | * and niagara?.c |
| 776 | */ |
| 777 | goto unknown_decode; |
| 778 | |
| 779 | case T2o3_udivx : |
| 780 | /* cant optimise for rd=0 because */ |
| 781 | /* need to test for /0 */ |
| 782 | SET_OPv9(udiv64_imm); |
| 783 | goto do_imm; |
| 784 | |
| 785 | case T2o3_udiv : |
| 786 | SET_OPv9(udiv_imm); |
| 787 | goto do_imm; |
| 788 | |
| 789 | case T2o3_sdiv : |
| 790 | SET_OPv9(sdiv_imm); |
| 791 | goto do_imm; |
| 792 | |
| 793 | case T2o3_umulcc : |
| 794 | SET_OPv9(umul_cc_imm); |
| 795 | goto do_imm; |
| 796 | |
| 797 | case T2o3_smulcc : |
| 798 | SET_OPv9(smul_cc_imm); |
| 799 | goto do_imm; |
| 800 | |
| 801 | case T2o3_udivcc : |
| 802 | SET_OPv9(udiv_cc_imm); |
| 803 | goto do_imm; |
| 804 | |
| 805 | case T2o3_sdivcc : |
| 806 | SET_OPv9(sdiv_cc_imm); |
| 807 | goto do_imm; |
| 808 | |
| 809 | case T2o3_taddcc : |
| 810 | SET_OPv9(tadd_co_imm); |
| 811 | goto do_imm; |
| 812 | |
| 813 | case T2o3_tsubcc : |
| 814 | SET_OPv9(tsub_co_imm); |
| 815 | goto do_imm; |
| 816 | |
| 817 | case T2o3_taddcctv : |
| 818 | SET_OPv9(tadd_co_tv_imm); |
| 819 | goto do_imm; |
| 820 | |
| 821 | case T2o3_tsubcctv : |
| 822 | SET_OPv9(tsub_co_tv_imm); |
| 823 | goto do_imm; |
| 824 | |
| 825 | case T2o3_mulscc : |
| 826 | goto unknown_decode; |
| 827 | |
| 828 | case T2o3_flushw : |
| 829 | SET_OP_ILL_REASON(flushw_reserved_field_non_zero); |
| 830 | goto illegal_instruction; |
| 831 | |
| 832 | case T2o3_movcc : |
| 833 | /* This instruction is handled differently wrt niagara and rock. |
| 834 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 835 | * and niagara?.c |
| 836 | */ |
| 837 | goto unknown_decode; |
| 838 | |
| 839 | case T2o3_sdivx : |
| 840 | SET_OPv9(sdiv64_imm); |
| 841 | goto do_imm; |
| 842 | |
| 843 | case T2o3_popc : |
| 844 | goto unknown_decode; |
| 845 | |
| 846 | case T2o3_movr : |
| 847 | if (rd == 0) goto do_noop; |
| 848 | simm = X_SIMM10(instn); |
| 849 | SET_OP_SIMM16(simm); |
| 850 | SET_OP_RS1(rs1); |
| 851 | SET_OP_RD(rd); |
| 852 | switch ((rcond_type_t)X_MOVRCOND(instn)) { |
| 853 | case RCond_z: |
| 854 | SET_OPv9(movr_imm_z); |
| 855 | break; |
| 856 | case RCond_lez: |
| 857 | SET_OPv9(movr_imm_lez); |
| 858 | break; |
| 859 | case RCond_lz: |
| 860 | SET_OPv9(movr_imm_lz); |
| 861 | break; |
| 862 | case RCond_nz: |
| 863 | SET_OPv9(movr_imm_nz); |
| 864 | break; |
| 865 | case RCond_gz: |
| 866 | SET_OPv9(movr_imm_gz); |
| 867 | break; |
| 868 | case RCond_gez: |
| 869 | SET_OPv9(movr_imm_gez); |
| 870 | break; |
| 871 | default: |
| 872 | SET_OP_ILL_REASON(movr_illegal_cc_field); |
| 873 | goto illegal_instruction; |
| 874 | } |
| 875 | goto all_done; |
| 876 | |
| 877 | case T2o3_fpop_0x34 : |
| 878 | /* jumping out of _imm to _rrr forms */ |
| 879 | rs2 = X_RS2(instn); |
| 880 | goto handle_fpop_0x34; |
| 881 | |
| 882 | case T2o3_fpop_0x35 : |
| 883 | /* jumping out of _imm to _rrr forms */ |
| 884 | rs2 = X_RS2(instn); |
| 885 | goto handle_fpop_0x35; |
| 886 | |
| 887 | case T2o3_gop : |
| 888 | /* jumping out of _imm to _rrr forms */ |
| 889 | rs2 = X_RS2(instn); |
| 890 | goto handle_gop; |
| 891 | |
| 892 | case T2o3_flush : |
| 893 | /* This instruction is handled differently wrt niagara and rock. |
| 894 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 895 | * and niagara?.c |
| 896 | */ |
| 897 | goto unknown_decode; |
| 898 | |
| 899 | case T2o3_unknown_0x19 : |
| 900 | case T2o3_unknown_0x1d : |
| 901 | case T2o3_unknown_0x37 : |
| 902 | case T2o3_unknown_0x3f : |
| 903 | break; |
| 904 | } |
| 905 | goto unknown_decode; |
| 906 | |
| 907 | } else { |
| 908 | rs2 = X_RS2(instn); |
| 909 | |
| 910 | /* register x register -> register forms */ |
| 911 | switch ( op2c ) { |
| 912 | case T2o3_add : |
| 913 | if (rd == 0) goto do_noop; |
| 914 | if (rs2 == 0) { |
| 915 | if (rs1 == 0) goto do_zero_reg; |
| 916 | goto do_move_reg; |
| 917 | } |
| 918 | if (rs1 == 0) { |
| 919 | rs1 = rs2; |
| 920 | goto do_move_reg; |
| 921 | } |
| 922 | SET_OP( add_rrr ); |
| 923 | goto do_rrr; |
| 924 | |
| 925 | case T2o3_addc : |
| 926 | if (rd == 0) goto do_noop; |
| 927 | SET_OPv9( add_ci_rrr ); |
| 928 | goto do_rrr; |
| 929 | |
| 930 | case T2o3_addcc : |
| 931 | if (rd == 0) { |
| 932 | SET_OPv9( add_co_rrr_rd0 ); |
| 933 | } else { |
| 934 | SET_OPv9( add_co_rrr ); |
| 935 | } |
| 936 | goto do_rrr; |
| 937 | |
| 938 | case T2o3_addccc : |
| 939 | if (rd == 0) { |
| 940 | SET_OPv9( add_cico_rrr_rd0 ); |
| 941 | } else { |
| 942 | SET_OPv9( add_cico_rrr ); |
| 943 | } |
| 944 | goto do_rrr; |
| 945 | |
| 946 | case T2o3_sub : |
| 947 | if (rd==0) goto do_noop; |
| 948 | if (rs2==0 && rs1==0) goto do_zero_reg; |
| 949 | if (rs2==0) goto do_move_reg; |
| 950 | SET_OP( sub_rrr ); |
| 951 | goto do_rrr; |
| 952 | |
| 953 | case T2o3_subc : |
| 954 | if (rd == 0) goto do_noop; |
| 955 | SET_OPv9( sub_ci_rrr ); |
| 956 | goto do_rrr; |
| 957 | |
| 958 | case T2o3_subcc : |
| 959 | if (rd == 0) { |
| 960 | SET_OPv9( sub_co_rrr_rd0 ); |
| 961 | } else { |
| 962 | SET_OPv9( sub_co_rrr ); |
| 963 | } |
| 964 | goto do_rrr; |
| 965 | |
| 966 | case T2o3_subccc : |
| 967 | if (rd == 0) { |
| 968 | SET_OPv9( sub_cico_rrr_rd0 ); |
| 969 | } else { |
| 970 | SET_OPv9( sub_cico_rrr ); |
| 971 | } |
| 972 | goto do_rrr; |
| 973 | |
| 974 | |
| 975 | /* |
| 976 | * Logic RRR forms |
| 977 | */ |
| 978 | |
| 979 | case T2o3_and : |
| 980 | if (rd == 0) goto do_noop; |
| 981 | if (rs2 == 0 || rs1==0) goto do_zero_reg; |
| 982 | SET_OP( and_rrr ); |
| 983 | goto do_rrr; |
| 984 | |
| 985 | case T2o3_or : |
| 986 | if (rd == 0) goto do_noop; |
| 987 | if (rs2 == 0 && rs1==0) goto do_zero_reg; |
| 988 | if (rs2 == 0) goto do_move_reg; |
| 989 | if (rs1 == 0) { |
| 990 | rs1 = rs2; |
| 991 | goto do_move_reg; |
| 992 | } |
| 993 | SET_OP( or_rrr ); |
| 994 | goto do_rrr; |
| 995 | |
| 996 | case T2o3_xor: |
| 997 | if (rd == 0) goto do_noop; |
| 998 | if (rs2 == 0 && rs1==0) goto do_zero_reg; |
| 999 | if (rs2 == 0) goto do_move_reg; |
| 1000 | if (rs1 == 0) { |
| 1001 | rs1 = rs2; |
| 1002 | goto do_move_reg; |
| 1003 | } |
| 1004 | SET_OP( xor_rrr ); |
| 1005 | goto do_rrr; |
| 1006 | |
| 1007 | case T2o3_andn : |
| 1008 | if (rd==0) goto do_noop; |
| 1009 | if (rs1==0) goto do_zero_reg; |
| 1010 | if (rs2==0) goto do_move_reg; |
| 1011 | SET_OP( andn_rrr ); |
| 1012 | goto do_rrr; |
| 1013 | |
| 1014 | case T2o3_orn : |
| 1015 | if (rd==0) goto do_noop; |
| 1016 | /* more optmisiing here - FIXME */ |
| 1017 | SET_OP( orn_rrr ); |
| 1018 | goto do_rrr; |
| 1019 | |
| 1020 | case T2o3_xnor : |
| 1021 | if (rd == 0) goto do_noop; |
| 1022 | SET_OP( xnor_rrr ); |
| 1023 | goto do_rrr; |
| 1024 | |
| 1025 | /* condition code forms */ |
| 1026 | |
| 1027 | case T2o3_andcc : |
| 1028 | if (rd == 0) { /* RD0DECODE */ |
| 1029 | SET_OPv9( and_cc_rrr_rd0 ); |
| 1030 | } else { |
| 1031 | SET_OPv9( and_cc_rrr ); |
| 1032 | } |
| 1033 | goto do_rrr; |
| 1034 | |
| 1035 | case T2o3_andncc : |
| 1036 | if (rd == 0) { /* RD0DECODE */ |
| 1037 | SET_OPv9( andn_cc_rrr_rd0 ); |
| 1038 | } else { |
| 1039 | SET_OPv9( andn_cc_rrr ); |
| 1040 | } |
| 1041 | goto do_rrr; |
| 1042 | |
| 1043 | case T2o3_orcc : |
| 1044 | if (rd == 0) { /* RD0DECODE */ |
| 1045 | SET_OPv9( or_cc_rrr_rd0 ); |
| 1046 | } else { |
| 1047 | SET_OPv9( or_cc_rrr ); |
| 1048 | } |
| 1049 | goto do_rrr; |
| 1050 | |
| 1051 | case T2o3_orncc : |
| 1052 | if (rd == 0) { /* RD0DECODE */ |
| 1053 | SET_OPv9( orn_cc_rrr_rd0 ); |
| 1054 | } else { |
| 1055 | SET_OPv9( orn_cc_rrr ); |
| 1056 | } |
| 1057 | goto do_rrr; |
| 1058 | |
| 1059 | case T2o3_xorcc : |
| 1060 | if (rd == 0) { /* RD0DECODE */ |
| 1061 | SET_OPv9( xor_cc_rrr_rd0 ); |
| 1062 | } else { |
| 1063 | SET_OPv9( xor_cc_rrr ); |
| 1064 | } |
| 1065 | goto do_rrr; |
| 1066 | |
| 1067 | case T2o3_xnorcc : |
| 1068 | if (rd == 0) { /* RD0DECODE */ |
| 1069 | SET_OPv9( xnor_cc_rrr_rd0 ); |
| 1070 | } else { |
| 1071 | SET_OPv9( xnor_cc_rrr ); |
| 1072 | } |
| 1073 | goto do_rrr; |
| 1074 | |
| 1075 | |
| 1076 | /* |
| 1077 | ** Shift operations |
| 1078 | */ |
| 1079 | |
| 1080 | |
| 1081 | case T2o3_sll : |
| 1082 | if (!CHECK_RESERVED_ZERO(instn, 11, 5)) { |
| 1083 | SET_OP_ILL_REASON(misc_reserved_field_non_zero); |
| 1084 | goto illegal_instruction; |
| 1085 | } |
| 1086 | if (rd == 0) goto do_noop; |
| 1087 | if (X_SHIFT_SIZE_BIT(instn)) { |
| 1088 | SET_OP(sll64_rrr); |
| 1089 | } else { |
| 1090 | SET_OP(sll32_rrr); |
| 1091 | } |
| 1092 | goto do_rrr; |
| 1093 | |
| 1094 | case T2o3_srl : |
| 1095 | if (!CHECK_RESERVED_ZERO(instn, 11, 5)) { |
| 1096 | SET_OP_ILL_REASON(misc_reserved_field_non_zero); |
| 1097 | goto illegal_instruction; |
| 1098 | } |
| 1099 | if (rd == 0) goto do_noop; |
| 1100 | if (X_SHIFT_SIZE_BIT(instn)) { |
| 1101 | SET_OP(srl64_rrr); |
| 1102 | } else { |
| 1103 | SET_OP(srl32_rrr); |
| 1104 | } |
| 1105 | goto do_rrr; |
| 1106 | |
| 1107 | |
| 1108 | case T2o3_sra : |
| 1109 | if (!CHECK_RESERVED_ZERO(instn, 11, 5)) { |
| 1110 | SET_OP_ILL_REASON(misc_reserved_field_non_zero); |
| 1111 | goto illegal_instruction; |
| 1112 | } |
| 1113 | if (rd == 0) goto do_noop; |
| 1114 | if (X_SHIFT_SIZE_BIT(instn)) { |
| 1115 | SET_OP(sra64_rrr); |
| 1116 | } else { |
| 1117 | SET_OP(sra32_rrr); |
| 1118 | } |
| 1119 | goto do_rrr; |
| 1120 | |
| 1121 | |
| 1122 | case T2o3_jmpl : |
| 1123 | if (!CHECK_RESERVED_ZERO(instn, 12, 5)) { |
| 1124 | SET_OP_ILL_REASON(misc_reserved_field_non_zero); |
| 1125 | goto illegal_instruction; |
| 1126 | } |
| 1127 | if (rd == 0) { |
| 1128 | SET_OPv9(jmpl_rrr_rd0); |
| 1129 | } else { |
| 1130 | SET_OPv9(jmpl_rrr); |
| 1131 | } |
| 1132 | goto do_rrr; |
| 1133 | |
| 1134 | case T2o3_saved: |
| 1135 | goto saved_instn; |
| 1136 | |
| 1137 | case T2o3_retry : |
| 1138 | goto done_retry_instn; |
| 1139 | |
| 1140 | |
| 1141 | case T2o3_smul : |
| 1142 | /* can't check for rd = 0 because side-effect is write to Y reg */ |
| 1143 | SET_OPv9(smul_rrr); |
| 1144 | goto do_rrr; |
| 1145 | |
| 1146 | case T2o3_umul : |
| 1147 | /* can't check for rd = 0 because side-effect is write to Y reg */ |
| 1148 | SET_OPv9(umul_rrr); |
| 1149 | goto do_rrr; |
| 1150 | |
| 1151 | case T2o3_mulx : |
| 1152 | if (rd==0) goto do_noop; |
| 1153 | SET_OP(mul_rrr); |
| 1154 | goto do_rrr; |
| 1155 | |
| 1156 | case T2o3_rdasr : |
| 1157 | /* Here I = 0 */ |
| 1158 | if (rd == 0 && rs1==15) { |
| 1159 | if (!CHECK_RESERVED_ZERO(instn, 12, 0)) { |
| 1160 | SET_OP_ILL_REASON(misc_reserved_field_non_zero); |
| 1161 | goto illegal_instruction; |
| 1162 | } |
| 1163 | SET_OPv9( stbar ); |
| 1164 | goto all_done; /* no further args */ |
| 1165 | } |
| 1166 | SET_OPv9( read_state_reg ); |
| 1167 | simm = 0; /* unused */ |
| 1168 | goto do_imm; |
| 1169 | |
| 1170 | case T2o3_rdpr : |
| 1171 | SET_OPv9( read_priv_reg ); |
| 1172 | simm = rs1; /* duplicate the reg code into simm */ |
| 1173 | goto do_imm; |
| 1174 | |
| 1175 | case T2o3_rdhpr : |
| 1176 | SET_OPv9( read_hyper_priv_reg ); |
| 1177 | simm = rs1; /* duplicate the reg code into simm */ |
| 1178 | goto do_imm; |
| 1179 | |
| 1180 | case T2o3_wrpr : |
| 1181 | SET_OPv9( write_priv_reg_rrr ); |
| 1182 | goto do_rrr; |
| 1183 | |
| 1184 | case T2o3_wrhpr : |
| 1185 | SET_OPv9( write_hyper_priv_reg_rrr ); |
| 1186 | goto do_rrr; |
| 1187 | |
| 1188 | case T2o3_wrasr : |
| 1189 | SET_OPv9( write_state_reg_rrr ); |
| 1190 | goto do_rrr; |
| 1191 | |
| 1192 | |
| 1193 | /* save and restore ! */ |
| 1194 | |
| 1195 | case T2o3_save : |
| 1196 | /* This instruction is handled differently wrt niagara and rock. |
| 1197 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 1198 | * and niagara?.c |
| 1199 | */ |
| 1200 | goto unknown_decode; |
| 1201 | |
| 1202 | case T2o3_restore : |
| 1203 | /* This instruction is handled differently wrt niagara and rock. |
| 1204 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 1205 | * and niagara?.c |
| 1206 | */ |
| 1207 | goto unknown_decode; |
| 1208 | |
| 1209 | case T2o3_return : |
| 1210 | /* This instruction is handled differently wrt niagara and rock. |
| 1211 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 1212 | * and niagara?.c |
| 1213 | */ |
| 1214 | goto unknown_decode; |
| 1215 | |
| 1216 | |
| 1217 | case T2o3_tcc : |
| 1218 | if (!CHECK_RESERVED_ZERO(instn, 10, 5)) { |
| 1219 | SET_OP_ILL_REASON(tcc_reserved_field_non_zero); |
| 1220 | goto illegal_instruction; |
| 1221 | } |
| 1222 | switch( (cc4bit_t)X_FMT4_CC(instn) ) { |
| 1223 | case CC4bit_icc: SET_OP_TRAP_CC(0); break; |
| 1224 | case CC4bit_xcc: SET_OP_TRAP_CC(1); break; |
| 1225 | default: |
| 1226 | SET_OP_ILL_REASON(tcc_illegal_cc_field); |
| 1227 | goto illegal_instruction; |
| 1228 | } |
| 1229 | |
| 1230 | if (X_COND(instn) == cond_n) goto do_noop; |
| 1231 | SET_OP_RS1(rs1); |
| 1232 | SET_OP_RS2(rs2); |
| 1233 | SET_OP_TRAP_COND(X_COND(instn)); |
| 1234 | SET_OPv9(trapcc_rr); |
| 1235 | goto all_done; |
| 1236 | |
| 1237 | case T2o3_udivx : |
| 1238 | /* cant optimise for rd=0 because */ |
| 1239 | /* need to test for /0 */ |
| 1240 | SET_OPv9(udiv64_rrr); |
| 1241 | goto do_rrr; |
| 1242 | |
| 1243 | case T2o3_udiv : |
| 1244 | SET_OPv9(udiv_rrr); |
| 1245 | goto do_rrr; |
| 1246 | |
| 1247 | case T2o3_sdiv : |
| 1248 | SET_OPv9(sdiv_rrr); |
| 1249 | goto do_rrr; |
| 1250 | |
| 1251 | case T2o3_umulcc : |
| 1252 | SET_OPv9(umul_cc_rrr); |
| 1253 | goto do_rrr; |
| 1254 | |
| 1255 | case T2o3_smulcc : |
| 1256 | SET_OPv9(smul_cc_rrr); |
| 1257 | goto do_rrr; |
| 1258 | |
| 1259 | case T2o3_udivcc : |
| 1260 | SET_OPv9(udiv_cc_rrr); |
| 1261 | goto do_rrr; |
| 1262 | |
| 1263 | case T2o3_sdivcc : |
| 1264 | SET_OPv9(sdiv_cc_rrr); |
| 1265 | goto do_rrr; |
| 1266 | |
| 1267 | case T2o3_taddcc : |
| 1268 | SET_OPv9(tadd_co_rrr); |
| 1269 | goto do_rrr; |
| 1270 | |
| 1271 | case T2o3_tsubcc : |
| 1272 | SET_OPv9(tsub_co_rrr); |
| 1273 | goto do_rrr; |
| 1274 | |
| 1275 | case T2o3_taddcctv : |
| 1276 | SET_OPv9(tadd_co_tv_rrr); |
| 1277 | goto do_rrr; |
| 1278 | |
| 1279 | case T2o3_tsubcctv : |
| 1280 | SET_OPv9(tsub_co_tv_rrr); |
| 1281 | goto do_rrr; |
| 1282 | |
| 1283 | case T2o3_mulscc : |
| 1284 | goto unknown_decode; |
| 1285 | |
| 1286 | case T2o3_flushw : |
| 1287 | { |
| 1288 | int fcn = X_FMT2_FCN(instn); |
| 1289 | |
| 1290 | if (!fcn && (!CHECK_RESERVED_ZERO(instn, 18, 0))) { |
| 1291 | SET_OP_ILL_REASON(flushw_reserved_field_non_zero); |
| 1292 | goto illegal_instruction; |
| 1293 | } |
| 1294 | SET_OPv9(flushw); |
| 1295 | goto all_done; |
| 1296 | } |
| 1297 | |
| 1298 | case T2o3_movcc : |
| 1299 | if (!CHECK_RESERVED_ZERO(instn, 10, 5)) { |
| 1300 | SET_OP_ILL_REASON(movcc_reserved_field_non_zero); |
| 1301 | goto illegal_instruction; |
| 1302 | } |
| 1303 | |
| 1304 | if (!X_FMT4_CC2(instn)) { |
| 1305 | FP_DECODE_FPU_ON_CHECK; |
| 1306 | if (rd == 0) goto do_noop; |
| 1307 | |
| 1308 | /* We attempt to fast path movfcc_a ... */ |
| 1309 | if (X_FMT4_COND(instn) == cond_n) goto do_noop; |
| 1310 | if (X_FMT4_COND(instn) == cond_a) { |
| 1311 | rs1 = rs2; |
| 1312 | goto do_move_reg; |
| 1313 | } |
| 1314 | SET_OP_MOVCC_CC(X_FMT4_CC(instn)); |
| 1315 | SET_OP_RD(rd); |
| 1316 | SET_OP_RS2(rs2); |
| 1317 | SET_OP_MOVCC_COND(X_FMT4_COND(instn)); |
| 1318 | SET_OPv9(movfcc_rr); |
| 1319 | goto all_done; |
| 1320 | } |
| 1321 | |
| 1322 | if (rd == 0) goto do_noop; |
| 1323 | |
| 1324 | switch( (cc4bit_t)X_FMT4_CC(instn) ) { |
| 1325 | case CC4bit_icc: SET_OP_MOVCC_CC(0); break; |
| 1326 | case CC4bit_xcc: SET_OP_MOVCC_CC(1); break; |
| 1327 | default: |
| 1328 | SET_OP_ILL_REASON(movcc_illegal_cc_field); |
| 1329 | goto illegal_instruction; |
| 1330 | } |
| 1331 | |
| 1332 | /* We attempt to fast path movcc_a ... */ |
| 1333 | if (X_FMT4_COND(instn) == cond_n) goto do_noop; |
| 1334 | if (X_FMT4_COND(instn) == cond_a) { |
| 1335 | rs1 = rs2; |
| 1336 | goto do_move_reg; |
| 1337 | } |
| 1338 | SET_OP_RD(rd); |
| 1339 | SET_OP_RS2(rs2); |
| 1340 | SET_OP_MOVCC_COND(X_FMT4_COND(instn)); |
| 1341 | SET_OPv9(movcc_rr); |
| 1342 | goto all_done; |
| 1343 | |
| 1344 | case T2o3_sdivx : |
| 1345 | SET_OPv9(sdiv64_rrr); |
| 1346 | goto do_rrr; |
| 1347 | |
| 1348 | case T2o3_popc : |
| 1349 | goto unknown_decode; |
| 1350 | |
| 1351 | case T2o3_movr : |
| 1352 | if (rd == 0) goto do_noop; |
| 1353 | SET_OP_RS1(rs1); |
| 1354 | SET_OP_RS2(rs2); |
| 1355 | SET_OP_RD(rd); |
| 1356 | switch ((rcond_type_t)X_MOVRCOND(instn)) { |
| 1357 | case RCond_z: |
| 1358 | SET_OPv9(movr_rr_z); |
| 1359 | break; |
| 1360 | case RCond_lez: |
| 1361 | SET_OPv9(movr_rr_lez); |
| 1362 | break; |
| 1363 | case RCond_lz: |
| 1364 | SET_OPv9(movr_rr_lz); |
| 1365 | break; |
| 1366 | case RCond_nz: |
| 1367 | SET_OPv9(movr_rr_nz); |
| 1368 | break; |
| 1369 | case RCond_gz: |
| 1370 | SET_OPv9(movr_rr_gz); |
| 1371 | break; |
| 1372 | case RCond_gez: |
| 1373 | SET_OPv9(movr_rr_gez); |
| 1374 | break; |
| 1375 | default: |
| 1376 | SET_OP_ILL_REASON(movr_illegal_cc_field); |
| 1377 | goto illegal_instruction; |
| 1378 | } |
| 1379 | goto all_done; |
| 1380 | |
| 1381 | |
| 1382 | case T2o3_fpop_0x34 : |
| 1383 | handle_fpop_0x34:; |
| 1384 | FP_DECODE_FPU_ON_CHECK; |
| 1385 | switch ((T3o3_fp34_opf_t)X_FP_OPF(instn)) { |
| 1386 | case FPop34_fmovs: SET_OPv9(fmovs); goto do_fp_s2s_ds; |
| 1387 | case FPop34_fmovd: SET_OPv9(fmovd); goto do_fp_s2d_dd; |
| 1388 | case FPop34_fmovq: goto unimplemented_fpop; |
| 1389 | case FPop34_fnegs: SET_OPv9(fnegs); goto do_fp_s2s_ds; |
| 1390 | case FPop34_fnegd: SET_OPv9(fnegd); goto do_fp_s2d_dd; |
| 1391 | case FPop34_fnegq: goto unimplemented_fpop; |
| 1392 | case FPop34_fabss: SET_OPv9(fabss); goto do_fp_s2s_ds; |
| 1393 | case FPop34_fabsd: SET_OPv9(fabsd); goto do_fp_s2d_dd; |
| 1394 | case FPop34_fabsq: goto unimplemented_fpop; |
| 1395 | /* |
| 1396 | * Niagara 1 doesn't have fsqrt[sd], but this |
| 1397 | * is dealt with in the fpsim_bw support. |
| 1398 | */ |
| 1399 | case FPop34_fsqrts: SET_OPv9(fsqrts); goto do_fp_s2s_ds; |
| 1400 | case FPop34_fsqrtd: SET_OPv9(fsqrtd); goto do_fp_s2d_dd; |
| 1401 | case FPop34_fsqrtq: goto unimplemented_fpop; |
| 1402 | |
| 1403 | case FPop34_fadds: SET_OPv9(fadds); goto do_fp_s1s_s2s_ds; |
| 1404 | case FPop34_faddd: SET_OPv9(faddd); goto do_fp_s1d_s2d_dd; |
| 1405 | case FPop34_faddq: goto unimplemented_fpop; |
| 1406 | case FPop34_fsubs: SET_OPv9(fsubs); goto do_fp_s1s_s2s_ds; |
| 1407 | case FPop34_fsubd: SET_OPv9(fsubd); goto do_fp_s1d_s2d_dd; |
| 1408 | case FPop34_fsubq: goto unimplemented_fpop; |
| 1409 | case FPop34_fmuls: SET_OPv9(fmuls); goto do_fp_s1s_s2s_ds; |
| 1410 | case FPop34_fmuld: SET_OPv9(fmuld); goto do_fp_s1d_s2d_dd; |
| 1411 | case FPop34_fmulq: goto unimplemented_fpop; |
| 1412 | case FPop34_fdivs: SET_OPv9(fdivs); goto do_fp_s1s_s2s_ds; |
| 1413 | case FPop34_fdivd: SET_OPv9(fdivd); goto do_fp_s1d_s2d_dd; |
| 1414 | case FPop34_fdivq: goto unimplemented_fpop; |
| 1415 | case FPop34_fsmuld: SET_OPv9(fsmuld); goto do_fp_s1s_s2s_dd; |
| 1416 | case FPop34_fdmulq: goto unimplemented_fpop; |
| 1417 | |
| 1418 | case FPop34_fstox: SET_OPv9(fstox); goto do_fp_s2s_dd; |
| 1419 | case FPop34_fdtox: SET_OPv9(fdtox); goto do_fp_s2d_dd; |
| 1420 | case FPop34_fqtox: goto unimplemented_fpop; |
| 1421 | case FPop34_fxtos: SET_OPv9(fxtos); goto do_fp_s2d_ds; |
| 1422 | case FPop34_fxtod: SET_OPv9(fxtod); goto do_fp_s2d_dd; |
| 1423 | case FPop34_fxtoq: goto unimplemented_fpop; |
| 1424 | case FPop34_fitos: SET_OPv9(fitos); goto do_fp_s2s_ds; |
| 1425 | case FPop34_fdtos: SET_OPv9(fdtos); goto do_fp_s2d_ds; |
| 1426 | case FPop34_fqtos: goto unimplemented_fpop; |
| 1427 | case FPop34_fitod: SET_OPv9(fitod); goto do_fp_s2s_dd; |
| 1428 | case FPop34_fstod: SET_OPv9(fstod); goto do_fp_s2s_dd; |
| 1429 | case FPop34_fqtod: goto unimplemented_fpop; |
| 1430 | case FPop34_fitoq: goto unimplemented_fpop; |
| 1431 | case FPop34_fstoq: goto unimplemented_fpop; |
| 1432 | case FPop34_fdtoq: goto unimplemented_fpop; |
| 1433 | case FPop34_fstoi: SET_OPv9(fstoi); goto do_fp_s2s_ds; |
| 1434 | case FPop34_fdtoi: SET_OPv9(fdtoi); goto do_fp_s2d_ds; |
| 1435 | case FPop34_fqtoi: goto unimplemented_fpop; |
| 1436 | default: |
| 1437 | goto unknown_fp_decode; |
| 1438 | } |
| 1439 | |
| 1440 | case T2o3_fpop_0x35 : |
| 1441 | handle_fpop_0x35: |
| 1442 | FP_DECODE_FPU_ON_CHECK; |
| 1443 | switch ((T3o3_fp35_opf_t)X_FP_OPF(instn)) { |
| 1444 | case FPop35_fcmps: |
| 1445 | switch( (fcc2bit_t)X_FCOND(instn)) { |
| 1446 | case FCC2bit_fcc0: |
| 1447 | SET_OPv9(fcmps_fcc0); break; |
| 1448 | case FCC2bit_fcc1: |
| 1449 | SET_OPv9(fcmps_fcc1); break; |
| 1450 | case FCC2bit_fcc2: |
| 1451 | SET_OPv9(fcmps_fcc2); break; |
| 1452 | case FCC2bit_fcc3: |
| 1453 | SET_OPv9(fcmps_fcc3); break; |
| 1454 | } |
| 1455 | goto do_fp_s1s_s2s_cmp; |
| 1456 | case FPop35_fcmpd: |
| 1457 | switch( (fcc2bit_t)X_FCOND(instn)) { |
| 1458 | case FCC2bit_fcc0: |
| 1459 | SET_OPv9(fcmpd_fcc0); break; |
| 1460 | case FCC2bit_fcc1: |
| 1461 | SET_OPv9(fcmpd_fcc1); break; |
| 1462 | case FCC2bit_fcc2: |
| 1463 | SET_OPv9(fcmpd_fcc2); break; |
| 1464 | case FCC2bit_fcc3: |
| 1465 | SET_OPv9(fcmpd_fcc3); break; |
| 1466 | } |
| 1467 | goto do_fp_s1d_s2d_cmp; |
| 1468 | case FPop35_fcmpq: goto unimplemented_fpop; |
| 1469 | case FPop35_fcmpes: |
| 1470 | switch( (fcc2bit_t)X_FCOND(instn)) { |
| 1471 | case FCC2bit_fcc0: |
| 1472 | SET_OPv9(fcmpes_fcc0); break; |
| 1473 | case FCC2bit_fcc1: |
| 1474 | SET_OPv9(fcmpes_fcc1); break; |
| 1475 | case FCC2bit_fcc2: |
| 1476 | SET_OPv9(fcmpes_fcc2); break; |
| 1477 | case FCC2bit_fcc3: |
| 1478 | SET_OPv9(fcmpes_fcc3); break; |
| 1479 | } |
| 1480 | goto do_fp_s1s_s2s_cmp; |
| 1481 | case FPop35_fcmped: |
| 1482 | switch( (fcc2bit_t)X_FCOND(instn)) { |
| 1483 | case FCC2bit_fcc0: |
| 1484 | SET_OPv9(fcmped_fcc0); break; |
| 1485 | case FCC2bit_fcc1: |
| 1486 | SET_OPv9(fcmped_fcc1); break; |
| 1487 | case FCC2bit_fcc2: |
| 1488 | SET_OPv9(fcmped_fcc2); break; |
| 1489 | case FCC2bit_fcc3: |
| 1490 | SET_OPv9(fcmped_fcc3); break; |
| 1491 | } |
| 1492 | goto do_fp_s1d_s2d_cmp; |
| 1493 | case FPop35_fcmpeq: goto unimplemented_fpop; |
| 1494 | |
| 1495 | case FPop35_fmovs_fcc0: |
| 1496 | case FPop35_fmovs_fcc1: |
| 1497 | case FPop35_fmovs_fcc2: |
| 1498 | case FPop35_fmovs_fcc3: |
| 1499 | case FPop35_fmovs_icc: |
| 1500 | case FPop35_fmovs_xcc: |
| 1501 | if (!CHECK_RESERVED_ZERO(instn, 18, 18)) { |
| 1502 | SET_OP_ILL_REASON(fmovcc_reserved_field_non_zero); |
| 1503 | goto illegal_instruction; |
| 1504 | } |
| 1505 | |
| 1506 | if (X_FMT4_COND(instn) == cond_n) |
| 1507 | goto do_noop; |
| 1508 | if (X_FMT4_COND(instn) == cond_a) { |
| 1509 | SET_OPv9(fmovs); |
| 1510 | goto do_fp_s2s_ds; |
| 1511 | } |
| 1512 | if (X_FMT4_CC2a(instn)) { |
| 1513 | switch( (cc4bit_t)X_FMT4_CC(instn) ) { |
| 1514 | case CC4bit_icc: SET_OP_MOVCC_CC(0); break; |
| 1515 | case CC4bit_xcc: SET_OP_MOVCC_CC(1); break; |
| 1516 | default: |
| 1517 | SET_OP_ILL_REASON(fmovcc_illegal_cc_field); |
| 1518 | goto illegal_instruction; |
| 1519 | } |
| 1520 | SET_OPv9(fmovscc); |
| 1521 | } else { |
| 1522 | SET_OP_MOVCC_CC(X_FMT4_CC(instn)); |
| 1523 | SET_OPv9(fmovsfcc); |
| 1524 | } |
| 1525 | SET_OP_MOVCC_COND(X_FMT4_COND(instn)); |
| 1526 | goto do_fp_s2s_ds; |
| 1527 | case FPop35_fmovd_fcc0: |
| 1528 | case FPop35_fmovd_fcc1: |
| 1529 | case FPop35_fmovd_fcc2: |
| 1530 | case FPop35_fmovd_fcc3: |
| 1531 | case FPop35_fmovd_icc: |
| 1532 | case FPop35_fmovd_xcc: |
| 1533 | if (!CHECK_RESERVED_ZERO(instn, 18, 18)) { |
| 1534 | SET_OP_ILL_REASON(fmovcc_reserved_field_non_zero); |
| 1535 | goto illegal_instruction; |
| 1536 | } |
| 1537 | |
| 1538 | if (X_FMT4_COND(instn) == cond_n) |
| 1539 | goto do_noop; |
| 1540 | if (X_FMT4_COND(instn) == cond_a) { |
| 1541 | SET_OPv9(fmovd); |
| 1542 | goto do_fp_s2d_dd; |
| 1543 | } |
| 1544 | if (X_FMT4_CC2a(instn)) { |
| 1545 | switch( (cc4bit_t)X_FMT4_CC(instn) ) { |
| 1546 | case CC4bit_icc: SET_OP_MOVCC_CC(0); break; |
| 1547 | case CC4bit_xcc: SET_OP_MOVCC_CC(1); break; |
| 1548 | default: |
| 1549 | SET_OP_ILL_REASON(fmovcc_illegal_cc_field); |
| 1550 | goto illegal_instruction; |
| 1551 | } |
| 1552 | SET_OPv9(fmovdcc); |
| 1553 | } else { |
| 1554 | SET_OP_MOVCC_CC(X_FMT4_CC(instn)); |
| 1555 | SET_OPv9(fmovdfcc); |
| 1556 | } |
| 1557 | SET_OP_MOVCC_COND(X_FMT4_COND(instn)); |
| 1558 | goto do_fp_s2d_dd; |
| 1559 | |
| 1560 | case FPop35_fmovrsz: |
| 1561 | SET_OPv9(fmovrs_z); |
| 1562 | goto fmovrs_common; |
| 1563 | case FPop35_fmovrslez: |
| 1564 | SET_OPv9(fmovrs_lez); |
| 1565 | goto fmovrs_common; |
| 1566 | case FPop35_fmovrslz: |
| 1567 | SET_OPv9(fmovrs_lz); |
| 1568 | goto fmovrs_common; |
| 1569 | case FPop35_fmovrsnz: |
| 1570 | SET_OPv9(fmovrs_nz); |
| 1571 | goto fmovrs_common; |
| 1572 | case FPop35_fmovrsgz: |
| 1573 | SET_OPv9(fmovrs_gz); |
| 1574 | goto fmovrs_common; |
| 1575 | case FPop35_fmovrsgez: |
| 1576 | SET_OPv9(fmovrs_gez); |
| 1577 | fmovrs_common: |
| 1578 | SET_OP_RS1(rs1); |
| 1579 | rs2 = FP_32_INDX(rs2); |
| 1580 | SET_OP_FPRS2( rs2 ); |
| 1581 | rd = FP_32_INDX(rd); |
| 1582 | SET_OP_FPRD( rd ); |
| 1583 | goto all_done; |
| 1584 | |
| 1585 | case FPop35_fmovrdz: |
| 1586 | SET_OPv9(fmovrd_z); |
| 1587 | goto fmovrd_common; |
| 1588 | case FPop35_fmovrdlez: |
| 1589 | SET_OPv9(fmovrd_lez); |
| 1590 | goto fmovrd_common; |
| 1591 | case FPop35_fmovrdlz: |
| 1592 | SET_OPv9(fmovrd_lz); |
| 1593 | goto fmovrd_common; |
| 1594 | case FPop35_fmovrdnz: |
| 1595 | SET_OPv9(fmovrd_nz); |
| 1596 | goto fmovrd_common; |
| 1597 | case FPop35_fmovrdgz: |
| 1598 | SET_OPv9(fmovrd_gz); |
| 1599 | goto fmovrd_common; |
| 1600 | case FPop35_fmovrdgez: |
| 1601 | SET_OPv9(fmovrd_gez); |
| 1602 | fmovrd_common: |
| 1603 | SET_OP_RS1(rs1); |
| 1604 | RESCALEFPREG(rs2); |
| 1605 | SET_OP_FPRS2( rs2 ); |
| 1606 | RESCALEFPREG(rd); |
| 1607 | SET_OP_FPRD( rd ); |
| 1608 | goto all_done; |
| 1609 | |
| 1610 | default: |
| 1611 | goto unimplemented_fpop; |
| 1612 | } |
| 1613 | |
| 1614 | case T2o3_gop : |
| 1615 | handle_gop:; |
| 1616 | /* |
| 1617 | * strange but true ... if fp disabled, VIS |
| 1618 | * instructions fail because they can't access |
| 1619 | * the FP registers ... except the ones that |
| 1620 | * don't use them. |
| 1621 | * ... otherwise unknown VIS instructions |
| 1622 | * fail as illegal instructions. |
| 1623 | */ |
| 1624 | switch ((T3o3_fp36_opf_t)X_FP_OPF(instn)) { |
| 1625 | case VISop36_alignaddr: |
| 1626 | FP_DECODE_FPU_ON_CHECK; |
| 1627 | SET_OPv9(alignaddr); |
| 1628 | goto do_rrr; |
| 1629 | case VISop36_alignaddrl: |
| 1630 | FP_DECODE_FPU_ON_CHECK; |
| 1631 | SET_OPv9(alignaddrl); |
| 1632 | goto do_rrr; |
| 1633 | case VISop36_faligndata: |
| 1634 | SET_OPv9(faligndata); |
| 1635 | goto do_fp_s1d_s2d_dd; |
| 1636 | case VISop36_fzerod: |
| 1637 | SET_OPv9(fzerod); |
| 1638 | goto do_fp_s1d; |
| 1639 | case VISop36_fzeros: |
| 1640 | SET_OPv9(fzeros); |
| 1641 | goto do_fp_s1s; |
| 1642 | case VISop36_foned: |
| 1643 | SET_OPv9(foned); |
| 1644 | goto do_fp_s1d; |
| 1645 | case VISop36_fones: |
| 1646 | SET_OPv9(fones); |
| 1647 | goto do_fp_s1s; |
| 1648 | case VISop36_fandd: |
| 1649 | SET_OPv9(fandd); |
| 1650 | goto do_fp_s1d_s2d_dd; |
| 1651 | case VISop36_fandnot1d: |
| 1652 | SET_OPv9(fandnot1d); |
| 1653 | goto do_fp_s1d_s2d_dd; |
| 1654 | case VISop36_fandnot1s: |
| 1655 | SET_OPv9(fandnot1s); |
| 1656 | goto do_fp_s1s_s2s_ds; |
| 1657 | case VISop36_fandnot2d: |
| 1658 | SET_OPv9(fandnot2d); |
| 1659 | goto do_fp_s1d_s2d_dd; |
| 1660 | case VISop36_fandnot2s: |
| 1661 | SET_OPv9(fandnot2s); |
| 1662 | goto do_fp_s1s_s2s_ds; |
| 1663 | case VISop36_fands: |
| 1664 | SET_OPv9(fands); |
| 1665 | goto do_fp_s1s_s2s_ds; |
| 1666 | case VISop36_fnandd: |
| 1667 | SET_OPv9(fnandd); |
| 1668 | goto do_fp_s1d_s2d_dd; |
| 1669 | case VISop36_fnands: |
| 1670 | SET_OPv9(fnands); |
| 1671 | goto do_fp_s1s_s2s_ds; |
| 1672 | case VISop36_fnord: |
| 1673 | SET_OPv9(fnord); |
| 1674 | goto do_fp_s1d_s2d_dd; |
| 1675 | case VISop36_fnors: |
| 1676 | SET_OPv9(fnors); |
| 1677 | goto do_fp_s1s_s2s_ds; |
| 1678 | case VISop36_fnot1d: |
| 1679 | SET_OPv9(fnotXd); |
| 1680 | goto do_fp_s1d_dd; |
| 1681 | case VISop36_fnot1s: |
| 1682 | SET_OPv9(fnotXs); |
| 1683 | goto do_fp_s1s_ds; |
| 1684 | case VISop36_fnot2d: |
| 1685 | SET_OPv9(fnotXd); |
| 1686 | goto do_fp_s2d_dd; |
| 1687 | case VISop36_fnot2s: |
| 1688 | SET_OPv9(fnotXs); |
| 1689 | goto do_fp_s2s_ds; |
| 1690 | case VISop36_ford: |
| 1691 | SET_OPv9(ford); |
| 1692 | goto do_fp_s1d_s2d_dd; |
| 1693 | case VISop36_fornot1d: |
| 1694 | SET_OPv9(fornot1d); |
| 1695 | goto do_fp_s1d_s2d_dd; |
| 1696 | case VISop36_fornot1s: |
| 1697 | SET_OPv9(fornot1s); |
| 1698 | goto do_fp_s1s_s2s_ds; |
| 1699 | case VISop36_fornot2d: |
| 1700 | SET_OPv9(fornot2d); |
| 1701 | goto do_fp_s1d_s2d_dd; |
| 1702 | case VISop36_fornot2s: |
| 1703 | SET_OPv9(fornot2s); |
| 1704 | goto do_fp_s1s_s2s_ds; |
| 1705 | case VISop36_fors: |
| 1706 | SET_OPv9(fors); |
| 1707 | goto do_fp_s1s_s2s_ds; |
| 1708 | case VISop36_fsrc1d: |
| 1709 | SET_OPv9(fsrcXd); |
| 1710 | goto do_fp_s1d_dd; |
| 1711 | case VISop36_fsrc1s: |
| 1712 | SET_OPv9(fsrcXs); |
| 1713 | goto do_fp_s1s_ds; |
| 1714 | case VISop36_fsrc2d: |
| 1715 | SET_OPv9(fsrcXd); |
| 1716 | goto do_fp_s2d_dd; |
| 1717 | case VISop36_fsrc2s: |
| 1718 | SET_OPv9(fsrcXs); |
| 1719 | goto do_fp_s2s_ds; |
| 1720 | case VISop36_fxnord: |
| 1721 | SET_OPv9(fxnord); |
| 1722 | goto do_fp_s1d_s2d_dd; |
| 1723 | case VISop36_fxnors: |
| 1724 | SET_OPv9(fxnors); |
| 1725 | goto do_fp_s1s_s2s_ds; |
| 1726 | case VISop36_fxord: |
| 1727 | SET_OPv9(fxord); |
| 1728 | goto do_fp_s1d_s2d_dd; |
| 1729 | case VISop36_fxors: |
| 1730 | SET_OPv9(fxors); |
| 1731 | goto do_fp_s1s_s2s_ds; |
| 1732 | case VISop36_fpadd16: |
| 1733 | SET_OPv9(fpadd16); |
| 1734 | goto do_fp_s1d_s2d_dd; |
| 1735 | case VISop36_fpadd16s: |
| 1736 | SET_OPv9(fpadd16s); |
| 1737 | goto do_fp_s1s_s2s_ds; |
| 1738 | case VISop36_fpadd32: |
| 1739 | SET_OPv9(fpadd32); |
| 1740 | goto do_fp_s1d_s2d_dd; |
| 1741 | case VISop36_fpadd32s: |
| 1742 | SET_OPv9(fpadd32s); |
| 1743 | goto do_fp_s1s_s2s_ds; |
| 1744 | case VISop36_fpsub16: |
| 1745 | SET_OPv9(fpsub16); |
| 1746 | goto do_fp_s1d_s2d_dd; |
| 1747 | case VISop36_fpsub16s: |
| 1748 | SET_OPv9(fpsub16s); |
| 1749 | goto do_fp_s1s_s2s_ds; |
| 1750 | case VISop36_fpsub32: |
| 1751 | SET_OPv9(fpsub32); |
| 1752 | goto do_fp_s1d_s2d_dd; |
| 1753 | case VISop36_fpsub32s: |
| 1754 | SET_OPv9(fpsub32s); |
| 1755 | goto do_fp_s1s_s2s_ds; |
| 1756 | case VISop36_siam: |
| 1757 | if (!CHECK_RESERVED_ZERO3(instn, 29, 25, 18, 14, 4, 3)) { |
| 1758 | SET_OP_ILL_REASON(visop36_reserved_field_non_zero); |
| 1759 | goto illegal_instruction; |
| 1760 | } |
| 1761 | FP_DECODE_FPU_ON_CHECK; |
| 1762 | /* extract mode field */ |
| 1763 | SET_OP_SIMM16((instn & 7)); |
| 1764 | SET_OPv9(siam); |
| 1765 | goto all_done; |
| 1766 | default: |
| 1767 | break; |
| 1768 | } |
| 1769 | goto unimplemented_visop; |
| 1770 | |
| 1771 | case T2o3_flush : |
| 1772 | /* This instruction is handled differently wrt niagara and rock. |
| 1773 | * Therefore it is moved to cpu_decode_me() functions in rock.c |
| 1774 | * and niagara?.c |
| 1775 | */ |
| 1776 | goto unknown_decode; |
| 1777 | |
| 1778 | case T2o3_unknown_0x19 : |
| 1779 | case T2o3_unknown_0x1d : |
| 1780 | case T2o3_unknown_0x37 : |
| 1781 | case T2o3_unknown_0x3f : |
| 1782 | goto unknown_decode; |
| 1783 | } |
| 1784 | goto unknown_decode; |
| 1785 | } |
| 1786 | |
| 1787 | /* |
| 1788 | * Principally load/store operation decoding |
| 1789 | */ |
| 1790 | |
| 1791 | case Ty_3: |
| 1792 | |
| 1793 | rs1 = X_RS1(instn); |
| 1794 | rd = X_RD(instn); |
| 1795 | |
| 1796 | op3c = (T3o3_code_t)X_OP3(instn); |
| 1797 | |
| 1798 | if (X_I(instn)) { |
| 1799 | simm = X_SIMM13(instn); |
| 1800 | |
| 1801 | /* register x immediate -> register forms */ |
| 1802 | |
| 1803 | switch ( op3c ) { |
| 1804 | case T3o3_lduw: |
| 1805 | if (rd == 0) { |
| 1806 | SET_OP_ASI_OP(MA_ldu32); |
| 1807 | SET_OPv9(memop_imm); |
| 1808 | goto do_memop_imm; |
| 1809 | } |
| 1810 | SET_OP( ldu32_imm ); |
| 1811 | goto do_imm; |
| 1812 | |
| 1813 | case T3o3_ldub: |
| 1814 | if (rd == 0) { |
| 1815 | SET_OP_ASI_OP(MA_ldu8); |
| 1816 | SET_OPv9(memop_imm); |
| 1817 | goto do_memop_imm; |
| 1818 | } |
| 1819 | SET_OP( ldu8_imm ); |
| 1820 | goto do_imm; |
| 1821 | |
| 1822 | case T3o3_lduh: |
| 1823 | if (rd == 0) { |
| 1824 | SET_OP_ASI_OP(MA_ldu16); |
| 1825 | SET_OPv9(memop_imm); |
| 1826 | goto do_memop_imm; |
| 1827 | } |
| 1828 | SET_OP( ldu16_imm ); |
| 1829 | goto do_imm; |
| 1830 | |
| 1831 | case T3o3_ldd: |
| 1832 | if (rd & 1) { |
| 1833 | SET_OP_ILL_REASON(odd_rd_for_ldd); |
| 1834 | goto illegal_instruction; |
| 1835 | } |
| 1836 | SET_OP_ASI_OP(MA_lddu64); |
| 1837 | SET_OPv9(memop_imm); |
| 1838 | goto do_memop_imm; |
| 1839 | |
| 1840 | case T3o3_stw: |
| 1841 | SET_OP( st32_imm ); |
| 1842 | goto do_imm; |
| 1843 | |
| 1844 | case T3o3_stb: |
| 1845 | SET_OP( st8_imm ); |
| 1846 | goto do_imm; |
| 1847 | |
| 1848 | case T3o3_sth: |
| 1849 | SET_OP( st16_imm ); |
| 1850 | goto do_imm; |
| 1851 | |
| 1852 | case T3o3_std: |
| 1853 | if (rd & 1) { |
| 1854 | SET_OP_ILL_REASON(odd_rd_for_std); |
| 1855 | goto illegal_instruction; |
| 1856 | } |
| 1857 | SET_OP_ASI_OP(MA_stdu64); |
| 1858 | SET_OPv9(memop_imm); |
| 1859 | goto do_memop_imm; |
| 1860 | |
| 1861 | case T3o3_ldsw: |
| 1862 | if (rd == 0) { |
| 1863 | SET_OP_ASI_OP(MA_lds32); |
| 1864 | SET_OPv9(memop_imm); |
| 1865 | goto do_memop_imm; |
| 1866 | } |
| 1867 | SET_OP( lds32_imm ); |
| 1868 | goto do_imm; |
| 1869 | |
| 1870 | case T3o3_ldsb: |
| 1871 | if (rd == 0) { |
| 1872 | SET_OP_ASI_OP(MA_lds8); |
| 1873 | SET_OPv9(memop_imm); |
| 1874 | goto do_memop_imm; |
| 1875 | } |
| 1876 | SET_OP( lds8_imm ); |
| 1877 | goto do_imm; |
| 1878 | |
| 1879 | case T3o3_ldsh: |
| 1880 | if (rd == 0) { |
| 1881 | SET_OP_ASI_OP(MA_lds16); |
| 1882 | SET_OPv9(memop_imm); |
| 1883 | goto do_memop_imm; |
| 1884 | } |
| 1885 | SET_OP( lds16_imm ); |
| 1886 | goto do_imm; |
| 1887 | |
| 1888 | case T3o3_ldx: |
| 1889 | if (rd == 0) { |
| 1890 | SET_OP_ASI_OP(MA_ldu64); |
| 1891 | SET_OPv9(memop_imm); |
| 1892 | goto do_memop_imm; |
| 1893 | } |
| 1894 | SET_OP( ld64_imm ); |
| 1895 | goto do_imm; |
| 1896 | |
| 1897 | case T3o3_ldstub1: |
| 1898 | SET_OP_ASI_OP(MA_ldstub); |
| 1899 | SET_OPv9(memop_imm); |
| 1900 | goto do_memop_imm; |
| 1901 | |
| 1902 | case T3o3_swapd: |
| 1903 | SET_OP_ASI_OP(MA_swap); |
| 1904 | SET_OPv9(memop_imm); |
| 1905 | goto do_memop_imm; |
| 1906 | |
| 1907 | case T3o3_stx: |
| 1908 | SET_OP( st64_imm ); |
| 1909 | goto do_imm; |
| 1910 | |
| 1911 | case T3o3_lduwa: |
| 1912 | SET_OP_ASI_OP(MA_ldu32); |
| 1913 | SET_OPv9(asi_reg_imm); |
| 1914 | goto do_asi_imm; |
| 1915 | |
| 1916 | case T3o3_lduba: |
| 1917 | SET_OP_ASI_OP(MA_ldu8); |
| 1918 | SET_OPv9(asi_reg_imm); |
| 1919 | goto do_asi_imm; |
| 1920 | |
| 1921 | case T3o3_lduha: |
| 1922 | SET_OP_ASI_OP(MA_ldu16); |
| 1923 | SET_OPv9(asi_reg_imm); |
| 1924 | goto do_asi_imm; |
| 1925 | |
| 1926 | case T3o3_ldxa: |
| 1927 | SET_OP_ASI_OP(MA_ldu64); |
| 1928 | SET_OPv9(asi_reg_imm); |
| 1929 | goto do_asi_imm; |
| 1930 | |
| 1931 | case T3o3_ldstuba: |
| 1932 | SET_OP_ASI_OP(MA_ldstub); |
| 1933 | SET_OPv9(asi_reg_imm); |
| 1934 | goto do_asi_imm; |
| 1935 | |
| 1936 | case T3o3_stwa: |
| 1937 | SET_OP_ASI_OP(MA_st32); |
| 1938 | SET_OPv9(asi_reg_imm); |
| 1939 | goto do_asi_imm; |
| 1940 | |
| 1941 | case T3o3_stba: |
| 1942 | SET_OP_ASI_OP(MA_st8); |
| 1943 | SET_OPv9(asi_reg_imm); |
| 1944 | goto do_asi_imm; |
| 1945 | |
| 1946 | case T3o3_stha: |
| 1947 | SET_OP_ASI_OP(MA_st16); |
| 1948 | SET_OPv9(asi_reg_imm); |
| 1949 | goto do_asi_imm; |
| 1950 | |
| 1951 | case T3o3_stxa: |
| 1952 | SET_OP_ASI_OP(MA_st64); |
| 1953 | SET_OPv9(asi_reg_imm); |
| 1954 | goto do_asi_imm; |
| 1955 | |
| 1956 | case T3o3_ldda: |
| 1957 | if (rd & 1) { |
| 1958 | SET_OP_ILL_REASON(odd_rd_for_ldd); |
| 1959 | goto illegal_instruction; |
| 1960 | } |
| 1961 | SET_OP_ASI_OP(MA_lddu64); |
| 1962 | SET_OPv9(asi_reg_imm); |
| 1963 | goto do_asi_imm; |
| 1964 | |
| 1965 | case T3o3_stda: |
| 1966 | if (rd & 1) { |
| 1967 | SET_OP_ILL_REASON(odd_rd_for_std); |
| 1968 | goto illegal_instruction; |
| 1969 | } |
| 1970 | SET_OP_ASI_OP(MA_stdu64); |
| 1971 | SET_OPv9(asi_reg_imm); |
| 1972 | goto do_asi_imm; |
| 1973 | |
| 1974 | case T3o3_ldswa: |
| 1975 | SET_OP_ASI_OP(MA_lds32); |
| 1976 | SET_OPv9(asi_reg_imm); |
| 1977 | goto do_asi_imm; |
| 1978 | |
| 1979 | case T3o3_ldsba: |
| 1980 | SET_OP_ASI_OP(MA_lds8); |
| 1981 | SET_OPv9(asi_reg_imm); |
| 1982 | goto do_asi_imm; |
| 1983 | |
| 1984 | case T3o3_ldsha: |
| 1985 | SET_OP_ASI_OP(MA_lds16); |
| 1986 | SET_OPv9(asi_reg_imm); |
| 1987 | goto do_asi_imm; |
| 1988 | |
| 1989 | case T3o3_casa: |
| 1990 | SET_OP_ASI_OP(MA_cas32); |
| 1991 | goto do_cas_imm; |
| 1992 | case T3o3_casxa: |
| 1993 | SET_OP_ASI_OP(MA_cas64); |
| 1994 | do_cas_imm: |
| 1995 | if (!CHECK_RESERVED_ZERO(instn, 12, 5)) { |
| 1996 | SET_OP_ILL_REASON(cas_reserved_field_non_zero); |
| 1997 | goto illegal_instruction; |
| 1998 | } |
| 1999 | SET_OPv9(asi_reg); |
| 2000 | SET_OP_RS1( rs1 ); |
| 2001 | SET_OP_RS2( X_RS2(instn) ); |
| 2002 | SET_OP_ASI_RD( rd ); |
| 2003 | goto all_done; |
| 2004 | |
| 2005 | case T3o3_ldf: |
| 2006 | rd = FP_32_INDX(rd); |
| 2007 | SET_OP( ldfp32_imm ); |
| 2008 | goto do_fp_ldst_imm; |
| 2009 | |
| 2010 | case T3o3_lddf: |
| 2011 | RESCALEFPREG(rd); |
| 2012 | SET_OP( ldfp64_imm ); |
| 2013 | goto do_fp_ldst_imm; |
| 2014 | |
| 2015 | case T3o3_ldqf: |
| 2016 | SET_OP_ILL_REASON(illegal_instruction); |
| 2017 | goto illegal_instruction; |
| 2018 | |
| 2019 | case T3o3_stf: |
| 2020 | rd = FP_32_INDX(rd); |
| 2021 | SET_OP( stfp32_imm ); |
| 2022 | goto do_fp_ldst_imm; |
| 2023 | |
| 2024 | case T3o3_stdf: |
| 2025 | RESCALEFPREG(rd); |
| 2026 | SET_OP( stfp64_imm ); |
| 2027 | goto do_fp_ldst_imm; |
| 2028 | |
| 2029 | case T3o3_stqf: |
| 2030 | SET_OP_ILL_REASON(illegal_instruction); |
| 2031 | goto illegal_instruction; |
| 2032 | |
| 2033 | case T3o3_ldfsr: |
| 2034 | switch (rd) { |
| 2035 | case 0: |
| 2036 | SET_OPv9( ldfsr_imm ); |
| 2037 | break; |
| 2038 | case 1: |
| 2039 | SET_OPv9( ldxfsr_imm ); |
| 2040 | break; |
| 2041 | default: |
| 2042 | SET_OP_ILL_REASON(illegal_fsr_specifier); |
| 2043 | goto illegal_instruction; |
| 2044 | } |
| 2045 | goto do_fp_fsr_imm; |
| 2046 | |
| 2047 | case T3o3_stfsr: |
| 2048 | switch (rd) { |
| 2049 | case 0: |
| 2050 | SET_OPv9( stfsr_imm ); |
| 2051 | break; |
| 2052 | case 1: |
| 2053 | SET_OPv9( stxfsr_imm ); |
| 2054 | break; |
| 2055 | default: |
| 2056 | SET_OP_ILL_REASON(illegal_fsr_specifier); |
| 2057 | goto illegal_instruction; |
| 2058 | } |
| 2059 | goto do_fp_fsr_imm; |
| 2060 | |
| 2061 | case T3o3_ldfa: |
| 2062 | FP_DECODE_FPU_ON_CHECK; |
| 2063 | SET_OP_ASI_OP(MA_ldfp32); |
| 2064 | SET_OPv9(fp64asi_imm); |
| 2065 | goto do_asi_imm; |
| 2066 | |
| 2067 | case T3o3_stfa: |
| 2068 | FP_DECODE_FPU_ON_CHECK; |
| 2069 | SET_OP_ASI_OP(MA_stfp32); |
| 2070 | SET_OPv9(fp64asi_imm); |
| 2071 | goto do_asi_imm; |
| 2072 | |
| 2073 | case T3o3_ldqfa: |
| 2074 | case T3o3_stqfa: |
| 2075 | SET_OP_ILL_REASON(illegal_instruction); |
| 2076 | goto illegal_instruction; |
| 2077 | |
| 2078 | case T3o3_lddfa: |
| 2079 | FP_DECODE_FPU_ON_CHECK; |
| 2080 | SET_OP_ASI_OP(MA_ldfp64); |
| 2081 | SET_OPv9(fp64asi_imm); |
| 2082 | goto do_fp_asi_imm; |
| 2083 | |
| 2084 | case T3o3_stdfa: |
| 2085 | FP_DECODE_FPU_ON_CHECK; |
| 2086 | SET_OP_ASI_OP(MA_stfp64); |
| 2087 | SET_OPv9(fp64asi_imm); |
| 2088 | goto do_fp_asi_imm; |
| 2089 | case T3o3_prefetch: |
| 2090 | case T3o3_prefetcha: |
| 2091 | goto do_noop; |
| 2092 | |
| 2093 | case T3o3_swapa: |
| 2094 | SET_OP_ASI_OP(MA_swap); |
| 2095 | SET_OPv9(asi_reg_imm); |
| 2096 | goto do_asi_imm; |
| 2097 | |
| 2098 | default: |
| 2099 | goto unknown_decode; |
| 2100 | } |
| 2101 | |
| 2102 | } else { |
| 2103 | rs2 = X_RS2(instn); |
| 2104 | |
| 2105 | switch ( op3c ) { |
| 2106 | case T3o3_lduw: |
| 2107 | if (rd == 0) { |
| 2108 | SET_OP_ASI_OP(MA_ldu32); |
| 2109 | SET_OPv9(memop_rrr); |
| 2110 | goto do_memop_rrr; |
| 2111 | } |
| 2112 | SET_OP(ldu32_rrr); |
| 2113 | goto do_rrr; |
| 2114 | |
| 2115 | case T3o3_ldub: |
| 2116 | if (rd == 0) { |
| 2117 | SET_OP_ASI_OP(MA_ldu8); |
| 2118 | SET_OPv9(memop_rrr); |
| 2119 | goto do_memop_rrr; |
| 2120 | } |
| 2121 | SET_OP(ldu8_rrr); |
| 2122 | goto do_rrr; |
| 2123 | |
| 2124 | case T3o3_lduh: |
| 2125 | if (rd == 0) { |
| 2126 | SET_OP_ASI_OP(MA_ldu16); |
| 2127 | SET_OPv9(memop_rrr); |
| 2128 | goto do_memop_rrr; |
| 2129 | } |
| 2130 | SET_OP(ldu16_rrr); |
| 2131 | goto do_rrr; |
| 2132 | |
| 2133 | case T3o3_ldd: |
| 2134 | if (rd & 1) { |
| 2135 | SET_OP_ILL_REASON(odd_rd_for_ldd); |
| 2136 | goto illegal_instruction; |
| 2137 | } |
| 2138 | SET_OP_ASI_OP(MA_lddu64); |
| 2139 | SET_OPv9(memop_rrr); |
| 2140 | goto do_memop_rrr; |
| 2141 | |
| 2142 | case T3o3_stw: |
| 2143 | SET_OP(st32_rrr); |
| 2144 | goto do_rrr; |
| 2145 | |
| 2146 | case T3o3_stb: |
| 2147 | SET_OP(st8_rrr); |
| 2148 | goto do_rrr; |
| 2149 | |
| 2150 | case T3o3_sth: |
| 2151 | SET_OP(st16_rrr); |
| 2152 | goto do_rrr; |
| 2153 | |
| 2154 | case T3o3_std: |
| 2155 | if (rd & 1) { |
| 2156 | SET_OP_ILL_REASON(odd_rd_for_std); |
| 2157 | goto illegal_instruction; |
| 2158 | } |
| 2159 | SET_OP_ASI_OP(MA_stdu64); |
| 2160 | SET_OPv9(memop_rrr); |
| 2161 | goto do_memop_rrr; |
| 2162 | |
| 2163 | case T3o3_ldsw: |
| 2164 | if (rd == 0) { |
| 2165 | SET_OP_ASI_OP(MA_lds32); |
| 2166 | SET_OPv9(memop_rrr); |
| 2167 | goto do_memop_rrr; |
| 2168 | } |
| 2169 | SET_OP(lds32_rrr); |
| 2170 | goto do_rrr; |
| 2171 | |
| 2172 | case T3o3_ldsb: |
| 2173 | if (rd == 0) { |
| 2174 | SET_OP_ASI_OP(MA_lds8); |
| 2175 | SET_OPv9(memop_rrr); |
| 2176 | goto do_memop_rrr; |
| 2177 | } |
| 2178 | SET_OP(lds8_rrr); |
| 2179 | goto do_rrr; |
| 2180 | |
| 2181 | case T3o3_ldsh: |
| 2182 | if (rd == 0) { |
| 2183 | SET_OP_ASI_OP(MA_lds16); |
| 2184 | SET_OPv9(memop_rrr); |
| 2185 | goto do_memop_rrr; |
| 2186 | } |
| 2187 | SET_OP(lds16_rrr); |
| 2188 | goto do_rrr; |
| 2189 | |
| 2190 | case T3o3_ldx: |
| 2191 | if (rd == 0) { |
| 2192 | SET_OP_ASI_OP(MA_ldu64); |
| 2193 | SET_OPv9(memop_rrr); |
| 2194 | goto do_memop_rrr; |
| 2195 | } |
| 2196 | SET_OP(ld64_rrr); |
| 2197 | goto do_rrr; |
| 2198 | |
| 2199 | case T3o3_ldstub1: |
| 2200 | SET_OP_ASI_OP(MA_ldstub); |
| 2201 | SET_OPv9(memop_rrr); |
| 2202 | goto do_memop_rrr; |
| 2203 | |
| 2204 | case T3o3_swapd: |
| 2205 | SET_OP_ASI_OP(MA_swap); |
| 2206 | SET_OPv9(memop_rrr); |
| 2207 | goto do_memop_rrr; |
| 2208 | |
| 2209 | case T3o3_stx: |
| 2210 | SET_OP(st64_rrr); |
| 2211 | goto do_rrr; |
| 2212 | |
| 2213 | case T3o3_lduwa: |
| 2214 | SET_OP_ASI_OP(MA_ldu32); |
| 2215 | SET_OPv9(asi_num); |
| 2216 | goto do_asi_rrr; |
| 2217 | |
| 2218 | case T3o3_lduba: |
| 2219 | SET_OP_ASI_OP(MA_ldu8); |
| 2220 | SET_OPv9(asi_num); |
| 2221 | goto do_asi_rrr; |
| 2222 | |
| 2223 | case T3o3_lduha: |
| 2224 | SET_OP_ASI_OP(MA_ldu16); |
| 2225 | SET_OPv9(asi_num); |
| 2226 | goto do_asi_rrr; |
| 2227 | |
| 2228 | case T3o3_ldstuba: |
| 2229 | SET_OP_ASI_OP(MA_ldstub); |
| 2230 | SET_OPv9(asi_num); |
| 2231 | goto do_asi_rrr; |
| 2232 | |
| 2233 | case T3o3_ldxa: |
| 2234 | SET_OP_ASI_OP(MA_ldu64); |
| 2235 | SET_OPv9(asi_num); |
| 2236 | goto do_asi_rrr; |
| 2237 | |
| 2238 | case T3o3_stwa: |
| 2239 | SET_OP_ASI_OP(MA_st32); |
| 2240 | SET_OPv9(asi_num); |
| 2241 | goto do_asi_rrr; |
| 2242 | |
| 2243 | case T3o3_stba: |
| 2244 | SET_OP_ASI_OP(MA_st8); |
| 2245 | SET_OPv9(asi_num); |
| 2246 | goto do_asi_rrr; |
| 2247 | |
| 2248 | case T3o3_stha: |
| 2249 | SET_OP_ASI_OP(MA_st16); |
| 2250 | SET_OPv9(asi_num); |
| 2251 | goto do_asi_rrr; |
| 2252 | |
| 2253 | case T3o3_stxa: |
| 2254 | SET_OP_ASI_OP(MA_st64); |
| 2255 | SET_OPv9(asi_num); |
| 2256 | goto do_asi_rrr; |
| 2257 | |
| 2258 | case T3o3_ldda: |
| 2259 | if (rd & 1) { |
| 2260 | SET_OP_ILL_REASON(odd_rd_for_ldd); |
| 2261 | goto illegal_instruction; |
| 2262 | } |
| 2263 | SET_OP_ASI_OP(MA_lddu64); |
| 2264 | SET_OPv9(asi_num); |
| 2265 | goto do_asi_rrr; |
| 2266 | |
| 2267 | case T3o3_stda: |
| 2268 | if (rd & 1) { |
| 2269 | SET_OP_ILL_REASON(odd_rd_for_std); |
| 2270 | goto illegal_instruction; |
| 2271 | } |
| 2272 | SET_OP_ASI_OP(MA_stdu64); |
| 2273 | SET_OPv9(asi_num); |
| 2274 | goto do_asi_rrr; |
| 2275 | |
| 2276 | case T3o3_ldswa: |
| 2277 | SET_OP_ASI_OP(MA_lds32); |
| 2278 | SET_OPv9(asi_num); |
| 2279 | goto do_asi_rrr; |
| 2280 | |
| 2281 | case T3o3_ldsba: |
| 2282 | SET_OP_ASI_OP(MA_lds8); |
| 2283 | SET_OPv9(asi_num); |
| 2284 | goto do_asi_rrr; |
| 2285 | |
| 2286 | case T3o3_ldsha: |
| 2287 | SET_OP_ASI_OP(MA_lds16); |
| 2288 | SET_OPv9(asi_num); |
| 2289 | goto do_asi_rrr; |
| 2290 | |
| 2291 | |
| 2292 | case T3o3_casa: |
| 2293 | SET_OP_ASI_OP(MA_cas32); |
| 2294 | goto do_cas_notimm; |
| 2295 | case T3o3_casxa: |
| 2296 | SET_OP_ASI_OP(MA_cas64); |
| 2297 | do_cas_notimm: |
| 2298 | SET_OPv9(asi_num); |
| 2299 | SET_OP_RS1( rs1 ); |
| 2300 | SET_OP_RS2( rs2 ); |
| 2301 | SET_OP_ASI_RD( rd ); |
| 2302 | SET_OP_ASI_NUM( X_ASI(instn) ); |
| 2303 | goto all_done; |
| 2304 | |
| 2305 | case T3o3_ldf: |
| 2306 | rd = FP_32_INDX(rd); |
| 2307 | SET_OP( ldfp32_rrr ); |
| 2308 | goto do_fp_ldst_rrr; |
| 2309 | |
| 2310 | case T3o3_lddf: |
| 2311 | RESCALEFPREG(rd); |
| 2312 | SET_OP( ldfp64_rrr ); |
| 2313 | goto do_fp_ldst_rrr; |
| 2314 | |
| 2315 | case T3o3_ldqf: |
| 2316 | SET_OP_ILL_REASON(illegal_instruction); |
| 2317 | goto illegal_instruction; |
| 2318 | |
| 2319 | case T3o3_stf: |
| 2320 | rd = FP_32_INDX(rd); |
| 2321 | SET_OP( stfp32_rrr ); |
| 2322 | goto do_fp_ldst_rrr; |
| 2323 | |
| 2324 | case T3o3_stdf: |
| 2325 | RESCALEFPREG(rd); |
| 2326 | SET_OP( stfp64_rrr ); |
| 2327 | goto do_fp_ldst_rrr; |
| 2328 | |
| 2329 | case T3o3_stqf: |
| 2330 | SET_OP_ILL_REASON(illegal_instruction); |
| 2331 | goto illegal_instruction; |
| 2332 | |
| 2333 | case T3o3_ldfsr: |
| 2334 | switch (rd) { |
| 2335 | case 0: |
| 2336 | SET_OPv9( ldfsr_rr ); |
| 2337 | break; |
| 2338 | case 1: |
| 2339 | SET_OPv9( ldxfsr_rr ); |
| 2340 | break; |
| 2341 | default: |
| 2342 | SET_OP_ILL_REASON(illegal_fsr_specifier); |
| 2343 | goto illegal_instruction; |
| 2344 | } |
| 2345 | goto do_fp_fsr_rr; |
| 2346 | |
| 2347 | case T3o3_stfsr: |
| 2348 | switch (rd) { |
| 2349 | case 0: |
| 2350 | SET_OPv9( stfsr_rr ); |
| 2351 | break; |
| 2352 | case 1: |
| 2353 | SET_OPv9( stxfsr_rr ); |
| 2354 | break; |
| 2355 | default: |
| 2356 | SET_OP_ILL_REASON(illegal_fsr_specifier); |
| 2357 | goto illegal_instruction; |
| 2358 | } |
| 2359 | goto do_fp_fsr_rr; |
| 2360 | |
| 2361 | case T3o3_ldfa: |
| 2362 | FP_DECODE_FPU_ON_CHECK; |
| 2363 | SET_OP_ASI_OP(MA_ldfp32); |
| 2364 | SET_OPv9(fp64asi_rrr); |
| 2365 | goto do_asi_rrr; |
| 2366 | |
| 2367 | case T3o3_stfa: |
| 2368 | FP_DECODE_FPU_ON_CHECK; |
| 2369 | SET_OP_ASI_OP(MA_stfp32); |
| 2370 | SET_OPv9(fp64asi_rrr); |
| 2371 | goto do_asi_rrr; |
| 2372 | |
| 2373 | case T3o3_ldqfa: |
| 2374 | case T3o3_stqfa: |
| 2375 | SET_OP_ILL_REASON(illegal_instruction); |
| 2376 | goto illegal_instruction; |
| 2377 | |
| 2378 | case T3o3_lddfa: |
| 2379 | FP_DECODE_FPU_ON_CHECK; |
| 2380 | SET_OP_ASI_OP(MA_ldfp64); |
| 2381 | SET_OPv9(fp64asi_rrr); |
| 2382 | goto do_fp_asi_rrr; |
| 2383 | case T3o3_stdfa: |
| 2384 | FP_DECODE_FPU_ON_CHECK; |
| 2385 | SET_OP_ASI_OP(MA_stfp64); |
| 2386 | SET_OPv9(fp64asi_rrr); |
| 2387 | goto do_fp_asi_rrr; |
| 2388 | |
| 2389 | case T3o3_prefetch: |
| 2390 | case T3o3_prefetcha: |
| 2391 | goto do_noop; |
| 2392 | |
| 2393 | case T3o3_swapa: |
| 2394 | SET_OP_ASI_OP(MA_swap); |
| 2395 | SET_OPv9(asi_num); |
| 2396 | goto do_asi_rrr; |
| 2397 | |
| 2398 | default: |
| 2399 | goto unknown_decode; /* FIXME */ |
| 2400 | } |
| 2401 | } |
| 2402 | } |
| 2403 | goto unknown_decode; /* Could be CPU specific instruction. */ |
| 2404 | |
| 2405 | unknown_decode:; /* We can reach here if either the decoder screwed up (Even illegal */ |
| 2406 | /* instructions should have a proper decode case) or we encountered */ |
| 2407 | /* a CPU specific instruction which the SparcV9 decoder doesn't */ |
| 2408 | /* know about. We check to see which of those two cases happened in */ |
| 2409 | /* the illegal instruction handling code below. */ |
| 2410 | |
| 2411 | SET_OP_ILL_REASON(unknown_instruction); |
| 2412 | goto illegal_instruction; |
| 2413 | |
| 2414 | /* |
| 2415 | * Sparc allows us to not decode FP ops when there is no floating point |
| 2416 | * unit. So in this case we deliver a fp_disabled trap ... |
| 2417 | */ |
| 2418 | |
| 2419 | #ifdef FP_DECODE_DISABLED |
| 2420 | fp_disabled:; |
| 2421 | #endif /* FP_DECODE_DISABLED */ |
| 2422 | unimplemented_fpop:; |
| 2423 | SET_OPv9(fp_unimplemented_instruction); |
| 2424 | goto all_done; |
| 2425 | |
| 2426 | |
| 2427 | /* FP version of unknown_decode. */ |
| 2428 | unknown_fp_decode:; |
| 2429 | SET_OP_ILL_REASON(unknown_fp_instruction); |
| 2430 | SET_OPv9(fp_unimplemented_instruction); |
| 2431 | goto try_proc_specific; |
| 2432 | |
| 2433 | |
| 2434 | #ifdef PROCESSOR_SUPPORTS_QUADFP |
| 2435 | invalid_fp_register: |
| 2436 | SET_OPv9(fp_invalidreg_instruction); |
| 2437 | goto all_done; |
| 2438 | #endif |
| 2439 | |
| 2440 | |
| 2441 | |
| 2442 | unimplemented_visop: |
| 2443 | SET_OP_ILL_REASON(unimplemented_visop); |
| 2444 | goto illegal_instruction; |
| 2445 | |
| 2446 | |
| 2447 | illegal_instruction:; /* we reach here if the decoder detected an illegal instruction*/ |
| 2448 | /* for example - a bpcc instrn with cc0=0 & cc1=1 */ |
| 2449 | /* Or if we have run into a CPU specific instruction which the */ |
| 2450 | /* SparcV9 decoder doesn't know about. */ |
| 2451 | SET_OPv9(illegal_instruction); |
| 2452 | |
| 2453 | try_proc_specific:; |
| 2454 | |
| 2455 | /* |
| 2456 | * Before declaring the instruction illegal or unknown, we check the CPU |
| 2457 | * specific instruction decoder. |
| 2458 | * Since some FP instructions want to return 'unimplemented' |
| 2459 | * instead of 'illegal', preserve whatever has been set until |
| 2460 | * we get a positive decode from the proc-specific decode. |
| 2461 | */ |
| 2462 | p_exec_funcp = sp->config_procp->proc_typep->cpu_decode_me(sp, xcip, instn); |
| 2463 | if (p_exec_funcp != NULL) { |
| 2464 | /* |
| 2465 | * CPU specific instruction decoder was successful. |
| 2466 | */ |
| 2467 | exec_funcp = p_exec_funcp; |
| 2468 | goto all_done; |
| 2469 | } |
| 2470 | |
| 2471 | DBGILLINST( lprintf(sp->gid, "decoded illegal instruction 0x%x " |
| 2472 | "(@PC = 0x%llx) : %s\n", instn, sp->pc, |
| 2473 | v9_illegal_reason_str[(int)xcip->di.ill_reason]);); |
| 2474 | |
| 2475 | DBGDECODE( |
| 2476 | if (xcip->di.ill_reason == unknown_instruction) { |
| 2477 | fprintf(stderr, "Error! : unable to decode instruction " |
| 2478 | "(PC = 0x%llx in mode %s) 0x%x\n", sp->pc, |
| 2479 | sparcv9_state_name[((sparcv9_cpu_t *) |
| 2480 | (sp->specificp))->state], instn); |
| 2481 | abort(); /* shouldnt get here*/ |
| 2482 | } |
| 2483 | ); |
| 2484 | |
| 2485 | goto all_done; |
| 2486 | |
| 2487 | |
| 2488 | |
| 2489 | /* |
| 2490 | * Setup and tests for decoded floating point instructions |
| 2491 | */ |
| 2492 | do_fp_s1d: |
| 2493 | FP_DECODE_FPU_ON_CHECK; |
| 2494 | RESCALEFPREG(rd); |
| 2495 | SET_OP_FPRD( rd ); |
| 2496 | goto all_done; |
| 2497 | do_fp_s1s: |
| 2498 | FP_DECODE_FPU_ON_CHECK; |
| 2499 | rd = FP_32_INDX(rd); |
| 2500 | SET_OP_FPRD( rd ); |
| 2501 | goto all_done; |
| 2502 | |
| 2503 | #ifdef PROCESSOR_SUPPORTS_QUADFP |
| 2504 | do_fp_s1q_s2q_dq: |
| 2505 | FP_DECODE_FPU_ON_CHECK; |
| 2506 | if (rs1 & 0x2) goto invalid_fp_register; |
| 2507 | do_fp_s2q_dq: |
| 2508 | FP_DECODE_FPU_ON_CHECK; |
| 2509 | if (rs2 & 0x2) goto invalid_fp_register; |
| 2510 | do_fp_s1d_s2d_dq: |
| 2511 | FP_DECODE_FPU_ON_CHECK; |
| 2512 | if (rd & 0x2) goto invalid_fp_register; |
| 2513 | /* Quad not supported yet - FIXME */ |
| 2514 | goto unimplemented_fpop; |
| 2515 | #endif |
| 2516 | |
| 2517 | do_fp_s1d_s2d_dd: |
| 2518 | FP_DECODE_FPU_ON_CHECK; |
| 2519 | RESCALEFPREG(rs1); |
| 2520 | RESCALEFPREG(rs2); |
| 2521 | RESCALEFPREG(rd); |
| 2522 | SET_OP_FPRS1( rs1 ); |
| 2523 | SET_OP_FPRS2( rs2 ); |
| 2524 | SET_OP_FPRD( rd ); |
| 2525 | goto all_done; |
| 2526 | do_fp_s1s_s2s_dd: |
| 2527 | FP_DECODE_FPU_ON_CHECK; |
| 2528 | rs1 = FP_32_INDX(rs1); |
| 2529 | SET_OP_FPRS1( rs1 ); |
| 2530 | rs2 = FP_32_INDX(rs2); |
| 2531 | SET_OP_FPRS2( rs2 ); |
| 2532 | RESCALEFPREG(rd); |
| 2533 | SET_OP_FPRD( rd ); |
| 2534 | goto all_done; |
| 2535 | do_fp_s1s_s2s_ds: |
| 2536 | FP_DECODE_FPU_ON_CHECK; |
| 2537 | rs1 = FP_32_INDX(rs1); |
| 2538 | SET_OP_FPRS1( rs1 ); |
| 2539 | rs2 = FP_32_INDX(rs2); |
| 2540 | SET_OP_FPRS2( rs2 ); |
| 2541 | rd = FP_32_INDX(rd); |
| 2542 | SET_OP_FPRD( rd ); |
| 2543 | goto all_done; |
| 2544 | |
| 2545 | /* |
| 2546 | * For FP ops with a single operand (e.g. abs) SPARC encodes into rs2 |
| 2547 | * I move it into rs1 for my pre-decoded form. |
| 2548 | */ |
| 2549 | do_fp_s1d_dd: |
| 2550 | rs2 = rs1; |
| 2551 | do_fp_s2d_dd: |
| 2552 | FP_DECODE_FPU_ON_CHECK; |
| 2553 | RESCALEFPREG(rs2); |
| 2554 | SET_OP_FPRS1( rs2 ); |
| 2555 | RESCALEFPREG(rd); |
| 2556 | SET_OP_FPRD( rd ); |
| 2557 | goto all_done; |
| 2558 | do_fp_s2d_ds: |
| 2559 | FP_DECODE_FPU_ON_CHECK; |
| 2560 | RESCALEFPREG(rs2); |
| 2561 | SET_OP_FPRS1( rs2 ); |
| 2562 | rd = FP_32_INDX(rd); |
| 2563 | SET_OP_FPRD( rd ); |
| 2564 | goto all_done; |
| 2565 | do_fp_s1s_ds: |
| 2566 | rs2 = rs1; |
| 2567 | do_fp_s2s_ds: |
| 2568 | FP_DECODE_FPU_ON_CHECK; |
| 2569 | rs2 = FP_32_INDX(rs2); |
| 2570 | SET_OP_FPRS1( rs2 ); |
| 2571 | rd = FP_32_INDX(rd); |
| 2572 | SET_OP_FPRD( rd ); |
| 2573 | goto all_done; |
| 2574 | do_fp_s2s_dd: |
| 2575 | FP_DECODE_FPU_ON_CHECK; |
| 2576 | rs2 = FP_32_INDX(rs2); |
| 2577 | SET_OP_FPRS1( rs2 ); |
| 2578 | RESCALEFPREG(rd); |
| 2579 | SET_OP_FPRD( rd ); |
| 2580 | goto all_done; |
| 2581 | |
| 2582 | do_fp_s1d_s2d_cmp: |
| 2583 | FP_DECODE_FPU_ON_CHECK; |
| 2584 | RESCALEFPREG(rs1); |
| 2585 | SET_OP_FPRS1( rs1 ); |
| 2586 | RESCALEFPREG(rs2); |
| 2587 | SET_OP_FPRS2( rs2 ); |
| 2588 | goto all_done; |
| 2589 | do_fp_s1s_s2s_cmp: |
| 2590 | FP_DECODE_FPU_ON_CHECK; |
| 2591 | rs1 = FP_32_INDX(rs1); |
| 2592 | SET_OP_FPRS1( rs1 ); |
| 2593 | rs2 = FP_32_INDX(rs2); |
| 2594 | SET_OP_FPRS2( rs2 ); |
| 2595 | goto all_done; |
| 2596 | |
| 2597 | |
| 2598 | |
| 2599 | do_fp_ldst_imm: |
| 2600 | FP_DECODE_FPU_ON_CHECK; |
| 2601 | SET_OP_FPRD(rd); |
| 2602 | SET_OP_RS1(rs1); |
| 2603 | SET_OP_SIMM16(simm); |
| 2604 | goto all_done; |
| 2605 | do_fp_fsr_imm: |
| 2606 | FP_DECODE_FPU_ON_CHECK; |
| 2607 | SET_OP_RS1(rs1); |
| 2608 | SET_OP_SIMM16(simm); |
| 2609 | goto all_done; |
| 2610 | |
| 2611 | do_fp_ldst_rrr: |
| 2612 | SET_OP_FPRD(rd); |
| 2613 | do_fp_fsr_rr: |
| 2614 | FP_DECODE_FPU_ON_CHECK; |
| 2615 | SET_OP_RS1(rs1); |
| 2616 | SET_OP_RS2(rs2); |
| 2617 | goto all_done; |
| 2618 | |
| 2619 | do_fp_asi_imm: |
| 2620 | FP_DECODE_FPU_ON_CHECK; |
| 2621 | SET_OP_RS1(rs1); |
| 2622 | SET_OP_SIMM16(simm); |
| 2623 | RESCALEFPREG(rd); |
| 2624 | SET_OP_ASI_FPRD(rd); |
| 2625 | goto all_done; |
| 2626 | |
| 2627 | do_fp_asi_rrr: |
| 2628 | FP_DECODE_FPU_ON_CHECK; |
| 2629 | SET_OP_ASI_NUM(X_ASI(instn)); |
| 2630 | SET_OP_RS1(rs1); |
| 2631 | SET_OP_RS2(rs2); |
| 2632 | RESCALEFPREG(rd); |
| 2633 | SET_OP_ASI_FPRD(rd); |
| 2634 | goto all_done; |
| 2635 | |
| 2636 | |
| 2637 | /* |
| 2638 | * Setup for decoded instructions |
| 2639 | */ |
| 2640 | |
| 2641 | |
| 2642 | do_asi_rrr: |
| 2643 | SET_OP_ASI_NUM(X_ASI(instn)); |
| 2644 | do_memop_rrr: |
| 2645 | SET_OP_RS1(rs1); |
| 2646 | SET_OP_RS2(rs2); |
| 2647 | SET_OP_ASI_RD(rd); |
| 2648 | goto all_done; |
| 2649 | |
| 2650 | do_memop_imm: |
| 2651 | do_asi_imm: |
| 2652 | SET_OP_RS1(rs1); |
| 2653 | SET_OP_SIMM16(simm); |
| 2654 | SET_OP_ASI_RD(rd); |
| 2655 | goto all_done; |
| 2656 | |
| 2657 | do_rrr: |
| 2658 | SET_OP_RD(rd); |
| 2659 | SET_OP_RS1(rs1); |
| 2660 | SET_OP_RS2(rs2); |
| 2661 | goto all_done; |
| 2662 | |
| 2663 | do_imm: |
| 2664 | SET_OP_RD(rd); |
| 2665 | SET_OP_RS1(rs1); |
| 2666 | SET_OP_SIMM16(simm); |
| 2667 | goto all_done; |
| 2668 | |
| 2669 | do_move_simm: |
| 2670 | SET_OP( move_simm ); |
| 2671 | SET_OP_RD(rd); |
| 2672 | SET_OP_SIMM32(simm); |
| 2673 | goto all_done; |
| 2674 | |
| 2675 | do_move_reg: |
| 2676 | SET_OP( move_reg ); |
| 2677 | SET_OP_RD(rd); |
| 2678 | SET_OP_RS1(rs1); |
| 2679 | goto all_done; |
| 2680 | |
| 2681 | do_zero_reg: |
| 2682 | SET_OP( zero_reg ); |
| 2683 | SET_OP_RD(rd); |
| 2684 | goto all_done; |
| 2685 | |
| 2686 | do_noop: |
| 2687 | SET_OP( noop ); |
| 2688 | goto all_done; |
| 2689 | |
| 2690 | |
| 2691 | all_done: |
| 2692 | |
| 2693 | |
| 2694 | /* |
| 2695 | * FIXME: This ugly hook is so that we can instruction trace for |
| 2696 | * debugging without penalising the main execution loop. |
| 2697 | * Basically, if debugging is turned on we leverage the same |
| 2698 | * behaviour as for breakpoint support and after dumping the |
| 2699 | * pre-execution state, prevent installation of the exec_func. |
| 2700 | * |
| 2701 | * Why is this a fixme ? This will ultimately done by a trampoline |
| 2702 | * for each instruction we wish to trace .. and will be done on a per |
| 2703 | * simcpu basis rather than globally. Until then we are left with this. |
| 2704 | */ |
| 2705 | DBGELMIN( |
| 2706 | sparcv9_trace_output(sp, instn); |
| 2707 | on_bp = true; |
| 2708 | ); |
| 2709 | /* |
| 2710 | * prevent installation of any instruction |
| 2711 | * that matched a live instruction |
| 2712 | */ |
| 2713 | if (on_bp) { |
| 2714 | xcip->exec_funcp = sp->decodemep; |
| 2715 | } else { |
| 2716 | /* cache for next time around */ |
| 2717 | xcip->exec_funcp = exec_funcp; |
| 2718 | } |
| 2719 | |
| 2720 | /* execute the instruction on behalf of the x-cache */ |
| 2721 | exec_funcp(sp, xcip); |
| 2722 | } |
| 2723 | |
| 2724 | |
| 2725 | |
| 2726 | |