| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: ITYPES.h |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 7 | * |
| 8 | * The above named program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public |
| 10 | * License version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * The above named program is distributed in the hope that it will be |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public |
| 18 | * License along with this work; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 20 | * |
| 21 | * ========== Copyright Header End ============================================ |
| 22 | */ |
| 23 | /* %COPYRIGHT% */ |
| 24 | |
| 25 | #ifndef _ITYPES_H |
| 26 | #define _ITYPES_H |
| 27 | |
| 28 | #pragma ident "@(#)ITYPES.h 1.1" |
| 29 | |
| 30 | #include "spix_sparc.h" |
| 31 | //#include "IHASH.h" |
| 32 | #include "INSTR.h" |
| 33 | |
| 34 | #ifdef __cplusplus |
| 35 | extern "C" { |
| 36 | #endif |
| 37 | |
| 38 | // ==== Instruction classification functions ==== |
| 39 | |
| 40 | // True for valid instructions. Returns false if ih >= NIHASH. |
| 41 | int ih_isvalid(int ih); |
| 42 | |
| 43 | int ih_isnone(int ih); |
| 44 | |
| 45 | // ==== Memory access ==== |
| 46 | |
| 47 | // True for instructions that load a value from memory. This |
| 48 | // includes all integer load instruc- tions, all FP load |
| 49 | // instructions, and all atomic load/store instructions. |
| 50 | int ih_isload(int ih); |
| 51 | |
| 52 | // True for instructions that load a value from memory into an |
| 53 | // integer register. This includes all atomic load/store |
| 54 | // instructions. |
| 55 | int ih_isiload(int ih); |
| 56 | |
| 57 | // True for instructions that unconditionally store a value to |
| 58 | // memory. This includes all integer store instructions, all FP |
| 59 | // store instructions, and the LDSTUB, LDSTUBA, SWAP, and SWAPA |
| 60 | // atomic load/store instructions. |
| 61 | int ih_isustore(int ih); |
| 62 | |
| 63 | // True for instructions that conditionally store a value to |
| 64 | // memory. This includes the CASA and CASXA instructions. |
| 65 | int ih_iscstore(int ih); |
| 66 | |
| 67 | // True for instructions that conditionally or unconditionally |
| 68 | // store a value from an integer register into memory. This |
| 69 | // includes all atomic load/store instructions. |
| 70 | int ih_isistore(int ih); |
| 71 | |
| 72 | // True for instructions that conditionally or unconditionally |
| 73 | // store any value into memory. This includes all atomic load/store |
| 74 | // instructions. |
| 75 | int ih_isstore(int ih); |
| 76 | |
| 77 | // ==== Integer arithmetic ==== |
| 78 | |
| 79 | // True for instructions that perform an integer arithmetic or |
| 80 | // logical operation. This does not include load, store, branch, |
| 81 | // or floating point instructions. |
| 82 | int ih_isalu(int ih); |
| 83 | |
| 84 | // ==== Control Transfer ==== |
| 85 | |
| 86 | // True if JMPL appears to function as register-indirect CALL. |
| 87 | int ih_isjmplcall(unsigned instr, int ih); |
| 88 | |
| 89 | // True if JMPL appears to return from subroutine. |
| 90 | int ih_isjmplreturn(unsigned instr, int ih); |
| 91 | |
| 92 | // True for CALL's and JMPL's calling subroutines. |
| 93 | int ih_iscall(unsigned instr, int ih); |
| 94 | |
| 95 | // True for RETURN's and JMPL's returning from subroutines. |
| 96 | int ih_isreturn(unsigned instr, int ih); |
| 97 | |
| 98 | // True for CALL, JMPL, and RETURN instructions. |
| 99 | int ih_isproc(int ih); |
| 100 | |
| 101 | // True for TCC instructions. |
| 102 | int ih_isticc(int ih); |
| 103 | |
| 104 | // True for delayed control transfer instructions. |
| 105 | int ih_isdcti(int ih); |
| 106 | |
| 107 | // True for CTI instructions. This includes all DCTI, TCC, DONE, |
| 108 | // and RETRY instructions. |
| 109 | int ih_iscti(int ih); |
| 110 | |
| 111 | // True for branch instructions with the annul bit set. |
| 112 | int ih_isannul(int ih); |
| 113 | |
| 114 | // True for conditional branch instructions, whether on the |
| 115 | // "always" condition, the "never" condition, or any other |
| 116 | // condition. Note, this type is the union of the isubranch() and |
| 117 | // is_cbranch() members below. |
| 118 | int ih_isbranch(int ih); |
| 119 | |
| 120 | // True for unconditional branch instructions. This includes only |
| 121 | // conditional branch instructions on the "always" condition. |
| 122 | // Note, it does not include CALL, JMPL, or RETURN instructions. |
| 123 | int ih_isuncond(int ih); |
| 124 | |
| 125 | // True for conditional branch instructions. This includes |
| 126 | // conditional branch instructions on any condition other than |
| 127 | // "always". |
| 128 | int ih_iscbranch(int ih); |
| 129 | |
| 130 | // True for conditional branches on the "always" condition that |
| 131 | // also have the "annul" attribute set. |
| 132 | int ih_isbaa(int ih); |
| 133 | |
| 134 | // True for non-predicted branch instructions that are contingent |
| 135 | // on the integer condition codes. |
| 136 | int ih_isbicc(int ih); |
| 137 | |
| 138 | // True for predicted branch instructions that are contingent on |
| 139 | // the integer condition codes. |
| 140 | int ih_isbpcc(int ih); |
| 141 | |
| 142 | // True for branch instructions that are contingent on the value |
| 143 | // of a register. |
| 144 | int ih_isbpr(int ih); |
| 145 | |
| 146 | // True for non-predicted branch instructions that are contingent |
| 147 | // on the floating point condition codes. |
| 148 | int ih_isfbfcc(int ih); |
| 149 | |
| 150 | // True for predicted branch instructions that are contingent on |
| 151 | // the floating point condition codes. |
| 152 | int ih_isfbpfcc(int ih); |
| 153 | |
| 154 | // ==== Conditional move ==== |
| 155 | |
| 156 | // True for conditional integer register move instructions that |
| 157 | // are contingent on either the integer or floating point |
| 158 | // condition codes. |
| 159 | int ih_ismovcc(int ih); |
| 160 | |
| 161 | // True for conditional integer register move instructions that |
| 162 | // are contingent on the value of a register. |
| 163 | int ih_ismovr(int ih); |
| 164 | |
| 165 | // True for conditional floating point register move instructions |
| 166 | // that are contingent on either the integer or floating point |
| 167 | // condition codes. |
| 168 | int ih_isfmovcc(int ih); |
| 169 | |
| 170 | // True for conditional floating point register move instructions |
| 171 | // that are contingent on the value of a register. |
| 172 | int ih_isfmovr(int ih); |
| 173 | |
| 174 | // ==== Floating point operations ==== |
| 175 | |
| 176 | // True for floating point instructions. This includes all FPOP1 |
| 177 | // and FPOP2 instructions, all loads or stores to floating point |
| 178 | // registers (including the %fsr register), the FBfcc and FBPfcc |
| 179 | // instructions, the MOVcc instructions that use the %fcc |
| 180 | // conditions, and all UltraSPARC extended "vis" instructions |
| 181 | // (including those that do not use floating point registers). |
| 182 | int ih_isfp(int ih); |
| 183 | |
| 184 | // True for FPOP1 instructions as defined by the SPARC |
| 185 | // Architecture Manual. |
| 186 | int ih_isfpop1(int ih); |
| 187 | |
| 188 | // ==== Condition code modifiers ==== |
| 189 | |
| 190 | // True for instructions that use either the %xcc or %icc |
| 191 | // condition codes. This includes the RDCCR instruction. |
| 192 | int ih_isuseccr(int ih); |
| 193 | |
| 194 | // True for instructions that set either the %xcc or %icc |
| 195 | // condition codes. This includes the WRCCR instruction. |
| 196 | int ih_issetccr(int ih); |
| 197 | |
| 198 | // True for instructions that set any of the floating point |
| 199 | // condition codes. This includes the LDFSR and LDXFSR |
| 200 | // instructions. |
| 201 | int ih_issetfcc(int ih); |
| 202 | |
| 203 | // ==== Architecture specific ==== |
| 204 | |
| 205 | // True for instructions that are defined for the SPARC V8 |
| 206 | // architecture. |
| 207 | int ih_isv8(int ih); |
| 208 | |
| 209 | // True for instructions that are defined for the SPARC V9 |
| 210 | // architecture. (It does not include any of the UltraSPARC |
| 211 | // extended instructions.) |
| 212 | int ih_isv9(int ih); |
| 213 | |
| 214 | // True for the UltraSPARC extended "vis" instructions. |
| 215 | int ih_isvis(int ih); |
| 216 | |
| 217 | // ==== Privileged instructions ==== |
| 218 | |
| 219 | // True for the privileged instructions. It does not select |
| 220 | // instructions that are privileged only for certain operands |
| 221 | // (such as RDASR) or that are only privileged depending on the |
| 222 | // processor's configuration (such as RDTICK). |
| 223 | int ih_ispriv(int ih); |
| 224 | |
| 225 | // ==== ???? ==== |
| 226 | |
| 227 | int ih_isfpcvt(int ih); |
| 228 | |
| 229 | int ih_isany(int ih); |
| 230 | |
| 231 | #ifdef __cplusplus |
| 232 | } |
| 233 | #endif |
| 234 | |
| 235 | #endif /* _ITYPES_H */ |