| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: N2_Core.h |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 7 | * |
| 8 | * The above named program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public |
| 10 | * License version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * The above named program is distributed in the hope that it will be |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public |
| 18 | * License along with this work; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 20 | * |
| 21 | * ========== Copyright Header End ============================================ |
| 22 | */ |
| 23 | #ifndef __N2_Core_h__ |
| 24 | #define __N2_Core_h__ |
| 25 | |
| 26 | #include <vector> |
| 27 | #include "SS_Node.h" |
| 28 | #include "N2_Tlb.h" |
| 29 | #include "N2_Cpu.h" |
| 30 | |
| 31 | /* RAS */ |
| 32 | #include "MemoryTransaction.h" |
| 33 | #include "N2_MemErrDetector.h" |
| 34 | #include "N2_RasState.h" |
| 35 | |
| 36 | |
| 37 | class N2_Strand; |
| 38 | class N2_MemErrDetector; |
| 39 | |
| 40 | class N2_Core : public SS_Node |
| 41 | { |
| 42 | public: |
| 43 | N2_Core( N2_Cpu& cpu, const char* _name, uint_t strand_id_base ); |
| 44 | ~N2_Core(); |
| 45 | |
| 46 | void hard_reset(); |
| 47 | void warm_reset(bool intp=true); |
| 48 | |
| 49 | void snapshot( SS_SnapShot& ss ); |
| 50 | |
| 51 | N2_Cpu& cpu; |
| 52 | |
| 53 | N2_Strand* strand[N2_Model::NO_STRANDS_PER_CORE]; |
| 54 | N2_Tlb inst_tlb; |
| 55 | N2_Tlb data_tlb; |
| 56 | N2_PowerMgmt power_mgmt; |
| 57 | N2_ErrorInject error_inject; |
| 58 | N2_Decr decr; |
| 59 | N2_Dfesr dfesr; |
| 60 | N2_Cerer cerer; |
| 61 | N2_Clesr clesr; |
| 62 | N2_Clesr clfesr; |
| 63 | N2_InstMask inst_iw[2]; // Strands 0-3 use inst_iw[0] and 4-7 use inst_iw[1] |
| 64 | N2_InstWp inst_wp[2]; // Strands 0-3 use inst_wp[0] and 4-7 use inst_wp[1] |
| 65 | N2_LsuDiag lsu_diag; |
| 66 | N2_TwStatus tw_status; |
| 67 | |
| 68 | |
| 69 | /* RAS routines */ |
| 70 | SS_Trap::Type icache_ifetch(const MemoryTransaction &memXact, |
| 71 | bool trap_enabled, |
| 72 | uint32_t strand_id, |
| 73 | N2_MemErrDetector *mem_err_detector); |
| 74 | |
| 75 | bool icache_empty; |
| 76 | |
| 77 | SS_Trap::Type dcache_trans(const MemoryTransaction &memXact, |
| 78 | bool trap_enabled, |
| 79 | uint32_t strand_id, |
| 80 | bool store_id, |
| 81 | N2_MemErrDetector *mem_err_detector); |
| 82 | |
| 83 | bool dcache_empty; |
| 84 | |
| 85 | void flush_icache(uint64_t paddr); |
| 86 | void flush_dcache(uint64_t paddr); |
| 87 | |
| 88 | // Flush all the decode caches associated with this core. |
| 89 | void flush_tte_all(); |
| 90 | |
| 91 | void update_clesr(int sid, int isDesr, uint64_t value); |
| 92 | |
| 93 | std::map<uint64_t,N2_IcacheInstrStReg> icacheInstr; |
| 94 | std::map<uint64_t,N2_DcacheDataStReg> dcacheData; |
| 95 | std::map<uint64_t,N2_DcacheTagLdReg> dcacheTag; |
| 96 | |
| 97 | void ras_enable(char*); |
| 98 | |
| 99 | private: |
| 100 | |
| 101 | static SS_AsiSpace::Error inst_iw_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* ); |
| 102 | static SS_AsiSpace::Error inst_iw_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t ); |
| 103 | static SS_AsiSpace::Error inst_wp_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* ); |
| 104 | static SS_AsiSpace::Error inst_wp_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t ); |
| 105 | static SS_AsiSpace::Error icache_tag_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* ); |
| 106 | static SS_AsiSpace::Error icache_tag_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t ); |
| 107 | static SS_AsiSpace::Error icache_data_ld64( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* ); |
| 108 | static SS_AsiSpace::Error icache_data_st64( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t ); |
| 109 | static SS_AsiSpace::Error dcache_tag_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* ); |
| 110 | static SS_AsiSpace::Error dcache_tag_st64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t ); |
| 111 | static SS_AsiSpace::Error dcache_data_ld64( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* ); |
| 112 | static SS_AsiSpace::Error dcache_data_st64( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t ); |
| 113 | static SS_AsiSpace::Error tw_status_ld64 ( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t* ); |
| 114 | static SS_AsiSpace::Error error_inject_st64( SS_Node*, void*, SS_Strand*, SS_Vaddr, uint64_t ); |
| 115 | |
| 116 | /* RAS */ |
| 117 | |
| 118 | uint32_t search_icache_tags(N2_IcacheAddressingFields paddr,int32_t &hit_way); |
| 119 | uint32_t search_dcache_tags(N2_DcacheAddressingFields paddr,int32_t &hit_way); |
| 120 | uint32_t calc_dcache_parity(N2_DcacheDiagDataLdAddrFields addr); |
| 121 | |
| 122 | // The N2_IcacheTagLdRegArray stores the icache diagnostics tag |
| 123 | // array in a vector for fast access. |
| 124 | class N2_IcacheTagLdRegArray |
| 125 | { |
| 126 | public: |
| 127 | N2_IcacheTagLdRegArray() : array_(VECTOR_SIZE) {} |
| 128 | virtual ~N2_IcacheTagLdRegArray() {} |
| 129 | |
| 130 | N2_IcacheTagLdReg get(N2_IcacheDiagTagAddrFields addr) |
| 131 | { |
| 132 | addr.vb_err_en(0); |
| 133 | addr.perren(0); |
| 134 | return array_[addr() >> N2_IcacheDiagTagAddrFields::bit_size_rsvd0]; |
| 135 | } |
| 136 | |
| 137 | void set(N2_IcacheDiagTagAddrFields addr,const N2_IcacheTagLdReg &data) |
| 138 | { |
| 139 | addr.vb_err_en(0); |
| 140 | addr.perren(0); |
| 141 | N2_IcacheTagLdReg ® = |
| 142 | array_[addr() >> N2_IcacheDiagTagAddrFields::bit_size_rsvd0]; |
| 143 | |
| 144 | reg = data; |
| 145 | } |
| 146 | |
| 147 | static const uint64_t N2_IcacheTagLdRegArray::VECTOR_SIZE = |
| 148 | 1 << (N2_IcacheDiagTagAddrFields::bit_size_rsvd0 + |
| 149 | N2_IcacheDiagTagAddrFields::bit_size_index + |
| 150 | N2_IcacheDiagTagAddrFields::bit_size_way); |
| 151 | |
| 152 | std::vector<N2_IcacheTagLdReg> array_; |
| 153 | }; |
| 154 | |
| 155 | |
| 156 | uint64_t icache_lru; |
| 157 | uint64_t dcache_lru; |
| 158 | |
| 159 | public: |
| 160 | N2_IcacheTagLdRegArray icacheTag; |
| 161 | }; |
| 162 | |
| 163 | #endif |
| 164 | |