| 1 | <!-- interpreter=xml2reg args='-t' --> |
| 2 | <register_list> |
| 3 | <register name="SOC_ERROR_STEERING_REG (SOC_ERROR_STEERING_REG)"> |
| 4 | <class_name>N2_SocErrorSteeringReg</class_name> |
| 5 | <submodule>N2</submodule> |
| 6 | <comment> |
| 7 | SOC Error Steering Register. This register controls which virtual core |
| 8 | will be sent SOC error interrupts. TABLE 12-53 shows the format of |
| 9 | the SOC Error Steering Register. TABLE 12-53 SOC Error Steering Register - SOC_ERROR_STEERING_REG (0x90-0104-1000) |
| 10 | </comment> |
| 11 | <base_address>0x9001041000ULL</base_address> |
| 12 | <count>1</count> |
| 13 | <stride>8</stride> |
| 14 | <priv>yes</priv> |
| 15 | <field name="RSVD"> |
| 16 | <start_offset>6</start_offset> |
| 17 | <end_offset>63</end_offset> |
| 18 | <initial_value>0</initial_value> |
| 19 | <protection>RO</protection> |
| 20 | <field_type>ZERO</field_type> |
| 21 | <comment> |
| 22 | Reserved |
| 23 | </comment> |
| 24 | </field> |
| 25 | <field name="VCID"> |
| 26 | <start_offset>0</start_offset> |
| 27 | <end_offset>5</end_offset> |
| 28 | <initial_value>0</initial_value> |
| 29 | <protection>RW</protection> |
| 30 | <field_type>NORMAL</field_type> |
| 31 | <comment> |
| 32 | ID of virtual core that will be the target of SOC error interrupts. |
| 33 | </comment> |
| 34 | <format type="hex"/> |
| 35 | </field> |
| 36 | </register> |
| 37 | </register_list> |