| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: SS_Ram.cc |
| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 6 | // |
| 7 | // The above named program is free software; you can redistribute it and/or |
| 8 | // modify it under the terms of the GNU General Public |
| 9 | // License version 2 as published by the Free Software Foundation. |
| 10 | // |
| 11 | // The above named program is distributed in the hope that it will be |
| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | // General Public License for more details. |
| 15 | // |
| 16 | // You should have received a copy of the GNU General Public |
| 17 | // License along with this work; if not, write to the Free Software |
| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 19 | // |
| 20 | // ========== Copyright Header End ============================================ |
| 21 | |
| 22 | #include <sys/socket.h> |
| 23 | #include <unistd.h> |
| 24 | #include "SS_Ram.h" |
| 25 | |
| 26 | SS_Ram::SS_Ram( SS_AddressMap* map, SS_Paddr lo, SS_Paddr hi )/*{{{*/ |
| 27 | : |
| 28 | base(lo), |
| 29 | ram(&SS_Memory::memory) |
| 30 | { |
| 31 | map->add(lo,hi,this,SS_AddressMap::REL,SS_Ram::access); |
| 32 | } |
| 33 | /*}}}*/ |
| 34 | SS_Ram::~SS_Ram()/*{{{*/ |
| 35 | { |
| 36 | } |
| 37 | /*}}}*/ |
| 38 | |
| 39 | void SS_Ram::access( void* obj, uint_t sid, SS_Access::Type type, SS_Paddr pa, uint_t size, uint64_t* data )/*{{{*/ |
| 40 | { |
| 41 | SS_Ram* self = (SS_Ram*)obj; |
| 42 | |
| 43 | pa += self->base; |
| 44 | |
| 45 | switch (type) |
| 46 | { |
| 47 | case SS_Access::LOAD: |
| 48 | switch (size) |
| 49 | { |
| 50 | case 1: *data = self->ram->ld8u(pa); break; |
| 51 | case 2: *data = self->ram->ld16u(pa); break; |
| 52 | case 4: *data = self->ram->ld32u(pa); break; |
| 53 | case 8: *data = self->ram->ld64(pa); break; |
| 54 | case 16: self->ram->ld128(pa,data); break; |
| 55 | case 64: self->ram->ld512(pa,data); break; |
| 56 | default: assert(0); |
| 57 | } |
| 58 | break; |
| 59 | case SS_Access::STORE: |
| 60 | switch (size) |
| 61 | { |
| 62 | case 1: self->ram->st8(pa,*data); break; |
| 63 | case 2: self->ram->st16(pa,*data); break; |
| 64 | case 4: self->ram->st32(pa,*data); break; |
| 65 | case 8: self->ram->st64(pa,*data); break; |
| 66 | case 16: self->ram->st128(pa,data); break; |
| 67 | case 64: self->ram->st512(pa,data); break; |
| 68 | default: assert(0); |
| 69 | } |
| 70 | break; |
| 71 | case SS_Access::STP: |
| 72 | assert(size == 8); |
| 73 | self->ram->st64partial(pa,data[0],data[1]); |
| 74 | break; |
| 75 | case SS_Access::SWAP: |
| 76 | assert(size == 4); |
| 77 | *data = self->ram->swap(pa,*data); |
| 78 | break; |
| 79 | case SS_Access::LDST: |
| 80 | assert(size == 1); |
| 81 | *data = self->ram->ldstub(pa); |
| 82 | break; |
| 83 | case SS_Access::CAS: |
| 84 | switch (size) |
| 85 | { |
| 86 | case 4: *data = self->ram->cas(pa,data[0],data[1]); break; |
| 87 | case 8: *data = self->ram->casx(pa,data[0],data[1]); break; |
| 88 | default: assert(0); |
| 89 | } |
| 90 | break; |
| 91 | default: |
| 92 | fprintf(stderr,"ROM: Invalid access detected\n"); |
| 93 | assert(0); |
| 94 | } |
| 95 | } |
| 96 | /*}}}*/ |
| 97 | |
| 98 | |
| 99 | |
| 100 | |
| 101 | |