| 1 | # ========== Copyright Header Begin ========================================== |
| 2 | # |
| 3 | # OpenSPARC T2 Processor File: SS_StateSrf.py |
| 4 | # Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 5 | # DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 6 | # |
| 7 | # The above named program is free software; you can redistribute it and/or |
| 8 | # modify it under the terms of the GNU General Public |
| 9 | # License version 2 as published by the Free Software Foundation. |
| 10 | # |
| 11 | # The above named program is distributed in the hope that it will be |
| 12 | # useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 14 | # General Public License for more details. |
| 15 | # |
| 16 | # You should have received a copy of the GNU General Public |
| 17 | # License along with this work; if not, write to the Free Software |
| 18 | # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 19 | # |
| 20 | # ========== Copyright Header End ============================================ |
| 21 | |
| 22 | from SS_State import * |
| 23 | |
| 24 | ctr_regs = [ |
| 25 | SS_CtrReg('SS','strand_id' , 'sim', 0,OOOOOO, 16, |
| 26 | [ |
| 27 | ]) |
| 28 | , SS_CtrReg('SS','max_wp' , 'sim', 1,OOOOOO, 8, |
| 29 | [ |
| 30 | ]) |
| 31 | , SS_CtrReg('SS','max_tl' , 'sim', 2,OOOOOO, 8, |
| 32 | [ |
| 33 | ]) |
| 34 | , SS_CtrReg('SS','max_ptl' , 'sim', 3,OOOOOO, 8, |
| 35 | [ |
| 36 | ]) |
| 37 | , SS_CtrReg('SS','max_gl' , 'sim', 4,OOOOOO, 8, |
| 38 | [ |
| 39 | ]) |
| 40 | , SS_CtrReg('SS','max_pgl' , 'sim', 5,OOOOOO, 8, |
| 41 | [ |
| 42 | ]) |
| 43 | , SS_CtrReg('SS','va_bits' , 'sim', 6,OOOOOO, 8, |
| 44 | [ |
| 45 | # The size of the virtual (real) address in bits |
| 46 | ]) |
| 47 | , SS_CtrReg('SS','pa_bits' , 'sim', 7,OOOOOO, 8, |
| 48 | [ |
| 49 | # The size of the physical address in bits |
| 50 | ]) |
| 51 | , SS_CtrReg('SS','rstv_addr' , 'sim', 8,OOOOOO,64, |
| 52 | [ |
| 53 | ('',16,63, RW, X) |
| 54 | ]) |
| 55 | , SS_CtrReg('SS','npc' , 'sim', 9,OOOOOO,64, |
| 56 | [ |
| 57 | ('', 2,63, RW, X) |
| 58 | ]) |
| 59 | , SS_CtrReg('SS','fsr' , 'sim',10,OOOOOO,64, |
| 60 | [ |
| 61 | ('cexc' , 0, 4,RW,0), |
| 62 | ('nxc' , 0, 0,RW,0), |
| 63 | ('dzc' , 1, 1,RW,0), |
| 64 | ('ufc' , 2, 2,RW,0), |
| 65 | ('ofc' , 3, 3,RW,0), |
| 66 | ('nvc' , 4, 4,RW,0), |
| 67 | |
| 68 | ('aexc' , 5, 9,RW,0), |
| 69 | ('nxa' , 5, 5,RW,0), |
| 70 | ('dza' , 6, 6,RW,0), |
| 71 | ('ufa' , 7, 7,RW,0), |
| 72 | ('ofa' , 8, 8,RW,0), |
| 73 | ('nva' , 9, 9,RW,0), |
| 74 | |
| 75 | ('fcc0' ,10,11,RW,0), |
| 76 | ('qne' ,13,13,RO,0), |
| 77 | ('ftt' ,14,16,RW,0), |
| 78 | ('ver' ,17,19,RO,0), |
| 79 | ('ns' ,22,22,RW,0), |
| 80 | |
| 81 | ('tem' ,23,27,RW,0), |
| 82 | ('nxm' ,23,23,RW,0), |
| 83 | ('dzm' ,24,24,RW,0), |
| 84 | ('ufm' ,25,25,RW,0), |
| 85 | ('ofm' ,26,26,RW,0), |
| 86 | ('nvm' ,27,27,RW,0), |
| 87 | |
| 88 | ('rd' ,30,31,RW,0), |
| 89 | ('fcc1' ,32,33,RW,0), |
| 90 | ('fcc2' ,34,35,RW,0), |
| 91 | ('fcc3' ,36,37,RW,0) |
| 92 | ]) |
| 93 | , SS_CtrReg('SS','sim_state' , 'sim',11,OOOOOO,64, |
| 94 | [ |
| 95 | # priv = pstate.priv + hpstate.hpriv * 2 |
| 96 | ('priv' , 0, 1, RW, X), |
| 97 | |
| 98 | # red = hpstate.red |
| 99 | ('red' , 2, 2, RW, X), |
| 100 | |
| 101 | # mode = priv and red bits together |
| 102 | ('mode' , 0, 2, RO, X), |
| 103 | |
| 104 | # lsu_ctr.im or inst mmu enabled |
| 105 | ('inst_mmu' , 3, 3, RW, X), |
| 106 | |
| 107 | # lsu_ctr.dm or data mmu enabled |
| 108 | ('data_mmu' , 4, 4, RW, X), |
| 109 | |
| 110 | # fp_disabled = fprs.pef & pstate.fef |
| 111 | ('fp_disabled' , 5, 5, RW, X), |
| 112 | |
| 113 | # ib_enabled = hpstate.ibe if available else the value of |
| 114 | # ibe_sig below when set by some event |
| 115 | ('ib_enabled' , 6, 6, RW, X), |
| 116 | |
| 117 | # ibe_sig(): signal instr break enable : ibe_sig = sgn->ib_enable; |
| 118 | # Used by processors the removed hpstate.ibe |
| 119 | ('ibe_sig' , 7, 7, RW, X), |
| 120 | |
| 121 | # irq_pending is set when an intrrupt has been found and is signalled |
| 122 | ('irq_pending' , 8, 8, RW, X), |
| 123 | |
| 124 | # running = cmp running status |
| 125 | ('running' , 9, 9, RW, X), |
| 126 | |
| 127 | # cosim = set to 1 when we're in cosim mode |
| 128 | ('cosim' ,10,10, RW, X), |
| 129 | |
| 130 | # XIR at tl == maxtl behaviour was changed late 2005. N2 |
| 131 | # does not go through error state on maxtl. |
| 132 | ('xir_error_state', 12,12, RW, X), |
| 133 | |
| 134 | # exec_driven is true when tools like xx use Vonk |
| 135 | ('exec_driven', 13,13, RW, 0), |
| 136 | |
| 137 | # ras_enabled is true when Vonk is doing all sort if RAS checks |
| 138 | ('ras_enabled' ,14,14, RW, 0), |
| 139 | |
| 140 | # trap_taken is true when some part of execute resulted in a trap |
| 141 | ('trap_taken' ,15,15, RW, X), |
| 142 | |
| 143 | # red_tl = tl value when in red state |
| 144 | ('red_tl' ,16,18, RW, X), |
| 145 | |
| 146 | # use_victim_tlb = set to 1 when victim tlb is turned on |
| 147 | # should be set only if cosim() is turned on and tlb trap follow-me |
| 148 | # is being used |
| 149 | # Currently, the plan is to use it only in. May be used in other |
| 150 | # places if needed by RTL-cosim strategy |
| 151 | ('use_victim_tlb',19,19, RW, X), |
| 152 | |
| 153 | # tlb_slamming is set to 1 to enable tlb initialization to run a diag |
| 154 | ('tlb_slamming',20,20, RW, X), |
| 155 | |
| 156 | # hintp_bit0_clear when set clear hintp.hsp bit on hstick match trap |
| 157 | ('hintp_hsp_clear',21,21,RW,X) |
| 158 | |
| 159 | ]) |
| 160 | , SS_CtrReg('SS','inst_count','sim',12,OOOOOO,64, |
| 161 | [ |
| 162 | # count number instructions executed on strand |
| 163 | ]) |
| 164 | ] |