| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * Hypervisor Software File: cache.h |
| 5 | * |
| 6 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 7 | * |
| 8 | * - Do no alter or remove copyright notices |
| 9 | * |
| 10 | * - Redistribution and use of this software in source and binary forms, with |
| 11 | * or without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistribution of source code must retain the above copyright notice, |
| 15 | * this list of conditions and the following disclaimer. |
| 16 | * |
| 17 | * - Redistribution in binary form must reproduce the above copyright notice, |
| 18 | * this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * |
| 21 | * Neither the name of Sun Microsystems, Inc. or the names of contributors |
| 22 | * may be used to endorse or promote products derived from this software |
| 23 | * without specific prior written permission. |
| 24 | * |
| 25 | * This software is provided "AS IS," without a warranty of any kind. |
| 26 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, |
| 27 | * INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A |
| 28 | * PARTICULAR PURPOSE OR NON-INFRINGEMENT, ARE HEREBY EXCLUDED. SUN |
| 29 | * MICROSYSTEMS, INC. ("SUN") AND ITS LICENSORS SHALL NOT BE LIABLE FOR |
| 30 | * ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, MODIFYING OR |
| 31 | * DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. IN NO EVENT WILL SUN |
| 32 | * OR ITS LICENSORS BE LIABLE FOR ANY LOST REVENUE, PROFIT OR DATA, OR |
| 33 | * FOR DIRECT, INDIRECT, SPECIAL, CONSEQUENTIAL, INCIDENTAL OR PUNITIVE |
| 34 | * DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, |
| 35 | * ARISING OUT OF THE USE OF OR INABILITY TO USE THIS SOFTWARE, EVEN IF |
| 36 | * SUN HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| 37 | * |
| 38 | * You acknowledge that this software is not designed, licensed or |
| 39 | * intended for use in the design, construction, operation or maintenance of |
| 40 | * any nuclear facility. |
| 41 | * |
| 42 | * ========== Copyright Header End ============================================ |
| 43 | */ |
| 44 | /* |
| 45 | * Copyright 2007 Sun Microsystems, Inc. All rights reserved. |
| 46 | * Use is subject to license terms. |
| 47 | */ |
| 48 | |
| 49 | #ifndef _PLATFORM_CACHE_H |
| 50 | #define _PLATFORM_CACHE_H |
| 51 | |
| 52 | #pragma ident "@(#)cache.h 1.3 07/06/27 SMI" |
| 53 | |
| 54 | #ifdef __cplusplus |
| 55 | extern "C" { |
| 56 | #endif |
| 57 | |
| 58 | #include <sys/htypes.h> |
| 59 | |
| 60 | /* |
| 61 | * L2 cache definitions |
| 62 | */ |
| 63 | #define L2_LINE_SHIFT 6 |
| 64 | #define L2_LINE_SIZE (1 << L2_LINE_SHIFT) |
| 65 | |
| 66 | #define L2_BANK_SHIFT 6 |
| 67 | #define L2_BANK_MASK 0x7 |
| 68 | #define L2_SET_SHIFT 9 |
| 69 | #define L2_SET_MASK 0x1ff |
| 70 | #define L2_WAY_SHIFT 18 |
| 71 | #define L2_WAY_MASK 0xF |
| 72 | #define NO_L2_BANKS 8 |
| 73 | #define L2_NUM_WAYS 16 |
| 74 | #define N_LONG_IN_LINE (L2_LINE_SIZE / SIZEOF_UI64) |
| 75 | |
| 76 | #define L2_BANK_SET \ |
| 77 | ((L2_BANK_MASK << L2_BANK_SHIFT) | \ |
| 78 | (L2_SET_MASK << L2_SET_SHIFT)) |
| 79 | |
| 80 | /* L2 Control Register definitions (Count 8 Step 64) */ |
| 81 | #define L2_CONTROL_REG (0xa9 << 32) |
| 82 | #define L2_DIS_SHIFT 0 |
| 83 | #define L2_DIS (1 << L2_DIS_SHIFT) |
| 84 | #define L2_DMMODE_SHIFT 1 |
| 85 | #define L2_DMMODE (1 << L2_DMMODE_SHIFT) |
| 86 | #define L2_SCRUBENABLE_SHIFT 2 |
| 87 | #define L2_SCRUBENABLE (1 << L2_SCRUBENABLE_SHIFT) |
| 88 | #define L2_SCRUBINTERVAL_SHIFT 3 |
| 89 | #define L2_SCRUBINTERVAL_MASK (0xfff << L2_SCRUBENABLE_SHIFT) |
| 90 | #define L2_ERRORSTEER_SHIFT 15 |
| 91 | #define L2_ERRORSTEER_MASK (0x3f << L2_ERRORSTEER_SHIFT) |
| 92 | |
| 93 | /* L2 Error Enable Register definitions (Count 8 Step 64) */ |
| 94 | #define L2_ERR_EN_BASE (0xaa << 32) |
| 95 | #define L2_NCEEN 0x2 |
| 96 | #define L2_CEEN 0x1 |
| 97 | |
| 98 | /* |
| 99 | * L2 Index Hash Enable Status |
| 100 | */ |
| 101 | #define L2_IDX_HASH_EN_STATUS 0x8000001038 |
| 102 | #define L2_IDX_HASH_EN_STATUS_MASK 0x1 |
| 103 | |
| 104 | /* |
| 105 | * L2 Bank Enable |
| 106 | */ |
| 107 | #define L2_BANK_ENABLE 0x8000001020 |
| 108 | #define L2_BANK_ENABLE_MASK 0xff |
| 109 | #define L2_BANK_ENABLE_SHIFT 0 |
| 110 | |
| 111 | /* |
| 112 | * L2 Bank Enable Status |
| 113 | */ |
| 114 | #define L2_BANK_ENABLE_STATUS 0x8000001028 |
| 115 | #define L2_BANK_ENABLE_STATUS_MASK 0xf |
| 116 | #define L2_BANK_ENABLE_STATUS_SHIFT 0 |
| 117 | |
| 118 | /* |
| 119 | * L2 Error Injector |
| 120 | */ |
| 121 | #define L2_ERROR_INJECTOR 0xad00000000 |
| 122 | #define L2_ERROR_INJECTOR_ENB_HP (1 << 0) |
| 123 | #define L2_ERROR_INJECTOR_SDSHOT (1 << 1) |
| 124 | |
| 125 | /* |
| 126 | * PrefetchICE Address Format |
| 127 | * |
| 128 | * +--------------------------------------+ |
| 129 | * | 64:40|39:37|36:22|21:18|17:9| 8:6|5:0| |
| 130 | * +--------------------------------------+ |
| 131 | * | - | key| - | way| set|bank| - | |
| 132 | * +--------------------------------------+ |
| 133 | * |
| 134 | * Note: If only 4 banks are enabled, set is bits [16:8] |
| 135 | * and bank is bits [7:6]. If 2 banks are enabled, |
| 136 | * set is bits [15:7] and bank is bit [6]. |
| 137 | */ |
| 138 | #define PREFETCHICE_KEY (0x3 << 37) |
| 139 | #define PREFETCHICE_WAY_SHIFT 18 |
| 140 | #define PREFETCHICE_WAY_MASK 0xf |
| 141 | #define PREFETCHICE_WAY_MAX \ |
| 142 | (PREFETCHICE_WAY_MASK << PREFETCHICE_WAY_SHIFT) |
| 143 | #define PREFETCHICE_SET_SHIFT 9 |
| 144 | #define PREFETCHICE_BANK_SET_MASK 0x1ff |
| 145 | #define PREFETCHICE_8BANK_SET_MAX \ |
| 146 | (PREFETCHICE_BANK_SET_MASK << PREFETCHICE_SET_SHIFT) |
| 147 | #define PREFETCHICE_4BANK_SET_MAX \ |
| 148 | (PREFETCHICE_BANK_SET_MASK << PREFETCHICE_SET_SHIFT - 1) |
| 149 | #define PREFETCHICE_2BANK_SET_MAX \ |
| 150 | (PREFETCHICE_BANK_SET_MASK << PREFETCHICE_SET_SHIFT - 2) |
| 151 | #define PREFETCHICE_BANK_SHIFT 6 |
| 152 | #define PREFETCHICE_8BANK_MASK 0x7 |
| 153 | #define PREFETCHICE_8BANK_MAX \ |
| 154 | (PREFETCHICE_8BANK_MASK << PREFETCHICE_BANK_SHIFT) |
| 155 | #define PREFETCHICE_4BANK_MASK 0x3 |
| 156 | #define PREFETCHICE_4BANK_MAX \ |
| 157 | (PREFETCHICE_4BANK_MASK << PREFETCHICE_BANK_SHIFT) |
| 158 | #define PREFETCHICE_2BANK_MASK 0x1 |
| 159 | #define PREFETCHICE_2BANK_MAX \ |
| 160 | (PREFETCHICE_2BANK_MASK << PREFETCHICE_BANK_SHIFT) |
| 161 | |
| 162 | /* |
| 163 | * The L2 cache cleanser is enabled and controlled by the following |
| 164 | * two HV MD properties: |
| 165 | * |
| 166 | * - L2_CACHE_CLEANSER_INTERVAL: |
| 167 | * controls the interval for the cyclic invocation of the cleanser |
| 168 | * |
| 169 | * - L2_CACHE_CLEANSER_ENTRIES: |
| 170 | * controls number of L2 entries to be cleansed per each invocation |
| 171 | * |
| 172 | * The default setting below will cycle through the entire L2 cache in |
| 173 | * 1000 seconds, with 10% of entries cleansed per each invocation on |
| 174 | * every 100 seconds |
| 175 | */ |
| 176 | #define L2_CACHE_ENTRIES 0x10000 /* 4Mb / 64b linesize */ |
| 177 | #define L2_CACHE_CLEANSER_INTERVAL 100 /* seconds */ |
| 178 | #define L2_CACHE_CLEANSER_ENTRIES 10 |
| 179 | |
| 180 | #define L2_TAG_DIAG_ECC_MASK 0x3f |
| 181 | |
| 182 | /* |
| 183 | * I/D Cache |
| 184 | */ |
| 185 | #define MAX_ICACHE_WAYS 8 |
| 186 | #define MAX_DCACHE_WAYS 4 |
| 187 | |
| 188 | /* BEGIN CSTYLED */ |
| 189 | #define SKIP_DISABLED_L2_BANK(bank, reg1, reg2, skip_label) \ |
| 190 | setx L2_BANK_ENABLE_STATUS, reg1, reg2 ;\ |
| 191 | ldx [reg2], reg2 ;\ |
| 192 | srlx reg2, L2_BANK_ENABLE_STATUS_SHIFT, reg2 ;\ |
| 193 | and reg2, L2_BANK_ENABLE_STATUS_MASK, reg2 ;\ |
| 194 | or %g0, bank, reg1 ;\ |
| 195 | srlx reg1, 1, reg1 ;\ |
| 196 | srlx reg2, reg1, reg2 ;\ |
| 197 | btst 1, reg2 ;\ |
| 198 | bz,pn %xcc, skip_label ;\ |
| 199 | nop ;\ |
| 200 | |
| 201 | #define N2_PERFORM_IDX_HASH(addr, lomask, himask) \ |
| 202 | mov 0x1f, himask ;\ |
| 203 | sllx himask, 28, himask ;\ |
| 204 | ;\ |
| 205 | mov 0x3, lomask ;\ |
| 206 | sllx lomask, L2_WAY_SHIFT, lomask ;\ |
| 207 | ;\ |
| 208 | and addr, himask, himask ;\ |
| 209 | and addr, lomask, lomask ;\ |
| 210 | ;\ |
| 211 | srlx himask, 15, himask ;\ |
| 212 | xor addr, himask, addr ;\ |
| 213 | ;\ |
| 214 | srlx lomask, 7, lomask ;\ |
| 215 | xor addr, lomask, addr |
| 216 | |
| 217 | /* END CSTYLED */ |
| 218 | |
| 219 | #ifdef __cplusplus |
| 220 | } |
| 221 | #endif |
| 222 | |
| 223 | #endif /* _PLATFORM_CACHE_H */ |