| 1 | <!-- interpreter=xml2reg args='-t' --> |
| 2 | <register_list> |
| 3 | <register name="DRAM_FBD_INJ_ERROR_SRC_REG (DRAM_FBD_INJ_ERROR_SRC_REG)"> |
| 4 | <class_name>N2_DramFbdInjectedErrSrcReg</class_name> |
| 5 | <submodule>N2</submodule> |
| 6 | <comment> |
| 7 | DRAM FBD Injected Error Source Register. When the NCU siganls the MCU |
| 8 | to inject an error, this register determines into which error |
| 9 | detection logic the error will be injected. |
| 10 | TABLE 12-38 shows the format of the DRAM FDB Injected Error Source |
| 11 | Register. TABLE 12-38 FBD Error Syndrome Register - DRAM_FBD_INJ_ERROR_SRC_REG (0x84-0000-0c08) (Count 4 Step 4096) |
| 12 | </comment> |
| 13 | <base_address>0x8400000c08ULL</base_address> |
| 14 | <count>4</count> |
| 15 | <stride>4096</stride> |
| 16 | <priv>yes</priv> |
| 17 | <public> |
| 18 | static const uint_t CRC_ERROR = 0; |
| 19 | static const uint_t ALERT_FRAME_ERROR = 1; |
| 20 | static const uint_t ALERT_ASSERTED = 2; |
| 21 | static const uint_t STATUS_FRAME_PARITY_ERROR = 3; |
| 22 | </public> |
| 23 | <field name="RSVD0"> |
| 24 | <start_offset>2</start_offset> |
| 25 | <end_offset>62</end_offset> |
| 26 | <initial_value>0</initial_value> |
| 27 | <protection>RO</protection> |
| 28 | <field_type>ZERO</field_type> |
| 29 | <comment> |
| 30 | Reserved |
| 31 | </comment> |
| 32 | </field> |
| 33 | <field name="ERRORSOURCE"> |
| 34 | <start_offset>0</start_offset> |
| 35 | <end_offset>1</end_offset> |
| 36 | <initial_value>0</initial_value> |
| 37 | <protection>RW</protection> |
| 38 | <field_type>NORMAL</field_type> |
| 39 | <comment> |
| 40 | Source of the Error. |
| 41 | 0: CRC Error |
| 42 | 1: Alert Frame Error |
| 43 | 2: Alert Asserted |
| 44 | 3: Status Frame Parity Error |
| 45 | </comment> |
| 46 | <format type="hex"/> |
| 47 | </field> |
| 48 | </register> |
| 49 | </register_list> |