| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: MemorySyncDefs.h |
| 5 | * Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
| 6 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
| 7 | * |
| 8 | * The above named program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public |
| 10 | * License version 2 as published by the Free Software Foundation. |
| 11 | * |
| 12 | * The above named program is distributed in the hope that it will be |
| 13 | * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public |
| 18 | * License along with this work; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
| 20 | * |
| 21 | * ========== Copyright Header End ============================================ |
| 22 | */ |
| 23 | #ifndef _MEMORYMODELDEFS_H |
| 24 | #define _MEMORYMODELDEFS_H |
| 25 | /************************************************************************ |
| 26 | ** |
| 27 | ** Copyright (C) 2002, Sun Microsystems, Inc. |
| 28 | ** |
| 29 | ** Sun considers its source code as an unpublished, proprietary |
| 30 | ** trade secret and it is available only under strict license provisions. |
| 31 | ** This copyright notice is placed here only to protect Sun in the event |
| 32 | ** the source is deemed a published work. Disassembly, decompilation, |
| 33 | ** or other means of reducing the object code to human readable form |
| 34 | ** is prohibited by the license agreement under which this code is |
| 35 | ** provided to the user or company in possession of this copy." |
| 36 | ** |
| 37 | *************************************************************************/ |
| 38 | #include "RieslingInterface.h" |
| 39 | |
| 40 | #define MAX_STRANDS RieslingInterface::max_strands |
| 41 | #define NSTRANDS_PER_CORE RieslingInterface::strands_per_core |
| 42 | |
| 43 | #define ICACHE_LINE_SIZE 32 |
| 44 | #define DCACHE_LINE_SIZE 16 |
| 45 | #define L2CACHE_LINE_SIZE 64 |
| 46 | |
| 47 | #define N_IFBUF_ENTRIES 16 |
| 48 | #define N_LDBUF_ENTRIES 16 |
| 49 | #define N_STBUF_ENTRIES 64 |
| 50 | |
| 51 | #ifdef PROC_KT |
| 52 | #define IO_ADDR_BIT_MASK 0x80000000000ull // bit 43 |
| 53 | #else // PROC_KT |
| 54 | #define IO_ADDR_BIT_MASK 0x8000000000ull // bit 39 |
| 55 | #endif // PROC_KT |
| 56 | #define L2_BANK_ADDR_BITS 0x1c0ull // bits 8:6 |
| 57 | #define L2_BANK_ADDR_SFT 6 // begins at bit 6 |
| 58 | |
| 59 | #define DATA_SIZE 8 |
| 60 | #define ADDR_MASK 0xfffffffffffffff8ull |
| 61 | #define FULL_ADDR_MASK 0xffffffffffffffffull |
| 62 | #define BLK_ADDR_MASK 0xfffffffffffffff8ull |
| 63 | #define QUAD_OP_ADDR_MASK 0xfffffffffffffff0ull |
| 64 | #define BLK_OP_ADDR_MASK 0xffffffffffffffc0ull |
| 65 | #ifdef PROC_KT |
| 66 | #define L2_CACHE_LINE_MASK 0x00000ffffffffff0ull // PA[43:4] |
| 67 | #else // PROC_KT |
| 68 | #define L2_CACHE_LINE_MASK 0x000000fffffffff0ull // PA[39:4] |
| 69 | #endif // PROC_KT |
| 70 | #define L1_CACHE_INDEX_MASK 0x00000000000007f0ull // PA[10:4] |
| 71 | #define INV_VEC_SIZE 16 |
| 72 | |
| 73 | /* typedef uint64_t cycle_t; */ |
| 74 | /* typedef uint64_t addr_t; */ |
| 75 | /* typedef uint64_t data_t; */ |
| 76 | /* typedef uint8_t size_t; */ |
| 77 | |
| 78 | enum INSTR_TYPE {ITYPE_NONE = 0, ITYPE_LOAD, ITYPE_BLOCK_LOAD, ITYPE_DOUBLE_LOAD, ITYPE_QUAD_LOAD, |
| 79 | ITYPE_PREFETCH, ITYPE_STORE, ITYPE_BLOCK_STORE, ITYPE_ATOMIC, ITYPE_STORE_INIT, |
| 80 | ITYPE_FETCH}; |
| 81 | |
| 82 | static char* mmitype[] = {(char*) "NA", (char*) "ld", (char*) "bl", (char*) "dl", (char*) "ql", |
| 83 | (char*) "pf", (char*) "st", (char*) "bs", (char*) "at", |
| 84 | (char*) "si", (char*) "if"}; |
| 85 | |
| 86 | /* Memory Operation Type */ |
| 87 | enum MEM_CMD {MEM_LOAD_ISSUE = 0, MEM_LOAD_DATA, MEM_LOAD_FILL, MEM_STORE_ISSUE, |
| 88 | MEM_STORE_COMMIT, MEM_STORE_INV, MEM_STORE_UPDATE, MEM_STORE_ACK, |
| 89 | MEM_EVICT, MEM_EVICT_INV, MEM_FETCH_ISSUE, MEM_FETCH_DATA, MEM_FETCH_FILL, |
| 90 | MEM_DMA_STORE, MEM_DMA_STORE_START, MAX_MEM_CMDS}; |
| 91 | |
| 92 | static char* mmcmd[] = {(char*) "LI", (char*) "LD", (char*) "LF", (char*) "SI", (char*) "SC", |
| 93 | (char*) "SV", (char*) "SU", (char*) "SA", (char*) "EV", (char*) "EI", |
| 94 | (char*) "FI", (char*) "FD", (char*) "FF", (char*) "DS", (char*) "DSS", |
| 95 | (char*) "NA"}; |
| 96 | |
| 97 | /* Load Data Sourece */ |
| 98 | enum DATA_SRC {DSRC_NONE = 0, DSRC_STB, DSRC_L1, DSRC_L2_MEMORY, DSRC_IO}; |
| 99 | |
| 100 | static char* mmdsrc[] = {(char*) "NA", (char*) "SB", (char*) "L1", (char*) "L2", (char*) "IO"}; |
| 101 | |
| 102 | /* buffer state */ |
| 103 | enum LS_ENTRY_STATE {LS_NEW = 0, LS_TDATA, LS_RDATA, LS_ISSUE, LS_ACK, LS_UPDATE, |
| 104 | LS_INV, LS_RETIRE}; |
| 105 | |
| 106 | static char* lstate[] = {(char*) "NEW", (char*) "TDT", (char*) "RDT", |
| 107 | (char*) "ISS", (char*) "ACK", (char*) "UPD", |
| 108 | (char*) "INV", (char*) "RET"}; |
| 109 | |
| 110 | /* DMA_STORE flags */ |
| 111 | enum DMA_STORE_ACT { DMA_STORE = 0, DMA_EVICT, DMA_EVICT_INV }; |
| 112 | |
| 113 | extern uint64_t rtlCycle; |
| 114 | |
| 115 | #endif /* _MEMORYMODELDEFS_H */ |